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Differential D94729

[RISCV][NFC] Fix order of parameters in cmov ge/le tests
ClosedPublic

Authored by mundaym on Jan 14 2021, 3:36 PM.

Details

Reviewers
luismarques
asb
Commits
rGbf1aa5db5c76: [RISCV][NFC] Fix order of parameters in cmov ge/le tests
Summary

The first parameter should be selected if the condition is true and
the last parameter if the condition is false. Prior to this change
it was the other way round which was confusing.

Diff Detail

Event Timeline

mundaym created this revision.Jan 14 2021, 3:36 PM
Herald added subscribers: frasercrmck, NickHung, evandro and 23 others. · View Herald TranscriptJan 14 2021, 3:36 PM
mundaym requested review of this revision.Jan 14 2021, 3:36 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 14 2021, 3:36 PM
Herald added subscribers: llvm-commits, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B85258: Diff 316797.Jan 14 2021, 4:13 PM
This revision was not accepted when it landed; it landed in state Needs Review.Jan 15 2021, 7:37 AM
Closed by commit rGbf1aa5db5c76: [RISCV][NFC] Fix order of parameters in cmov ge/le tests (authored by mundaym, committed by lenary). · Explain Why
This revision was automatically updated to reflect the committed changes.
lenary added a commit: rGbf1aa5db5c76: [RISCV][NFC] Fix order of parameters in cmov ge/le tests.

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
100 lines
88 lines

Diff 316948

llvm/test/CodeGen/RISCV/rv32Zbt.ll

Show First 20 Lines • Show All 85 Lines • ▼ Show 20 Lines; RV32IBT-NEXT: ret
ret i32 %cond ret i32 %cond
} }
define i32 @cmov_sle_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { define i32 @cmov_sle_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; RV32I-LABEL: cmov_sle_i32: ; RV32I-LABEL: cmov_sle_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: bge a2, a1, .LBB3_2 ; RV32I-NEXT: bge a2, a1, .LBB3_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a3, a0
; RV32I-NEXT: .LBB3_2:
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: .LBB3_2:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IB-LABEL: cmov_sle_i32: ; RV32IB-LABEL: cmov_sle_i32:
; RV32IB: # %bb.0: ; RV32IB: # %bb.0:
; RV32IB-NEXT: bge a2, a1, .LBB3_2 ; RV32IB-NEXT: bge a2, a1, .LBB3_2
; RV32IB-NEXT: # %bb.1: ; RV32IB-NEXT: # %bb.1:
; RV32IB-NEXT: mv a3, a0
; RV32IB-NEXT: .LBB3_2:
; RV32IB-NEXT: mv a0, a3 ; RV32IB-NEXT: mv a0, a3
; RV32IB-NEXT: .LBB3_2:
; RV32IB-NEXT: ret ; RV32IB-NEXT: ret
; ;
; RV32IBT-LABEL: cmov_sle_i32: ; RV32IBT-LABEL: cmov_sle_i32:
; RV32IBT: # %bb.0: ; RV32IBT: # %bb.0:
; RV32IBT-NEXT: bge a2, a1, .LBB3_2 ; RV32IBT-NEXT: bge a2, a1, .LBB3_2
; RV32IBT-NEXT: # %bb.1: ; RV32IBT-NEXT: # %bb.1:
; RV32IBT-NEXT: mv a3, a0
; RV32IBT-NEXT: .LBB3_2:
; RV32IBT-NEXT: mv a0, a3 ; RV32IBT-NEXT: mv a0, a3
; RV32IBT-NEXT: .LBB3_2:
; RV32IBT-NEXT: ret ; RV32IBT-NEXT: ret
%tobool = icmp sle i32 %b, %c %tobool = icmp sle i32 %b, %c
%cond = select i1 %tobool, i32 %d, i32 %a %cond = select i1 %tobool, i32 %a, i32 %d
ret i32 %cond ret i32 %cond
} }
define i32 @cmov_sge_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { define i32 @cmov_sge_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; RV32I-LABEL: cmov_sge_i32: ; RV32I-LABEL: cmov_sge_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: bge a1, a2, .LBB4_2 ; RV32I-NEXT: bge a1, a2, .LBB4_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a3, a0
; RV32I-NEXT: .LBB4_2:
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: .LBB4_2:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IB-LABEL: cmov_sge_i32: ; RV32IB-LABEL: cmov_sge_i32:
; RV32IB: # %bb.0: ; RV32IB: # %bb.0:
; RV32IB-NEXT: bge a1, a2, .LBB4_2 ; RV32IB-NEXT: bge a1, a2, .LBB4_2
; RV32IB-NEXT: # %bb.1: ; RV32IB-NEXT: # %bb.1:
; RV32IB-NEXT: mv a3, a0
; RV32IB-NEXT: .LBB4_2:
; RV32IB-NEXT: mv a0, a3 ; RV32IB-NEXT: mv a0, a3
; RV32IB-NEXT: .LBB4_2:
; RV32IB-NEXT: ret ; RV32IB-NEXT: ret
; ;
; RV32IBT-LABEL: cmov_sge_i32: ; RV32IBT-LABEL: cmov_sge_i32:
; RV32IBT: # %bb.0: ; RV32IBT: # %bb.0:
; RV32IBT-NEXT: bge a1, a2, .LBB4_2 ; RV32IBT-NEXT: bge a1, a2, .LBB4_2
; RV32IBT-NEXT: # %bb.1: ; RV32IBT-NEXT: # %bb.1:
; RV32IBT-NEXT: mv a3, a0
; RV32IBT-NEXT: .LBB4_2:
; RV32IBT-NEXT: mv a0, a3 ; RV32IBT-NEXT: mv a0, a3
; RV32IBT-NEXT: .LBB4_2:
; RV32IBT-NEXT: ret ; RV32IBT-NEXT: ret
%tobool = icmp sge i32 %b, %c %tobool = icmp sge i32 %b, %c
%cond = select i1 %tobool, i32 %d, i32 %a %cond = select i1 %tobool, i32 %a, i32 %d
ret i32 %cond ret i32 %cond
} }
define i32 @cmov_ule_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { define i32 @cmov_ule_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; RV32I-LABEL: cmov_ule_i32: ; RV32I-LABEL: cmov_ule_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: bgeu a2, a1, .LBB5_2 ; RV32I-NEXT: bgeu a2, a1, .LBB5_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a3, a0
; RV32I-NEXT: .LBB5_2:
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: .LBB5_2:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IB-LABEL: cmov_ule_i32: ; RV32IB-LABEL: cmov_ule_i32:
; RV32IB: # %bb.0: ; RV32IB: # %bb.0:
; RV32IB-NEXT: bgeu a2, a1, .LBB5_2 ; RV32IB-NEXT: bgeu a2, a1, .LBB5_2
; RV32IB-NEXT: # %bb.1: ; RV32IB-NEXT: # %bb.1:
; RV32IB-NEXT: mv a3, a0
; RV32IB-NEXT: .LBB5_2:
; RV32IB-NEXT: mv a0, a3 ; RV32IB-NEXT: mv a0, a3
; RV32IB-NEXT: .LBB5_2:
; RV32IB-NEXT: ret ; RV32IB-NEXT: ret
; ;
; RV32IBT-LABEL: cmov_ule_i32: ; RV32IBT-LABEL: cmov_ule_i32:
; RV32IBT: # %bb.0: ; RV32IBT: # %bb.0:
; RV32IBT-NEXT: bgeu a2, a1, .LBB5_2 ; RV32IBT-NEXT: bgeu a2, a1, .LBB5_2
; RV32IBT-NEXT: # %bb.1: ; RV32IBT-NEXT: # %bb.1:
; RV32IBT-NEXT: mv a3, a0
; RV32IBT-NEXT: .LBB5_2:
; RV32IBT-NEXT: mv a0, a3 ; RV32IBT-NEXT: mv a0, a3
; RV32IBT-NEXT: .LBB5_2:
; RV32IBT-NEXT: ret ; RV32IBT-NEXT: ret
%tobool = icmp ule i32 %b, %c %tobool = icmp ule i32 %b, %c
%cond = select i1 %tobool, i32 %d, i32 %a %cond = select i1 %tobool, i32 %a, i32 %d
ret i32 %cond ret i32 %cond
} }
define i32 @cmov_uge_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { define i32 @cmov_uge_i32(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; RV32I-LABEL: cmov_uge_i32: ; RV32I-LABEL: cmov_uge_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: bgeu a1, a2, .LBB6_2 ; RV32I-NEXT: bgeu a1, a2, .LBB6_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a3, a0
; RV32I-NEXT: .LBB6_2:
; RV32I-NEXT: mv a0, a3 ; RV32I-NEXT: mv a0, a3
; RV32I-NEXT: .LBB6_2:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IB-LABEL: cmov_uge_i32: ; RV32IB-LABEL: cmov_uge_i32:
; RV32IB: # %bb.0: ; RV32IB: # %bb.0:
; RV32IB-NEXT: bgeu a1, a2, .LBB6_2 ; RV32IB-NEXT: bgeu a1, a2, .LBB6_2
; RV32IB-NEXT: # %bb.1: ; RV32IB-NEXT: # %bb.1:
; RV32IB-NEXT: mv a3, a0
; RV32IB-NEXT: .LBB6_2:
; RV32IB-NEXT: mv a0, a3 ; RV32IB-NEXT: mv a0, a3
; RV32IB-NEXT: .LBB6_2:
; RV32IB-NEXT: ret ; RV32IB-NEXT: ret
; ;
; RV32IBT-LABEL: cmov_uge_i32: ; RV32IBT-LABEL: cmov_uge_i32:
; RV32IBT: # %bb.0: ; RV32IBT: # %bb.0:
; RV32IBT-NEXT: bgeu a1, a2, .LBB6_2 ; RV32IBT-NEXT: bgeu a1, a2, .LBB6_2
; RV32IBT-NEXT: # %bb.1: ; RV32IBT-NEXT: # %bb.1:
; RV32IBT-NEXT: mv a3, a0
; RV32IBT-NEXT: .LBB6_2:
; RV32IBT-NEXT: mv a0, a3 ; RV32IBT-NEXT: mv a0, a3
; RV32IBT-NEXT: .LBB6_2:
; RV32IBT-NEXT: ret ; RV32IBT-NEXT: ret
%tobool = icmp uge i32 %b, %c %tobool = icmp uge i32 %b, %c
%cond = select i1 %tobool, i32 %d, i32 %a %cond = select i1 %tobool, i32 %a, i32 %d
ret i32 %cond ret i32 %cond
} }
define i64 @cmov_i64(i64 %a, i64 %b, i64 %c) nounwind { define i64 @cmov_i64(i64 %a, i64 %b, i64 %c) nounwind {
; RV32I-LABEL: cmov_i64: ; RV32I-LABEL: cmov_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: or a2, a2, a3 ; RV32I-NEXT: or a2, a2, a3
; RV32I-NEXT: beqz a2, .LBB7_2 ; RV32I-NEXT: beqz a2, .LBB7_2
Show All 32 Lines
; RV32I-NEXT: xori a2, a2, 1 ; RV32I-NEXT: xori a2, a2, 1
; RV32I-NEXT: beqz a2, .LBB8_3 ; RV32I-NEXT: beqz a2, .LBB8_3
; RV32I-NEXT: j .LBB8_4 ; RV32I-NEXT: j .LBB8_4
; RV32I-NEXT: .LBB8_2: ; RV32I-NEXT: .LBB8_2:
; RV32I-NEXT: sltu a2, a4, a2 ; RV32I-NEXT: sltu a2, a4, a2
; RV32I-NEXT: xori a2, a2, 1 ; RV32I-NEXT: xori a2, a2, 1
; RV32I-NEXT: bnez a2, .LBB8_4 ; RV32I-NEXT: bnez a2, .LBB8_4
; RV32I-NEXT: .LBB8_3: ; RV32I-NEXT: .LBB8_3:
; RV32I-NEXT: mv a6, a0
; RV32I-NEXT: mv a7, a1
; RV32I-NEXT: .LBB8_4:
; RV32I-NEXT: mv a0, a6 ; RV32I-NEXT: mv a0, a6
; RV32I-NEXT: mv a1, a7 ; RV32I-NEXT: mv a1, a7
; RV32I-NEXT: .LBB8_4:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IB-LABEL: cmov_sle_i64: ; RV32IB-LABEL: cmov_sle_i64:
; RV32IB: # %bb.0: ; RV32IB: # %bb.0:
; RV32IB-NEXT: beq a3, a5, .LBB8_2 ; RV32IB-NEXT: beq a3, a5, .LBB8_2
; RV32IB-NEXT: # %bb.1: ; RV32IB-NEXT: # %bb.1:
; RV32IB-NEXT: slt a2, a5, a3 ; RV32IB-NEXT: slt a2, a5, a3
; RV32IB-NEXT: xori a2, a2, 1 ; RV32IB-NEXT: xori a2, a2, 1
; RV32IB-NEXT: beqz a2, .LBB8_3 ; RV32IB-NEXT: beqz a2, .LBB8_3
; RV32IB-NEXT: j .LBB8_4 ; RV32IB-NEXT: j .LBB8_4
; RV32IB-NEXT: .LBB8_2: ; RV32IB-NEXT: .LBB8_2:
; RV32IB-NEXT: sltu a2, a4, a2 ; RV32IB-NEXT: sltu a2, a4, a2
; RV32IB-NEXT: xori a2, a2, 1 ; RV32IB-NEXT: xori a2, a2, 1
; RV32IB-NEXT: bnez a2, .LBB8_4 ; RV32IB-NEXT: bnez a2, .LBB8_4
; RV32IB-NEXT: .LBB8_3: ; RV32IB-NEXT: .LBB8_3:
; RV32IB-NEXT: mv a6, a0
; RV32IB-NEXT: mv a7, a1
; RV32IB-NEXT: .LBB8_4:
; RV32IB-NEXT: mv a0, a6 ; RV32IB-NEXT: mv a0, a6
; RV32IB-NEXT: mv a1, a7 ; RV32IB-NEXT: mv a1, a7
; RV32IB-NEXT: .LBB8_4:
; RV32IB-NEXT: ret ; RV32IB-NEXT: ret
; ;
; RV32IBT-LABEL: cmov_sle_i64: ; RV32IBT-LABEL: cmov_sle_i64:
; RV32IBT: # %bb.0: ; RV32IBT: # %bb.0:
; RV32IBT-NEXT: beq a3, a5, .LBB8_2 ; RV32IBT-NEXT: beq a3, a5, .LBB8_2
; RV32IBT-NEXT: # %bb.1: ; RV32IBT-NEXT: # %bb.1:
; RV32IBT-NEXT: slt a2, a5, a3 ; RV32IBT-NEXT: slt a2, a5, a3
; RV32IBT-NEXT: xori a2, a2, 1 ; RV32IBT-NEXT: xori a2, a2, 1
; RV32IBT-NEXT: beqz a2, .LBB8_3 ; RV32IBT-NEXT: beqz a2, .LBB8_3
; RV32IBT-NEXT: j .LBB8_4 ; RV32IBT-NEXT: j .LBB8_4
; RV32IBT-NEXT: .LBB8_2: ; RV32IBT-NEXT: .LBB8_2:
; RV32IBT-NEXT: sltu a2, a4, a2 ; RV32IBT-NEXT: sltu a2, a4, a2
; RV32IBT-NEXT: xori a2, a2, 1 ; RV32IBT-NEXT: xori a2, a2, 1
; RV32IBT-NEXT: bnez a2, .LBB8_4 ; RV32IBT-NEXT: bnez a2, .LBB8_4
; RV32IBT-NEXT: .LBB8_3: ; RV32IBT-NEXT: .LBB8_3:
; RV32IBT-NEXT: mv a6, a0
; RV32IBT-NEXT: mv a7, a1
; RV32IBT-NEXT: .LBB8_4:
; RV32IBT-NEXT: mv a0, a6 ; RV32IBT-NEXT: mv a0, a6
; RV32IBT-NEXT: mv a1, a7 ; RV32IBT-NEXT: mv a1, a7
; RV32IBT-NEXT: .LBB8_4:
; RV32IBT-NEXT: ret ; RV32IBT-NEXT: ret
%tobool = icmp sle i64 %b, %c %tobool = icmp sle i64 %b, %c
%cond = select i1 %tobool, i64 %d, i64 %a %cond = select i1 %tobool, i64 %a, i64 %d
ret i64 %cond ret i64 %cond
} }
define i64 @cmov_sge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind { define i64 @cmov_sge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV32I-LABEL: cmov_sge_i64: ; RV32I-LABEL: cmov_sge_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: beq a3, a5, .LBB9_2 ; RV32I-NEXT: beq a3, a5, .LBB9_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: slt a2, a3, a5 ; RV32I-NEXT: slt a2, a3, a5
; RV32I-NEXT: xori a2, a2, 1 ; RV32I-NEXT: xori a2, a2, 1
; RV32I-NEXT: beqz a2, .LBB9_3 ; RV32I-NEXT: beqz a2, .LBB9_3
; RV32I-NEXT: j .LBB9_4 ; RV32I-NEXT: j .LBB9_4
; RV32I-NEXT: .LBB9_2: ; RV32I-NEXT: .LBB9_2:
; RV32I-NEXT: sltu a2, a2, a4 ; RV32I-NEXT: sltu a2, a2, a4
; RV32I-NEXT: xori a2, a2, 1 ; RV32I-NEXT: xori a2, a2, 1
; RV32I-NEXT: bnez a2, .LBB9_4 ; RV32I-NEXT: bnez a2, .LBB9_4
; RV32I-NEXT: .LBB9_3: ; RV32I-NEXT: .LBB9_3:
; RV32I-NEXT: mv a6, a0
; RV32I-NEXT: mv a7, a1
; RV32I-NEXT: .LBB9_4:
; RV32I-NEXT: mv a0, a6 ; RV32I-NEXT: mv a0, a6
; RV32I-NEXT: mv a1, a7 ; RV32I-NEXT: mv a1, a7
; RV32I-NEXT: .LBB9_4:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IB-LABEL: cmov_sge_i64: ; RV32IB-LABEL: cmov_sge_i64:
; RV32IB: # %bb.0: ; RV32IB: # %bb.0:
; RV32IB-NEXT: beq a3, a5, .LBB9_2 ; RV32IB-NEXT: beq a3, a5, .LBB9_2
; RV32IB-NEXT: # %bb.1: ; RV32IB-NEXT: # %bb.1:
; RV32IB-NEXT: slt a2, a3, a5 ; RV32IB-NEXT: slt a2, a3, a5
; RV32IB-NEXT: xori a2, a2, 1 ; RV32IB-NEXT: xori a2, a2, 1
; RV32IB-NEXT: beqz a2, .LBB9_3 ; RV32IB-NEXT: beqz a2, .LBB9_3
; RV32IB-NEXT: j .LBB9_4 ; RV32IB-NEXT: j .LBB9_4
; RV32IB-NEXT: .LBB9_2: ; RV32IB-NEXT: .LBB9_2:
; RV32IB-NEXT: sltu a2, a2, a4 ; RV32IB-NEXT: sltu a2, a2, a4
; RV32IB-NEXT: xori a2, a2, 1 ; RV32IB-NEXT: xori a2, a2, 1
; RV32IB-NEXT: bnez a2, .LBB9_4 ; RV32IB-NEXT: bnez a2, .LBB9_4
; RV32IB-NEXT: .LBB9_3: ; RV32IB-NEXT: .LBB9_3:
; RV32IB-NEXT: mv a6, a0
; RV32IB-NEXT: mv a7, a1
; RV32IB-NEXT: .LBB9_4:
; RV32IB-NEXT: mv a0, a6 ; RV32IB-NEXT: mv a0, a6
; RV32IB-NEXT: mv a1, a7 ; RV32IB-NEXT: mv a1, a7
; RV32IB-NEXT: .LBB9_4:
; RV32IB-NEXT: ret ; RV32IB-NEXT: ret
; ;
; RV32IBT-LABEL: cmov_sge_i64: ; RV32IBT-LABEL: cmov_sge_i64:
; RV32IBT: # %bb.0: ; RV32IBT: # %bb.0:
; RV32IBT-NEXT: beq a3, a5, .LBB9_2 ; RV32IBT-NEXT: beq a3, a5, .LBB9_2
; RV32IBT-NEXT: # %bb.1: ; RV32IBT-NEXT: # %bb.1:
; RV32IBT-NEXT: slt a2, a3, a5 ; RV32IBT-NEXT: slt a2, a3, a5
; RV32IBT-NEXT: xori a2, a2, 1 ; RV32IBT-NEXT: xori a2, a2, 1
; RV32IBT-NEXT: beqz a2, .LBB9_3 ; RV32IBT-NEXT: beqz a2, .LBB9_3
; RV32IBT-NEXT: j .LBB9_4 ; RV32IBT-NEXT: j .LBB9_4
; RV32IBT-NEXT: .LBB9_2: ; RV32IBT-NEXT: .LBB9_2:
; RV32IBT-NEXT: sltu a2, a2, a4 ; RV32IBT-NEXT: sltu a2, a2, a4
; RV32IBT-NEXT: xori a2, a2, 1 ; RV32IBT-NEXT: xori a2, a2, 1
; RV32IBT-NEXT: bnez a2, .LBB9_4 ; RV32IBT-NEXT: bnez a2, .LBB9_4
; RV32IBT-NEXT: .LBB9_3: ; RV32IBT-NEXT: .LBB9_3:
; RV32IBT-NEXT: mv a6, a0
; RV32IBT-NEXT: mv a7, a1
; RV32IBT-NEXT: .LBB9_4:
; RV32IBT-NEXT: mv a0, a6 ; RV32IBT-NEXT: mv a0, a6
; RV32IBT-NEXT: mv a1, a7 ; RV32IBT-NEXT: mv a1, a7
; RV32IBT-NEXT: .LBB9_4:
; RV32IBT-NEXT: ret ; RV32IBT-NEXT: ret
%tobool = icmp sge i64 %b, %c %tobool = icmp sge i64 %b, %c
%cond = select i1 %tobool, i64 %d, i64 %a %cond = select i1 %tobool, i64 %a, i64 %d
ret i64 %cond ret i64 %cond
} }
define i64 @cmov_ule_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind { define i64 @cmov_ule_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV32I-LABEL: cmov_ule_i64: ; RV32I-LABEL: cmov_ule_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: beq a3, a5, .LBB10_2 ; RV32I-NEXT: beq a3, a5, .LBB10_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu a2, a5, a3 ; RV32I-NEXT: sltu a2, a5, a3
; RV32I-NEXT: xori a2, a2, 1 ; RV32I-NEXT: xori a2, a2, 1
; RV32I-NEXT: beqz a2, .LBB10_3 ; RV32I-NEXT: beqz a2, .LBB10_3
; RV32I-NEXT: j .LBB10_4 ; RV32I-NEXT: j .LBB10_4
; RV32I-NEXT: .LBB10_2: ; RV32I-NEXT: .LBB10_2:
; RV32I-NEXT: sltu a2, a4, a2 ; RV32I-NEXT: sltu a2, a4, a2
; RV32I-NEXT: xori a2, a2, 1 ; RV32I-NEXT: xori a2, a2, 1
; RV32I-NEXT: bnez a2, .LBB10_4 ; RV32I-NEXT: bnez a2, .LBB10_4
; RV32I-NEXT: .LBB10_3: ; RV32I-NEXT: .LBB10_3:
; RV32I-NEXT: mv a6, a0
; RV32I-NEXT: mv a7, a1
; RV32I-NEXT: .LBB10_4:
; RV32I-NEXT: mv a0, a6 ; RV32I-NEXT: mv a0, a6
; RV32I-NEXT: mv a1, a7 ; RV32I-NEXT: mv a1, a7
; RV32I-NEXT: .LBB10_4:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IB-LABEL: cmov_ule_i64: ; RV32IB-LABEL: cmov_ule_i64:
; RV32IB: # %bb.0: ; RV32IB: # %bb.0:
; RV32IB-NEXT: beq a3, a5, .LBB10_2 ; RV32IB-NEXT: beq a3, a5, .LBB10_2
; RV32IB-NEXT: # %bb.1: ; RV32IB-NEXT: # %bb.1:
; RV32IB-NEXT: sltu a2, a5, a3 ; RV32IB-NEXT: sltu a2, a5, a3
; RV32IB-NEXT: xori a2, a2, 1 ; RV32IB-NEXT: xori a2, a2, 1
; RV32IB-NEXT: beqz a2, .LBB10_3 ; RV32IB-NEXT: beqz a2, .LBB10_3
; RV32IB-NEXT: j .LBB10_4 ; RV32IB-NEXT: j .LBB10_4
; RV32IB-NEXT: .LBB10_2: ; RV32IB-NEXT: .LBB10_2:
; RV32IB-NEXT: sltu a2, a4, a2 ; RV32IB-NEXT: sltu a2, a4, a2
; RV32IB-NEXT: xori a2, a2, 1 ; RV32IB-NEXT: xori a2, a2, 1
; RV32IB-NEXT: bnez a2, .LBB10_4 ; RV32IB-NEXT: bnez a2, .LBB10_4
; RV32IB-NEXT: .LBB10_3: ; RV32IB-NEXT: .LBB10_3:
; RV32IB-NEXT: mv a6, a0
; RV32IB-NEXT: mv a7, a1
; RV32IB-NEXT: .LBB10_4:
; RV32IB-NEXT: mv a0, a6 ; RV32IB-NEXT: mv a0, a6
; RV32IB-NEXT: mv a1, a7 ; RV32IB-NEXT: mv a1, a7
; RV32IB-NEXT: .LBB10_4:
; RV32IB-NEXT: ret ; RV32IB-NEXT: ret
; ;
; RV32IBT-LABEL: cmov_ule_i64: ; RV32IBT-LABEL: cmov_ule_i64:
; RV32IBT: # %bb.0: ; RV32IBT: # %bb.0:
; RV32IBT-NEXT: beq a3, a5, .LBB10_2 ; RV32IBT-NEXT: beq a3, a5, .LBB10_2
; RV32IBT-NEXT: # %bb.1: ; RV32IBT-NEXT: # %bb.1:
; RV32IBT-NEXT: sltu a2, a5, a3 ; RV32IBT-NEXT: sltu a2, a5, a3
; RV32IBT-NEXT: xori a2, a2, 1 ; RV32IBT-NEXT: xori a2, a2, 1
; RV32IBT-NEXT: beqz a2, .LBB10_3 ; RV32IBT-NEXT: beqz a2, .LBB10_3
; RV32IBT-NEXT: j .LBB10_4 ; RV32IBT-NEXT: j .LBB10_4
; RV32IBT-NEXT: .LBB10_2: ; RV32IBT-NEXT: .LBB10_2:
; RV32IBT-NEXT: sltu a2, a4, a2 ; RV32IBT-NEXT: sltu a2, a4, a2
; RV32IBT-NEXT: xori a2, a2, 1 ; RV32IBT-NEXT: xori a2, a2, 1
; RV32IBT-NEXT: bnez a2, .LBB10_4 ; RV32IBT-NEXT: bnez a2, .LBB10_4
; RV32IBT-NEXT: .LBB10_3: ; RV32IBT-NEXT: .LBB10_3:
; RV32IBT-NEXT: mv a6, a0
; RV32IBT-NEXT: mv a7, a1
; RV32IBT-NEXT: .LBB10_4:
; RV32IBT-NEXT: mv a0, a6 ; RV32IBT-NEXT: mv a0, a6
; RV32IBT-NEXT: mv a1, a7 ; RV32IBT-NEXT: mv a1, a7
; RV32IBT-NEXT: .LBB10_4:
; RV32IBT-NEXT: ret ; RV32IBT-NEXT: ret
%tobool = icmp ule i64 %b, %c %tobool = icmp ule i64 %b, %c
%cond = select i1 %tobool, i64 %d, i64 %a %cond = select i1 %tobool, i64 %a, i64 %d
ret i64 %cond ret i64 %cond
} }
define i64 @cmov_uge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind { define i64 @cmov_uge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV32I-LABEL: cmov_uge_i64: ; RV32I-LABEL: cmov_uge_i64:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: beq a3, a5, .LBB11_2 ; RV32I-NEXT: beq a3, a5, .LBB11_2
; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu a2, a3, a5 ; RV32I-NEXT: sltu a2, a3, a5
; RV32I-NEXT: xori a2, a2, 1 ; RV32I-NEXT: xori a2, a2, 1
; RV32I-NEXT: beqz a2, .LBB11_3 ; RV32I-NEXT: beqz a2, .LBB11_3
; RV32I-NEXT: j .LBB11_4 ; RV32I-NEXT: j .LBB11_4
; RV32I-NEXT: .LBB11_2: ; RV32I-NEXT: .LBB11_2:
; RV32I-NEXT: sltu a2, a2, a4 ; RV32I-NEXT: sltu a2, a2, a4
; RV32I-NEXT: xori a2, a2, 1 ; RV32I-NEXT: xori a2, a2, 1
; RV32I-NEXT: bnez a2, .LBB11_4 ; RV32I-NEXT: bnez a2, .LBB11_4
; RV32I-NEXT: .LBB11_3: ; RV32I-NEXT: .LBB11_3:
; RV32I-NEXT: mv a6, a0
; RV32I-NEXT: mv a7, a1
; RV32I-NEXT: .LBB11_4:
; RV32I-NEXT: mv a0, a6 ; RV32I-NEXT: mv a0, a6
; RV32I-NEXT: mv a1, a7 ; RV32I-NEXT: mv a1, a7
; RV32I-NEXT: .LBB11_4:
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV32IB-LABEL: cmov_uge_i64: ; RV32IB-LABEL: cmov_uge_i64:
; RV32IB: # %bb.0: ; RV32IB: # %bb.0:
; RV32IB-NEXT: beq a3, a5, .LBB11_2 ; RV32IB-NEXT: beq a3, a5, .LBB11_2
; RV32IB-NEXT: # %bb.1: ; RV32IB-NEXT: # %bb.1:
; RV32IB-NEXT: sltu a2, a3, a5 ; RV32IB-NEXT: sltu a2, a3, a5
; RV32IB-NEXT: xori a2, a2, 1 ; RV32IB-NEXT: xori a2, a2, 1
; RV32IB-NEXT: beqz a2, .LBB11_3 ; RV32IB-NEXT: beqz a2, .LBB11_3
; RV32IB-NEXT: j .LBB11_4 ; RV32IB-NEXT: j .LBB11_4
; RV32IB-NEXT: .LBB11_2: ; RV32IB-NEXT: .LBB11_2:
; RV32IB-NEXT: sltu a2, a2, a4 ; RV32IB-NEXT: sltu a2, a2, a4
; RV32IB-NEXT: xori a2, a2, 1 ; RV32IB-NEXT: xori a2, a2, 1
; RV32IB-NEXT: bnez a2, .LBB11_4 ; RV32IB-NEXT: bnez a2, .LBB11_4
; RV32IB-NEXT: .LBB11_3: ; RV32IB-NEXT: .LBB11_3:
; RV32IB-NEXT: mv a6, a0
; RV32IB-NEXT: mv a7, a1
; RV32IB-NEXT: .LBB11_4:
; RV32IB-NEXT: mv a0, a6 ; RV32IB-NEXT: mv a0, a6
; RV32IB-NEXT: mv a1, a7 ; RV32IB-NEXT: mv a1, a7
; RV32IB-NEXT: .LBB11_4:
; RV32IB-NEXT: ret ; RV32IB-NEXT: ret
; ;
; RV32IBT-LABEL: cmov_uge_i64: ; RV32IBT-LABEL: cmov_uge_i64:
; RV32IBT: # %bb.0: ; RV32IBT: # %bb.0:
; RV32IBT-NEXT: beq a3, a5, .LBB11_2 ; RV32IBT-NEXT: beq a3, a5, .LBB11_2
; RV32IBT-NEXT: # %bb.1: ; RV32IBT-NEXT: # %bb.1:
; RV32IBT-NEXT: sltu a2, a3, a5 ; RV32IBT-NEXT: sltu a2, a3, a5
; RV32IBT-NEXT: xori a2, a2, 1 ; RV32IBT-NEXT: xori a2, a2, 1
; RV32IBT-NEXT: beqz a2, .LBB11_3 ; RV32IBT-NEXT: beqz a2, .LBB11_3
; RV32IBT-NEXT: j .LBB11_4 ; RV32IBT-NEXT: j .LBB11_4
; RV32IBT-NEXT: .LBB11_2: ; RV32IBT-NEXT: .LBB11_2:
; RV32IBT-NEXT: sltu a2, a2, a4 ; RV32IBT-NEXT: sltu a2, a2, a4
; RV32IBT-NEXT: xori a2, a2, 1 ; RV32IBT-NEXT: xori a2, a2, 1
; RV32IBT-NEXT: bnez a2, .LBB11_4 ; RV32IBT-NEXT: bnez a2, .LBB11_4
; RV32IBT-NEXT: .LBB11_3: ; RV32IBT-NEXT: .LBB11_3:
; RV32IBT-NEXT: mv a6, a0
; RV32IBT-NEXT: mv a7, a1
; RV32IBT-NEXT: .LBB11_4:
; RV32IBT-NEXT: mv a0, a6 ; RV32IBT-NEXT: mv a0, a6
; RV32IBT-NEXT: mv a1, a7 ; RV32IBT-NEXT: mv a1, a7
; RV32IBT-NEXT: .LBB11_4:
; RV32IBT-NEXT: ret ; RV32IBT-NEXT: ret
%tobool = icmp uge i64 %b, %c %tobool = icmp uge i64 %b, %c
%cond = select i1 %tobool, i64 %d, i64 %a %cond = select i1 %tobool, i64 %a, i64 %d
ret i64 %cond ret i64 %cond
} }
declare i32 @llvm.fshl.i32(i32, i32, i32) declare i32 @llvm.fshl.i32(i32, i32, i32)
define i32 @fshl_i32(i32 %a, i32 %b, i32 %c) nounwind { define i32 @fshl_i32(i32 %a, i32 %b, i32 %c) nounwind {
; RV32I-LABEL: fshl_i32: ; RV32I-LABEL: fshl_i32:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
▲ Show 20 Lines • Show All 470 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rv64Zbt.ll

Show First 20 Lines • Show All 79 Lines • ▼ Show 20 Lines; RV64IBT-NEXT: ret
ret i32 %cond ret i32 %cond
} }
define signext i32 @cmov_sle_i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind { define signext i32 @cmov_sle_i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
; RV64I-LABEL: cmov_sle_i32: ; RV64I-LABEL: cmov_sle_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bge a2, a1, .LBB3_2 ; RV64I-NEXT: bge a2, a1, .LBB3_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a3, a0
; RV64I-NEXT: .LBB3_2:
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB3_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IB-LABEL: cmov_sle_i32: ; RV64IB-LABEL: cmov_sle_i32:
; RV64IB: # %bb.0: ; RV64IB: # %bb.0:
; RV64IB-NEXT: bge a2, a1, .LBB3_2 ; RV64IB-NEXT: bge a2, a1, .LBB3_2
; RV64IB-NEXT: # %bb.1: ; RV64IB-NEXT: # %bb.1:
; RV64IB-NEXT: mv a3, a0
; RV64IB-NEXT: .LBB3_2:
; RV64IB-NEXT: mv a0, a3 ; RV64IB-NEXT: mv a0, a3
; RV64IB-NEXT: .LBB3_2:
; RV64IB-NEXT: ret ; RV64IB-NEXT: ret
; ;
; RV64IBT-LABEL: cmov_sle_i32: ; RV64IBT-LABEL: cmov_sle_i32:
; RV64IBT: # %bb.0: ; RV64IBT: # %bb.0:
; RV64IBT-NEXT: bge a2, a1, .LBB3_2 ; RV64IBT-NEXT: bge a2, a1, .LBB3_2
; RV64IBT-NEXT: # %bb.1: ; RV64IBT-NEXT: # %bb.1:
; RV64IBT-NEXT: mv a3, a0
; RV64IBT-NEXT: .LBB3_2:
; RV64IBT-NEXT: mv a0, a3 ; RV64IBT-NEXT: mv a0, a3
; RV64IBT-NEXT: .LBB3_2:
; RV64IBT-NEXT: ret ; RV64IBT-NEXT: ret
%tobool = icmp sle i32 %b, %c %tobool = icmp sle i32 %b, %c
%cond = select i1 %tobool, i32 %d, i32 %a %cond = select i1 %tobool, i32 %a, i32 %d
ret i32 %cond ret i32 %cond
} }
define signext i32 @cmov_sge_i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind { define signext i32 @cmov_sge_i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
; RV64I-LABEL: cmov_sge_i32: ; RV64I-LABEL: cmov_sge_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bge a1, a2, .LBB4_2 ; RV64I-NEXT: bge a1, a2, .LBB4_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a3, a0
; RV64I-NEXT: .LBB4_2:
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB4_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IB-LABEL: cmov_sge_i32: ; RV64IB-LABEL: cmov_sge_i32:
; RV64IB: # %bb.0: ; RV64IB: # %bb.0:
; RV64IB-NEXT: bge a1, a2, .LBB4_2 ; RV64IB-NEXT: bge a1, a2, .LBB4_2
; RV64IB-NEXT: # %bb.1: ; RV64IB-NEXT: # %bb.1:
; RV64IB-NEXT: mv a3, a0
; RV64IB-NEXT: .LBB4_2:
; RV64IB-NEXT: mv a0, a3 ; RV64IB-NEXT: mv a0, a3
; RV64IB-NEXT: .LBB4_2:
; RV64IB-NEXT: ret ; RV64IB-NEXT: ret
; ;
; RV64IBT-LABEL: cmov_sge_i32: ; RV64IBT-LABEL: cmov_sge_i32:
; RV64IBT: # %bb.0: ; RV64IBT: # %bb.0:
; RV64IBT-NEXT: bge a1, a2, .LBB4_2 ; RV64IBT-NEXT: bge a1, a2, .LBB4_2
; RV64IBT-NEXT: # %bb.1: ; RV64IBT-NEXT: # %bb.1:
; RV64IBT-NEXT: mv a3, a0
; RV64IBT-NEXT: .LBB4_2:
; RV64IBT-NEXT: mv a0, a3 ; RV64IBT-NEXT: mv a0, a3
; RV64IBT-NEXT: .LBB4_2:
; RV64IBT-NEXT: ret ; RV64IBT-NEXT: ret
%tobool = icmp sge i32 %b, %c %tobool = icmp sge i32 %b, %c
%cond = select i1 %tobool, i32 %d, i32 %a %cond = select i1 %tobool, i32 %a, i32 %d
ret i32 %cond ret i32 %cond
} }
define signext i32 @cmov_ule_i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind { define signext i32 @cmov_ule_i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
; RV64I-LABEL: cmov_ule_i32: ; RV64I-LABEL: cmov_ule_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bgeu a2, a1, .LBB5_2 ; RV64I-NEXT: bgeu a2, a1, .LBB5_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a3, a0
; RV64I-NEXT: .LBB5_2:
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB5_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IB-LABEL: cmov_ule_i32: ; RV64IB-LABEL: cmov_ule_i32:
; RV64IB: # %bb.0: ; RV64IB: # %bb.0:
; RV64IB-NEXT: bgeu a2, a1, .LBB5_2 ; RV64IB-NEXT: bgeu a2, a1, .LBB5_2
; RV64IB-NEXT: # %bb.1: ; RV64IB-NEXT: # %bb.1:
; RV64IB-NEXT: mv a3, a0
; RV64IB-NEXT: .LBB5_2:
; RV64IB-NEXT: mv a0, a3 ; RV64IB-NEXT: mv a0, a3
; RV64IB-NEXT: .LBB5_2:
; RV64IB-NEXT: ret ; RV64IB-NEXT: ret
; ;
; RV64IBT-LABEL: cmov_ule_i32: ; RV64IBT-LABEL: cmov_ule_i32:
; RV64IBT: # %bb.0: ; RV64IBT: # %bb.0:
; RV64IBT-NEXT: bgeu a2, a1, .LBB5_2 ; RV64IBT-NEXT: bgeu a2, a1, .LBB5_2
; RV64IBT-NEXT: # %bb.1: ; RV64IBT-NEXT: # %bb.1:
; RV64IBT-NEXT: mv a3, a0
; RV64IBT-NEXT: .LBB5_2:
; RV64IBT-NEXT: mv a0, a3 ; RV64IBT-NEXT: mv a0, a3
; RV64IBT-NEXT: .LBB5_2:
; RV64IBT-NEXT: ret ; RV64IBT-NEXT: ret
%tobool = icmp ule i32 %b, %c %tobool = icmp ule i32 %b, %c
%cond = select i1 %tobool, i32 %d, i32 %a %cond = select i1 %tobool, i32 %a, i32 %d
ret i32 %cond ret i32 %cond
} }
define signext i32 @cmov_uge_i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind { define signext i32 @cmov_uge_i32(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
; RV64I-LABEL: cmov_uge_i32: ; RV64I-LABEL: cmov_uge_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bgeu a1, a2, .LBB6_2 ; RV64I-NEXT: bgeu a1, a2, .LBB6_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a3, a0
; RV64I-NEXT: .LBB6_2:
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB6_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IB-LABEL: cmov_uge_i32: ; RV64IB-LABEL: cmov_uge_i32:
; RV64IB: # %bb.0: ; RV64IB: # %bb.0:
; RV64IB-NEXT: bgeu a1, a2, .LBB6_2 ; RV64IB-NEXT: bgeu a1, a2, .LBB6_2
; RV64IB-NEXT: # %bb.1: ; RV64IB-NEXT: # %bb.1:
; RV64IB-NEXT: mv a3, a0
; RV64IB-NEXT: .LBB6_2:
; RV64IB-NEXT: mv a0, a3 ; RV64IB-NEXT: mv a0, a3
; RV64IB-NEXT: .LBB6_2:
; RV64IB-NEXT: ret ; RV64IB-NEXT: ret
; ;
; RV64IBT-LABEL: cmov_uge_i32: ; RV64IBT-LABEL: cmov_uge_i32:
; RV64IBT: # %bb.0: ; RV64IBT: # %bb.0:
; RV64IBT-NEXT: bgeu a1, a2, .LBB6_2 ; RV64IBT-NEXT: bgeu a1, a2, .LBB6_2
; RV64IBT-NEXT: # %bb.1: ; RV64IBT-NEXT: # %bb.1:
; RV64IBT-NEXT: mv a3, a0
; RV64IBT-NEXT: .LBB6_2:
; RV64IBT-NEXT: mv a0, a3 ; RV64IBT-NEXT: mv a0, a3
; RV64IBT-NEXT: .LBB6_2:
; RV64IBT-NEXT: ret ; RV64IBT-NEXT: ret
%tobool = icmp uge i32 %b, %c %tobool = icmp uge i32 %b, %c
%cond = select i1 %tobool, i32 %d, i32 %a %cond = select i1 %tobool, i32 %a, i32 %d
ret i32 %cond ret i32 %cond
} }
define i64 @cmov_i64(i64 %a, i64 %b, i64 %c) nounwind { define i64 @cmov_i64(i64 %a, i64 %b, i64 %c) nounwind {
; RV64I-LABEL: cmov_i64: ; RV64I-LABEL: cmov_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: beqz a1, .LBB7_2 ; RV64I-NEXT: beqz a1, .LBB7_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
Show All 16 Lines; RV64IBT-NEXT: ret
ret i64 %cond ret i64 %cond
} }
define i64 @cmov_sle_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind { define i64 @cmov_sle_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV64I-LABEL: cmov_sle_i64: ; RV64I-LABEL: cmov_sle_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bge a2, a1, .LBB8_2 ; RV64I-NEXT: bge a2, a1, .LBB8_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a3, a0
; RV64I-NEXT: .LBB8_2:
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB8_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IB-LABEL: cmov_sle_i64: ; RV64IB-LABEL: cmov_sle_i64:
; RV64IB: # %bb.0: ; RV64IB: # %bb.0:
; RV64IB-NEXT: bge a2, a1, .LBB8_2 ; RV64IB-NEXT: bge a2, a1, .LBB8_2
; RV64IB-NEXT: # %bb.1: ; RV64IB-NEXT: # %bb.1:
; RV64IB-NEXT: mv a3, a0
; RV64IB-NEXT: .LBB8_2:
; RV64IB-NEXT: mv a0, a3 ; RV64IB-NEXT: mv a0, a3
; RV64IB-NEXT: .LBB8_2:
; RV64IB-NEXT: ret ; RV64IB-NEXT: ret
; ;
; RV64IBT-LABEL: cmov_sle_i64: ; RV64IBT-LABEL: cmov_sle_i64:
; RV64IBT: # %bb.0: ; RV64IBT: # %bb.0:
; RV64IBT-NEXT: bge a2, a1, .LBB8_2 ; RV64IBT-NEXT: bge a2, a1, .LBB8_2
; RV64IBT-NEXT: # %bb.1: ; RV64IBT-NEXT: # %bb.1:
; RV64IBT-NEXT: mv a3, a0
; RV64IBT-NEXT: .LBB8_2:
; RV64IBT-NEXT: mv a0, a3 ; RV64IBT-NEXT: mv a0, a3
; RV64IBT-NEXT: .LBB8_2:
; RV64IBT-NEXT: ret ; RV64IBT-NEXT: ret
%tobool = icmp sle i64 %b, %c %tobool = icmp sle i64 %b, %c
%cond = select i1 %tobool, i64 %d, i64 %a %cond = select i1 %tobool, i64 %a, i64 %d
ret i64 %cond ret i64 %cond
} }
define i64 @cmov_sge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind { define i64 @cmov_sge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV64I-LABEL: cmov_sge_i64: ; RV64I-LABEL: cmov_sge_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bge a1, a2, .LBB9_2 ; RV64I-NEXT: bge a1, a2, .LBB9_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a3, a0
; RV64I-NEXT: .LBB9_2:
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB9_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IB-LABEL: cmov_sge_i64: ; RV64IB-LABEL: cmov_sge_i64:
; RV64IB: # %bb.0: ; RV64IB: # %bb.0:
; RV64IB-NEXT: bge a1, a2, .LBB9_2 ; RV64IB-NEXT: bge a1, a2, .LBB9_2
; RV64IB-NEXT: # %bb.1: ; RV64IB-NEXT: # %bb.1:
; RV64IB-NEXT: mv a3, a0
; RV64IB-NEXT: .LBB9_2:
; RV64IB-NEXT: mv a0, a3 ; RV64IB-NEXT: mv a0, a3
; RV64IB-NEXT: .LBB9_2:
; RV64IB-NEXT: ret ; RV64IB-NEXT: ret
; ;
; RV64IBT-LABEL: cmov_sge_i64: ; RV64IBT-LABEL: cmov_sge_i64:
; RV64IBT: # %bb.0: ; RV64IBT: # %bb.0:
; RV64IBT-NEXT: bge a1, a2, .LBB9_2 ; RV64IBT-NEXT: bge a1, a2, .LBB9_2
; RV64IBT-NEXT: # %bb.1: ; RV64IBT-NEXT: # %bb.1:
; RV64IBT-NEXT: mv a3, a0
; RV64IBT-NEXT: .LBB9_2:
; RV64IBT-NEXT: mv a0, a3 ; RV64IBT-NEXT: mv a0, a3
; RV64IBT-NEXT: .LBB9_2:
; RV64IBT-NEXT: ret ; RV64IBT-NEXT: ret
%tobool = icmp sge i64 %b, %c %tobool = icmp sge i64 %b, %c
%cond = select i1 %tobool, i64 %d, i64 %a %cond = select i1 %tobool, i64 %a, i64 %d
ret i64 %cond ret i64 %cond
} }
define i64 @cmov_ule_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind { define i64 @cmov_ule_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV64I-LABEL: cmov_ule_i64: ; RV64I-LABEL: cmov_ule_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bgeu a2, a1, .LBB10_2 ; RV64I-NEXT: bgeu a2, a1, .LBB10_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a3, a0
; RV64I-NEXT: .LBB10_2:
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB10_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IB-LABEL: cmov_ule_i64: ; RV64IB-LABEL: cmov_ule_i64:
; RV64IB: # %bb.0: ; RV64IB: # %bb.0:
; RV64IB-NEXT: bgeu a2, a1, .LBB10_2 ; RV64IB-NEXT: bgeu a2, a1, .LBB10_2
; RV64IB-NEXT: # %bb.1: ; RV64IB-NEXT: # %bb.1:
; RV64IB-NEXT: mv a3, a0
; RV64IB-NEXT: .LBB10_2:
; RV64IB-NEXT: mv a0, a3 ; RV64IB-NEXT: mv a0, a3
; RV64IB-NEXT: .LBB10_2:
; RV64IB-NEXT: ret ; RV64IB-NEXT: ret
; ;
; RV64IBT-LABEL: cmov_ule_i64: ; RV64IBT-LABEL: cmov_ule_i64:
; RV64IBT: # %bb.0: ; RV64IBT: # %bb.0:
; RV64IBT-NEXT: bgeu a2, a1, .LBB10_2 ; RV64IBT-NEXT: bgeu a2, a1, .LBB10_2
; RV64IBT-NEXT: # %bb.1: ; RV64IBT-NEXT: # %bb.1:
; RV64IBT-NEXT: mv a3, a0
; RV64IBT-NEXT: .LBB10_2:
; RV64IBT-NEXT: mv a0, a3 ; RV64IBT-NEXT: mv a0, a3
; RV64IBT-NEXT: .LBB10_2:
; RV64IBT-NEXT: ret ; RV64IBT-NEXT: ret
%tobool = icmp ule i64 %b, %c %tobool = icmp ule i64 %b, %c
%cond = select i1 %tobool, i64 %d, i64 %a %cond = select i1 %tobool, i64 %a, i64 %d
ret i64 %cond ret i64 %cond
} }
define i64 @cmov_uge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind { define i64 @cmov_uge_i64(i64 %a, i64 %b, i64 %c, i64 %d) nounwind {
; RV64I-LABEL: cmov_uge_i64: ; RV64I-LABEL: cmov_uge_i64:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: bgeu a1, a2, .LBB11_2 ; RV64I-NEXT: bgeu a1, a2, .LBB11_2
; RV64I-NEXT: # %bb.1: ; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a3, a0
; RV64I-NEXT: .LBB11_2:
; RV64I-NEXT: mv a0, a3 ; RV64I-NEXT: mv a0, a3
; RV64I-NEXT: .LBB11_2:
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV64IB-LABEL: cmov_uge_i64: ; RV64IB-LABEL: cmov_uge_i64:
; RV64IB: # %bb.0: ; RV64IB: # %bb.0:
; RV64IB-NEXT: bgeu a1, a2, .LBB11_2 ; RV64IB-NEXT: bgeu a1, a2, .LBB11_2
; RV64IB-NEXT: # %bb.1: ; RV64IB-NEXT: # %bb.1:
; RV64IB-NEXT: mv a3, a0
; RV64IB-NEXT: .LBB11_2:
; RV64IB-NEXT: mv a0, a3 ; RV64IB-NEXT: mv a0, a3
; RV64IB-NEXT: .LBB11_2:
; RV64IB-NEXT: ret ; RV64IB-NEXT: ret
; ;
; RV64IBT-LABEL: cmov_uge_i64: ; RV64IBT-LABEL: cmov_uge_i64:
; RV64IBT: # %bb.0: ; RV64IBT: # %bb.0:
; RV64IBT-NEXT: bgeu a1, a2, .LBB11_2 ; RV64IBT-NEXT: bgeu a1, a2, .LBB11_2
; RV64IBT-NEXT: # %bb.1: ; RV64IBT-NEXT: # %bb.1:
; RV64IBT-NEXT: mv a3, a0
; RV64IBT-NEXT: .LBB11_2:
; RV64IBT-NEXT: mv a0, a3 ; RV64IBT-NEXT: mv a0, a3
; RV64IBT-NEXT: .LBB11_2:
; RV64IBT-NEXT: ret ; RV64IBT-NEXT: ret
%tobool = icmp uge i64 %b, %c %tobool = icmp uge i64 %b, %c
%cond = select i1 %tobool, i64 %d, i64 %a %cond = select i1 %tobool, i64 %a, i64 %d
ret i64 %cond ret i64 %cond
} }
declare i32 @llvm.fshl.i32(i32, i32, i32) declare i32 @llvm.fshl.i32(i32, i32, i32)
define signext i32 @fshl_i32(i32 signext %a, i32 signext %b, i32 signext %c) nounwind { define signext i32 @fshl_i32(i32 signext %a, i32 signext %b, i32 signext %c) nounwind {
; RV64I-LABEL: fshl_i32: ; RV64I-LABEL: fshl_i32:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
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