[X86] Add segment and address-size override prefixes

[void]

Summary

X86 allows for the "addr32" and "addr16" address size override prefixes.
Also, these and the segment override prefixes should be recognized as
valid prefixes.

[skan]

llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp

3263–3269

Hmm, could you capitalize the first char of "isPrefix" by the way?

llvm/lib/Target/X86/X86InstrSystem.td

180–182

A minor suggestion: Add tests to check the predicates "In32BitMode", "In64BitMode" for addr16/32.

llvm/test/MC/X86/addr16-32.s

25

Remove this line.

llvm/test/MC/X86/segment-prefix.s

22

Remove this line.

[void]

Fixed variable name and removed excess test lines.

llvm/lib/Target/X86/X86InstrSystem.td

180–182

The tests which include ".code16"/".code32", etc., should be doing this already.

[skan]

LGTM. Before this patch, we could only write code like

CS
insl

addr32/addr16 and CS/DS/ES/FS/GS/SS are prefixes, so they should be allowed to be written before the instruction in the same line, and GNU-AS does support this syntax.
One behavior different from GNU-AS is that as rejects es and ss in 64-bit mode, but this has beyond the purpose of this patch.

llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp

bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
 
   // Determine whether this is an instruction prefix.
   // FIXME:
   // Enhance prefixes integrity robustness. for example, following forms
   // are currently tolerated:
   // repz repnz <insn>    ; GAS errors for the use of two similar prefixes
   // lock addq %rax, %rbx ; Destination operand must be of memory type
   // xacquire <insn>      ; xacquire must be accompanied by 'lock'
-  bool isPrefix = StringSwitch<bool>(Name)
-                      .Cases("rex64", "data32", "data16", true)
-                      .Cases("xacquire", "xrelease", true)
-                      .Cases("acquire", "release", isParsingIntelSyntax())
-                      .Default(false);
+  bool IsPrefix =
+      StringSwitch<bool>(Name)
+          .Cases("cs", "ds", "es", "fs", "gs", "ss", true)
+          .Cases("rex64", "data32", "data16", "addr32", "addr16", true)
 
   auto isLockRepeatNtPrefix = [](StringRef N) {
     return StringSwitch<bool>(N)
         .Cases("lock", "rep", "repe", "repz", "repne", "repnz", "notrack", true)
         .Default(false);
   };
 
   bool CurlyAsEndOfStatement = false;
if (getLexer().isNot(AsmToken::EndOfStatement)) {
       if (Next == "callw")
         Next = "calll";
       if (Next == "ljmpw")
         Next = "ljmpl";
 
       Name = Next;
       PatchedName = Name;
       ForcedDataPrefix = X86::Mode32Bit;
-      isPrefix = false;
+      IsPrefix = false;
     }
   }
 
   Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
 
   // Push the immediate if we extracted one from the mnemonic.
   if (ComparisonPredicate != ~0U && !isParsingIntelSyntax()) {
     const MCExpr *ImmOp = MCConstantExpr::create(ComparisonPredicate,
                                                  getParser().getContext());
     Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc));
   }
 
   // This does the actual operand parsing.  Don't parse any more if we have a
   // prefix juxtaposed with an operation like "lock incl 4(%rax)", because we
   // just want to parse the "lock" as the first instruction and the "incl" as
   // the next one.
-  if (getLexer().isNot(AsmToken::EndOfStatement) && !isPrefix) {
+  if (getLexer().isNot(AsmToken::EndOfStatement) && !IsPrefix) {
     // Parse '*' modifier.
     if (getLexer().is(AsmToken::Star))
       Operands.push_back(X86Operand::CreateToken("*", consumeToken()));
 
     // Read the operands.
     while(1) {
       if (ParseOperand(Operands))
         return true;
bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
   if (ComparisonPredicate != ~0U && isParsingIntelSyntax()) {
     const MCExpr *ImmOp = MCConstantExpr::create(ComparisonPredicate,
                                                  getParser().getContext());
     Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc));
   }
 
   // Consume the EndOfStatement or the prefix separator Slash
   if (getLexer().is(AsmToken::EndOfStatement) ||
-      (isPrefix && getLexer().is(AsmToken::Slash)))
+      (IsPrefix && getLexer().is(AsmToken::Slash)))
     Parser.Lex();
   else if (CurlyAsEndOfStatement)
     // Add an actual EndOfStatement before the curly brace
     Info.AsmRewrites->emplace_back(AOK_EndOfStatement,
                                    getLexer().getTok().getLoc(), 0);
 
   // This is for gas compatibility and cannot be done in td.
   // Adding "p" for some floating point with no argument.

llvm/lib/Target/X86/X86InstrSystem.td

 def SS_PREFIX : I<0x36, PrefixByte, (outs), (ins), "ss", []>;
 def DS_PREFIX : I<0x3E, PrefixByte, (outs), (ins), "ds", []>;
 def ES_PREFIX : I<0x26, PrefixByte, (outs), (ins), "es", []>;
 def FS_PREFIX : I<0x64, PrefixByte, (outs), (ins), "fs", []>;
 def GS_PREFIX : I<0x65, PrefixByte, (outs), (ins), "gs", []>;
 } // SchedRW
 
 //===----------------------------------------------------------------------===//
+// Address-size override prefixes.
+//
+
+let SchedRW = [WriteNop] in {
+def ADDR16_PREFIX : I<0x67, PrefixByte, (outs), (ins), "addr16", []>,
+                      Requires<[In32BitMode]>;
+def ADDR32_PREFIX : I<0x67, PrefixByte, (outs), (ins), "addr32", []>,
+                      Requires<[In64BitMode]>;
+} // SchedRW
+
+//===----------------------------------------------------------------------===//
 // Moves to and from segment registers.
 //
 
 let SchedRW = [WriteMove] in {
 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
                 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16;
 def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
                 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32;

llvm/test/MC/X86/addr16-32.s

+# RUN: llvm-mc %s -triple x86_64-linux-gnu -filetype=obj -o - | llvm-objdump -d - | FileCheck %s
+
+.text
+.global foo
+foo:
+  insl
+  gs outsl
+  .code64
+  addr32 insl
+  addr32 gs outsl
+  .code32
+  addr16 insl
+  addr16 gs outsl
+  .code64
+  retq
+
+# CHECK: <foo>:
+# CHECK-NEXT: 6d                            insl   %dx, %es:(%rdi)
+# CHECK-NEXT: 65 6f                         outsl  %gs:(%rsi), %dx
+# CHECK-NEXT: 67 6d                         insl   %dx, %es:(%edi)
+# CHECK-NEXT: 67 65 6f                      outsl  %gs:(%esi), %dx
+# CHECK-NEXT: 67 6d                         insl   %dx, %es:(%edi)
+# CHECK-NEXT: 67 65 6f                      outsl  %gs:(%esi), %dx

llvm/test/MC/X86/segment-prefix.s

+# RUN: llvm-mc %s -triple x86_64-linux-gnu -filetype=obj -o - | llvm-objdump -d - | FileCheck %s
+
+.text
+.global foo
+foo:
+  cs outsl
+  ds outsl
+  es outsw
+  fs outsw
+  gs outsl
+  ss outsl
+  retq
+
+# CHECK: <foo>:
+# CHECK-NEXT: 2e 6f                         outsl  %cs:(%rsi), %dx
+# CHECK-NEXT: 3e 6f                         outsl  %ds:(%rsi), %dx
+# CHECK-NEXT: 26 66 6f                      outsw  %es:(%rsi), %dx
+# CHECK-NEXT: 64 66 6f                      outsw  %fs:(%rsi), %dx
+# CHECK-NEXT: 65 6f                         outsl  %gs:(%rsi), %dx
+# CHECK-NEXT: 36 6f                         outsl  %ss:(%rsi), %dx