diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td --- a/llvm/include/llvm/IR/IntrinsicsAArch64.td +++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td @@ -12,47 +12,58 @@ let TargetPrefix = "aarch64" in { -def int_aarch64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>; -def int_aarch64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty]>; -def int_aarch64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>; -def int_aarch64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty]>; - -def int_aarch64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>; -def int_aarch64_ldaxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty]>; +def int_aarch64_ldxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty], + [IntrNoFree, IntrWillReturn]>; +def int_aarch64_ldaxr : Intrinsic<[llvm_i64_ty], [llvm_anyptr_ty], + [IntrNoFree, IntrWillReturn]>; +def int_aarch64_stxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty], + [IntrNoFree, IntrWillReturn]>; +def int_aarch64_stlxr : Intrinsic<[llvm_i32_ty], [llvm_i64_ty, llvm_anyptr_ty], + [IntrNoFree, IntrWillReturn]>; + +def int_aarch64_ldxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty], + [IntrNoFree, IntrWillReturn]>; +def int_aarch64_ldaxp : Intrinsic<[llvm_i64_ty, llvm_i64_ty], [llvm_ptr_ty], + [IntrNoFree, IntrWillReturn]>; def int_aarch64_stxp : Intrinsic<[llvm_i32_ty], - [llvm_i64_ty, llvm_i64_ty, llvm_ptr_ty]>; + [llvm_i64_ty, llvm_i64_ty, llvm_ptr_ty], + [IntrNoFree, IntrWillReturn]>; def int_aarch64_stlxp : Intrinsic<[llvm_i32_ty], - [llvm_i64_ty, llvm_i64_ty, llvm_ptr_ty]>; + [llvm_i64_ty, llvm_i64_ty, llvm_ptr_ty], + [IntrNoFree, IntrWillReturn]>; def int_aarch64_clrex : Intrinsic<[]>; -def int_aarch64_sdiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, +def int_aarch64_sdiv : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; -def int_aarch64_udiv : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, +def int_aarch64_udiv : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; -def int_aarch64_fjcvtzs : Intrinsic<[llvm_i32_ty], [llvm_double_ty], [IntrNoMem]>; +def int_aarch64_fjcvtzs : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_double_ty], [IntrNoMem]>; -def int_aarch64_cls: Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>; -def int_aarch64_cls64: Intrinsic<[llvm_i32_ty], [llvm_i64_ty], [IntrNoMem]>; +def int_aarch64_cls: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>; +def int_aarch64_cls64: DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i64_ty], [IntrNoMem]>; //===----------------------------------------------------------------------===// // HINT -def int_aarch64_hint : Intrinsic<[], [llvm_i32_ty]>; +def int_aarch64_hint : DefaultAttrsIntrinsic<[], [llvm_i32_ty]>; //===----------------------------------------------------------------------===// // Data Barrier Instructions -def int_aarch64_dmb : GCCBuiltin<"__builtin_arm_dmb">, MSBuiltin<"__dmb">, Intrinsic<[], [llvm_i32_ty]>; -def int_aarch64_dsb : GCCBuiltin<"__builtin_arm_dsb">, MSBuiltin<"__dsb">, Intrinsic<[], [llvm_i32_ty]>; -def int_aarch64_isb : GCCBuiltin<"__builtin_arm_isb">, MSBuiltin<"__isb">, Intrinsic<[], [llvm_i32_ty]>; +def int_aarch64_dmb : GCCBuiltin<"__builtin_arm_dmb">, MSBuiltin<"__dmb">, + Intrinsic<[], [llvm_i32_ty], [IntrNoFree, IntrWillReturn]>; +def int_aarch64_dsb : GCCBuiltin<"__builtin_arm_dsb">, MSBuiltin<"__dsb">, + Intrinsic<[], [llvm_i32_ty], [IntrNoFree, IntrWillReturn]>; +def int_aarch64_isb : GCCBuiltin<"__builtin_arm_isb">, MSBuiltin<"__isb">, + Intrinsic<[], [llvm_i32_ty], [IntrNoFree, IntrWillReturn]>; // A space-consuming intrinsic primarily for testing block and jump table // placements. The first argument is the number of bytes this "instruction" // takes up, the second and return value are essentially chains, used to force // ordering during ISel. -def int_aarch64_space : Intrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i64_ty], []>; +def int_aarch64_space : DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i64_ty], []>; } @@ -61,131 +72,131 @@ let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.". class AdvSIMD_2Scalar_Float_Intrinsic - : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>], + : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; class AdvSIMD_FPToIntRounding_Intrinsic - : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty], [IntrNoMem]>; + : DefaultAttrsIntrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty], [IntrNoMem]>; class AdvSIMD_1IntArg_Intrinsic - : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrNoMem]>; + : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrNoMem]>; class AdvSIMD_1FloatArg_Intrinsic - : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>; + : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>; class AdvSIMD_1VectorArg_Intrinsic - : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>; + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>; class AdvSIMD_1VectorArg_Expand_Intrinsic - : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>; + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>; class AdvSIMD_1VectorArg_Long_Intrinsic - : Intrinsic<[llvm_anyvector_ty], [LLVMTruncatedType<0>], [IntrNoMem]>; + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMTruncatedType<0>], [IntrNoMem]>; class AdvSIMD_1IntArg_Narrow_Intrinsic - : Intrinsic<[llvm_anyint_ty], [llvm_anyint_ty], [IntrNoMem]>; + : DefaultAttrsIntrinsic<[llvm_anyint_ty], [llvm_anyint_ty], [IntrNoMem]>; class AdvSIMD_1VectorArg_Narrow_Intrinsic - : Intrinsic<[llvm_anyint_ty], [LLVMExtendedType<0>], [IntrNoMem]>; + : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMExtendedType<0>], [IntrNoMem]>; class AdvSIMD_1VectorArg_Int_Across_Intrinsic - : Intrinsic<[llvm_anyint_ty], [llvm_anyvector_ty], [IntrNoMem]>; + : DefaultAttrsIntrinsic<[llvm_anyint_ty], [llvm_anyvector_ty], [IntrNoMem]>; class AdvSIMD_1VectorArg_Float_Across_Intrinsic - : Intrinsic<[llvm_anyfloat_ty], [llvm_anyvector_ty], [IntrNoMem]>; + : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [llvm_anyvector_ty], [IntrNoMem]>; class AdvSIMD_2IntArg_Intrinsic - : Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>], + : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; class AdvSIMD_2FloatArg_Intrinsic - : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>], + : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; class AdvSIMD_2VectorArg_Intrinsic - : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; class AdvSIMD_2VectorArg_Compare_Intrinsic - : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>], [IntrNoMem]>; class AdvSIMD_2Arg_FloatCompare_Intrinsic - : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, LLVMMatchType<1>], + : DefaultAttrsIntrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, LLVMMatchType<1>], [IntrNoMem]>; class AdvSIMD_2VectorArg_Long_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMTruncatedType<0>, LLVMTruncatedType<0>], [IntrNoMem]>; class AdvSIMD_2VectorArg_Wide_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMTruncatedType<0>], [IntrNoMem]>; class AdvSIMD_2VectorArg_Narrow_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>, LLVMExtendedType<0>], [IntrNoMem]>; class AdvSIMD_2Arg_Scalar_Narrow_Intrinsic - : Intrinsic<[llvm_anyint_ty], + : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMExtendedType<0>, llvm_i32_ty], [IntrNoMem]>; class AdvSIMD_2VectorArg_Scalar_Expand_BySize_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>; class AdvSIMD_2VectorArg_Scalar_Wide_BySize_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMTruncatedType<0>], [IntrNoMem]>; class AdvSIMD_2VectorArg_Scalar_Wide_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMTruncatedType<0>, llvm_i32_ty], [IntrNoMem]>; class AdvSIMD_2VectorArg_Tied_Narrow_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty], [IntrNoMem]>; class AdvSIMD_2VectorArg_Lane_Intrinsic - : Intrinsic<[llvm_anyint_ty], + : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>; class AdvSIMD_3VectorArg_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; class AdvSIMD_3VectorArg_Scalar_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty], [IntrNoMem]>; class AdvSIMD_3VectorArg_Tied_Narrow_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty, LLVMMatchType<1>], [IntrNoMem]>; class AdvSIMD_3VectorArg_Scalar_Tied_Narrow_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMHalfElementsVectorType<0>, llvm_anyvector_ty, llvm_i32_ty], [IntrNoMem]>; class AdvSIMD_CvtFxToFP_Intrinsic - : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], + : DefaultAttrsIntrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>; class AdvSIMD_CvtFPToFx_Intrinsic - : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], + : DefaultAttrsIntrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>; class AdvSIMD_1Arg_Intrinsic - : Intrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrNoMem]>; + : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrNoMem]>; class AdvSIMD_Dot_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<1>], [IntrNoMem]>; class AdvSIMD_FP16FML_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<1>], [IntrNoMem]>; class AdvSIMD_MatMul_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<1>], [IntrNoMem]>; class AdvSIMD_FML_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<1>], [IntrNoMem]>; class AdvSIMD_BF16FML_Intrinsic - : Intrinsic<[llvm_v4f32_ty], + : DefaultAttrsIntrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v8bf16_ty, llvm_v8bf16_ty], [IntrNoMem]>; } @@ -245,7 +256,7 @@ // 64-bit polynomial multiply really returns an i128, which is not legal. Fake // it with a v16i8. def int_aarch64_neon_pmull64 : - Intrinsic<[llvm_v16i8_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>; + DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>; // Vector Extending Multiply def int_aarch64_neon_fmulx : AdvSIMD_2FloatArg_Intrinsic { @@ -255,7 +266,7 @@ // Vector Saturating Doubling Long Multiply def int_aarch64_neon_sqdmull : AdvSIMD_2VectorArg_Long_Intrinsic; def int_aarch64_neon_sqdmulls_scalar - : Intrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; + : DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; // Vector Halving Subtract def int_aarch64_neon_shsub : AdvSIMD_2VectorArg_Intrinsic; @@ -425,9 +436,9 @@ // Vector Conversions Between Half-Precision and Single-Precision. def int_aarch64_neon_vcvtfp2hf - : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>; + : DefaultAttrsIntrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>; def int_aarch64_neon_vcvthf2fp - : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>; + : DefaultAttrsIntrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>; // Vector Conversions Between Floating-point and Fixed-point. def int_aarch64_neon_vcvtfp2fxs : AdvSIMD_CvtFPToFx_Intrinsic; @@ -457,7 +468,7 @@ def int_aarch64_neon_fcvtxn : AdvSIMD_1VectorArg_Expand_Intrinsic; // Scalar FP Inexact Narrowing - def int_aarch64_sisd_fcvtxn : Intrinsic<[llvm_float_ty], [llvm_double_ty], + def int_aarch64_sisd_fcvtxn : DefaultAttrsIntrinsic<[llvm_float_ty], [llvm_double_ty], [IntrNoMem]>; // v8.2-A Dot Product @@ -471,7 +482,7 @@ def int_aarch64_neon_usdot : AdvSIMD_Dot_Intrinsic; def int_aarch64_neon_bfdot : AdvSIMD_Dot_Intrinsic; def int_aarch64_neon_bfmmla - : Intrinsic<[llvm_v4f32_ty], + : DefaultAttrsIntrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v8bf16_ty, llvm_v8bf16_ty], [IntrNoMem]>; def int_aarch64_neon_bfmlalb : AdvSIMD_BF16FML_Intrinsic; @@ -480,11 +491,11 @@ // v8.6-A Bfloat Intrinsics def int_aarch64_neon_bfcvt - : Intrinsic<[llvm_bfloat_ty], [llvm_float_ty], [IntrNoMem]>; + : DefaultAttrsIntrinsic<[llvm_bfloat_ty], [llvm_float_ty], [IntrNoMem]>; def int_aarch64_neon_bfcvtn - : Intrinsic<[llvm_v8bf16_ty], [llvm_v4f32_ty], [IntrNoMem]>; + : DefaultAttrsIntrinsic<[llvm_v8bf16_ty], [llvm_v4f32_ty], [IntrNoMem]>; def int_aarch64_neon_bfcvtn2 - : Intrinsic<[llvm_v8bf16_ty], + : DefaultAttrsIntrinsic<[llvm_v8bf16_ty], [llvm_v8bf16_ty, llvm_v4f32_ty], [IntrNoMem]>; @@ -506,7 +517,7 @@ let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.". class AdvSIMD_2Vector2Index_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, llvm_i64_ty, LLVMMatchType<0>, llvm_i64_ty], [IntrNoMem]>; } @@ -516,68 +527,68 @@ let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.". class AdvSIMD_1Vec_Load_Intrinsic - : Intrinsic<[llvm_anyvector_ty], [LLVMAnyPointerType>], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMAnyPointerType>], [IntrReadMem, IntrArgMemOnly]>; class AdvSIMD_1Vec_Store_Lane_Intrinsic - : Intrinsic<[], [llvm_anyvector_ty, llvm_i64_ty, llvm_anyptr_ty], + : DefaultAttrsIntrinsic<[], [llvm_anyvector_ty, llvm_i64_ty, llvm_anyptr_ty], [IntrArgMemOnly, NoCapture>]>; class AdvSIMD_2Vec_Load_Intrinsic - : Intrinsic<[LLVMMatchType<0>, llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[LLVMMatchType<0>, llvm_anyvector_ty], [LLVMAnyPointerType>], [IntrReadMem, IntrArgMemOnly]>; class AdvSIMD_2Vec_Load_Lane_Intrinsic - : Intrinsic<[LLVMMatchType<0>, LLVMMatchType<0>], + : DefaultAttrsIntrinsic<[LLVMMatchType<0>, LLVMMatchType<0>], [LLVMMatchType<0>, llvm_anyvector_ty, llvm_i64_ty, llvm_anyptr_ty], [IntrReadMem, IntrArgMemOnly]>; class AdvSIMD_2Vec_Store_Intrinsic - : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>, + : DefaultAttrsIntrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>, LLVMAnyPointerType>], [IntrArgMemOnly, NoCapture>]>; class AdvSIMD_2Vec_Store_Lane_Intrinsic - : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>, + : DefaultAttrsIntrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>, llvm_i64_ty, llvm_anyptr_ty], [IntrArgMemOnly, NoCapture>]>; class AdvSIMD_3Vec_Load_Intrinsic - : Intrinsic<[LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty], [LLVMAnyPointerType>], [IntrReadMem, IntrArgMemOnly]>; class AdvSIMD_3Vec_Load_Lane_Intrinsic - : Intrinsic<[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], + : DefaultAttrsIntrinsic<[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, llvm_i64_ty, llvm_anyptr_ty], [IntrReadMem, IntrArgMemOnly]>; class AdvSIMD_3Vec_Store_Intrinsic - : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>, + : DefaultAttrsIntrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMAnyPointerType>], [IntrArgMemOnly, NoCapture>]>; class AdvSIMD_3Vec_Store_Lane_Intrinsic - : Intrinsic<[], [llvm_anyvector_ty, + : DefaultAttrsIntrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, llvm_i64_ty, llvm_anyptr_ty], [IntrArgMemOnly, NoCapture>]>; class AdvSIMD_4Vec_Load_Intrinsic - : Intrinsic<[LLVMMatchType<0>, LLVMMatchType<0>, + : DefaultAttrsIntrinsic<[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty], [LLVMAnyPointerType>], [IntrReadMem, IntrArgMemOnly]>; class AdvSIMD_4Vec_Load_Lane_Intrinsic - : Intrinsic<[LLVMMatchType<0>, LLVMMatchType<0>, + : DefaultAttrsIntrinsic<[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, llvm_i64_ty, llvm_anyptr_ty], [IntrReadMem, IntrArgMemOnly]>; class AdvSIMD_4Vec_Store_Intrinsic - : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>, + : DefaultAttrsIntrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>, LLVMAnyPointerType>], [IntrArgMemOnly, NoCapture>]>; class AdvSIMD_4Vec_Store_Lane_Intrinsic - : Intrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>, + : DefaultAttrsIntrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>, llvm_i64_ty, llvm_anyptr_ty], [IntrArgMemOnly, NoCapture>]>; @@ -615,38 +626,38 @@ let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.". class AdvSIMD_Tbl1_Intrinsic - : Intrinsic<[llvm_anyvector_ty], [llvm_v16i8_ty, LLVMMatchType<0>], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_v16i8_ty, LLVMMatchType<0>], [IntrNoMem]>; class AdvSIMD_Tbl2_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>], [IntrNoMem]>; class AdvSIMD_Tbl3_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>], [IntrNoMem]>; class AdvSIMD_Tbl4_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>], [IntrNoMem]>; class AdvSIMD_Tbx1_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, llvm_v16i8_ty, LLVMMatchType<0>], [IntrNoMem]>; class AdvSIMD_Tbx2_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>], [IntrNoMem]>; class AdvSIMD_Tbx3_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>], [IntrNoMem]>; class AdvSIMD_Tbx4_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty, LLVMMatchType<0>], [IntrNoMem]>; @@ -663,7 +674,7 @@ let TargetPrefix = "aarch64" in { class FPCR_Get_Intrinsic - : Intrinsic<[llvm_i64_ty], [], [IntrNoMem, IntrHasSideEffects]>; + : DefaultAttrsIntrinsic<[llvm_i64_ty], [], [IntrNoMem, IntrHasSideEffects]>; } // FPCR @@ -671,34 +682,34 @@ let TargetPrefix = "aarch64" in { class Crypto_AES_DataKey_Intrinsic - : Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>; + : DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>; class Crypto_AES_Data_Intrinsic - : Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>; + : DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>; // SHA intrinsic taking 5 words of the hash (v4i32, i32) and 4 of the schedule // (v4i32). class Crypto_SHA_5Hash4Schedule_Intrinsic - : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty], + : DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty], [IntrNoMem]>; // SHA intrinsic taking 5 words of the hash (v4i32, i32) and 4 of the schedule // (v4i32). class Crypto_SHA_1Hash_Intrinsic - : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>; + : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>; // SHA intrinsic taking 8 words of the schedule class Crypto_SHA_8Schedule_Intrinsic - : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; + : DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; // SHA intrinsic taking 12 words of the schedule class Crypto_SHA_12Schedule_Intrinsic - : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], + : DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; // SHA intrinsic taking 8 words of the hash and 4 of the schedule. class Crypto_SHA_8Hash4Schedule_Intrinsic - : Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], + : DefaultAttrsIntrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>; } @@ -728,44 +739,44 @@ let TargetPrefix = "aarch64" in { -def int_aarch64_crc32b : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], +def int_aarch64_crc32b : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; -def int_aarch64_crc32cb : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], +def int_aarch64_crc32cb : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; -def int_aarch64_crc32h : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], +def int_aarch64_crc32h : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; -def int_aarch64_crc32ch : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], +def int_aarch64_crc32ch : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; -def int_aarch64_crc32w : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], +def int_aarch64_crc32w : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; -def int_aarch64_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], +def int_aarch64_crc32cw : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; -def int_aarch64_crc32x : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty], +def int_aarch64_crc32x : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty], [IntrNoMem]>; -def int_aarch64_crc32cx : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty], +def int_aarch64_crc32cx : DefaultAttrsIntrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty], [IntrNoMem]>; } //===----------------------------------------------------------------------===// // Memory Tagging Extensions (MTE) Intrinsics let TargetPrefix = "aarch64" in { -def int_aarch64_irg : Intrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_i64_ty], +def int_aarch64_irg : DefaultAttrsIntrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_i64_ty], [IntrNoMem, IntrHasSideEffects]>; -def int_aarch64_addg : Intrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_i64_ty], +def int_aarch64_addg : DefaultAttrsIntrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_i64_ty], [IntrNoMem]>; -def int_aarch64_gmi : Intrinsic<[llvm_i64_ty], [llvm_ptr_ty, llvm_i64_ty], +def int_aarch64_gmi : DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_ptr_ty, llvm_i64_ty], [IntrNoMem]>; -def int_aarch64_ldg : Intrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_ptr_ty], +def int_aarch64_ldg : DefaultAttrsIntrinsic<[llvm_ptr_ty], [llvm_ptr_ty, llvm_ptr_ty], [IntrReadMem]>; -def int_aarch64_stg : Intrinsic<[], [llvm_ptr_ty, llvm_ptr_ty], +def int_aarch64_stg : DefaultAttrsIntrinsic<[], [llvm_ptr_ty, llvm_ptr_ty], [IntrWriteMem]>; -def int_aarch64_subp : Intrinsic<[llvm_i64_ty], [llvm_ptr_ty, llvm_ptr_ty], +def int_aarch64_subp : DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_ptr_ty, llvm_ptr_ty], [IntrNoMem]>; // The following are codegen-only intrinsics for stack instrumentation. // Generate a randomly tagged stack base pointer. -def int_aarch64_irg_sp : Intrinsic<[llvm_ptr_ty], [llvm_i64_ty], +def int_aarch64_irg_sp : DefaultAttrsIntrinsic<[llvm_ptr_ty], [llvm_i64_ty], [IntrNoMem, IntrHasSideEffects]>; // Transfer pointer tag with offset. @@ -780,35 +791,35 @@ // When offset between ptr0 and baseptr is a compile time constant, this can be emitted as // ADDG ptr1, baseptr, (ptr0 - baseptr), tag_offset // It is intended that ptr0 is an alloca address, and baseptr is the direct output of llvm.aarch64.irg.sp. -def int_aarch64_tagp : Intrinsic<[llvm_anyptr_ty], [LLVMMatchType<0>, llvm_ptr_ty, llvm_i64_ty], +def int_aarch64_tagp : DefaultAttrsIntrinsic<[llvm_anyptr_ty], [LLVMMatchType<0>, llvm_ptr_ty, llvm_i64_ty], [IntrNoMem, ImmArg>]>; // Update allocation tags for the memory range to match the tag in the pointer argument. -def int_aarch64_settag : Intrinsic<[], [llvm_ptr_ty, llvm_i64_ty], +def int_aarch64_settag : DefaultAttrsIntrinsic<[], [llvm_ptr_ty, llvm_i64_ty], [IntrWriteMem, IntrArgMemOnly, NoCapture>, WriteOnly>]>; // Update allocation tags for the memory range to match the tag in the pointer argument, // and set memory contents to zero. -def int_aarch64_settag_zero : Intrinsic<[], [llvm_ptr_ty, llvm_i64_ty], +def int_aarch64_settag_zero : DefaultAttrsIntrinsic<[], [llvm_ptr_ty, llvm_i64_ty], [IntrWriteMem, IntrArgMemOnly, NoCapture>, WriteOnly>]>; // Update allocation tags for 16-aligned, 16-sized memory region, and store a pair 8-byte values. -def int_aarch64_stgp : Intrinsic<[], [llvm_ptr_ty, llvm_i64_ty, llvm_i64_ty], +def int_aarch64_stgp : DefaultAttrsIntrinsic<[], [llvm_ptr_ty, llvm_i64_ty, llvm_i64_ty], [IntrWriteMem, IntrArgMemOnly, NoCapture>, WriteOnly>]>; } // Transactional Memory Extension (TME) Intrinsics let TargetPrefix = "aarch64" in { def int_aarch64_tstart : GCCBuiltin<"__builtin_arm_tstart">, - Intrinsic<[llvm_i64_ty]>; + DefaultAttrsIntrinsic<[llvm_i64_ty]>; -def int_aarch64_tcommit : GCCBuiltin<"__builtin_arm_tcommit">, Intrinsic<[]>; +def int_aarch64_tcommit : GCCBuiltin<"__builtin_arm_tcommit">, DefaultAttrsIntrinsic<[]>; def int_aarch64_tcancel : GCCBuiltin<"__builtin_arm_tcancel">, - Intrinsic<[], [llvm_i64_ty], [ImmArg>]>; + DefaultAttrsIntrinsic<[], [llvm_i64_ty], [ImmArg>]>; def int_aarch64_ttest : GCCBuiltin<"__builtin_arm_ttest">, - Intrinsic<[llvm_i64_ty], [], + DefaultAttrsIntrinsic<[llvm_i64_ty], [], [IntrNoMem, IntrHasSideEffects]>; // Armv8.7-A load/store 64-byte intrinsics @@ -835,88 +846,88 @@ let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.". class AdvSIMD_SVE_Create_2Vector_Tuple - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>], [IntrReadMem]>; class AdvSIMD_SVE_Create_3Vector_Tuple - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>, LLVMMatchType<1>], [IntrReadMem]>; class AdvSIMD_SVE_Create_4Vector_Tuple - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>, LLVMMatchType<1>, LLVMMatchType<1>], [IntrReadMem]>; class AdvSIMD_SVE_Set_Vector_Tuple - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, llvm_i32_ty, llvm_anyvector_ty], [IntrReadMem, ImmArg>]>; class AdvSIMD_SVE_Get_Vector_Tuple - : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, llvm_i32_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, llvm_i32_ty], [IntrReadMem, IntrArgMemOnly, ImmArg>]>; class AdvSIMD_ManyVec_PredLoad_Intrinsic - : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMPointerToElt<0>], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMPointerToElt<0>], [IntrReadMem, IntrArgMemOnly]>; class AdvSIMD_1Vec_PredLoad_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMPointerToElt<0>], [IntrReadMem, IntrArgMemOnly]>; class AdvSIMD_1Vec_PredStore_Intrinsic - : Intrinsic<[], + : DefaultAttrsIntrinsic<[], [llvm_anyvector_ty, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMPointerToElt<0>], [IntrArgMemOnly, NoCapture>]>; class AdvSIMD_2Vec_PredStore_Intrinsic - : Intrinsic<[], + : DefaultAttrsIntrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMPointerToElt<0>], [IntrArgMemOnly, NoCapture>]>; class AdvSIMD_3Vec_PredStore_Intrinsic - : Intrinsic<[], + : DefaultAttrsIntrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMPointerToElt<0>], [IntrArgMemOnly, NoCapture>]>; class AdvSIMD_4Vec_PredStore_Intrinsic - : Intrinsic<[], + : DefaultAttrsIntrinsic<[], [llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMPointerToElt<0>], [IntrArgMemOnly, NoCapture>]>; class AdvSIMD_SVE_Index_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMVectorElementType<0>, LLVMVectorElementType<0>], [IntrNoMem]>; class AdvSIMD_Merged1VectorArg_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMMatchType<0>], [IntrNoMem]>; class AdvSIMD_2VectorArgIndexed_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty], [IntrNoMem, ImmArg>]>; class AdvSIMD_3VectorArgIndexed_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>, @@ -924,20 +935,20 @@ [IntrNoMem, ImmArg>]>; class AdvSIMD_Pred1VectorArg_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMMatchType<0>], [IntrNoMem]>; class AdvSIMD_Pred2VectorArg_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>; class AdvSIMD_Pred3VectorArg_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMMatchType<0>, LLVMMatchType<0>, @@ -945,77 +956,77 @@ [IntrNoMem]>; class AdvSIMD_SVE_Compare_Intrinsic - : Intrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>], + : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>], [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyvector_ty, LLVMMatchType<0>], [IntrNoMem]>; class AdvSIMD_SVE_CompareWide_Intrinsic - : Intrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>], + : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>], [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyvector_ty, llvm_nxv2i64_ty], [IntrNoMem]>; class AdvSIMD_SVE_Saturating_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>], [IntrNoMem]>; class AdvSIMD_SVE_SaturatingWithPattern_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, llvm_i32_ty, llvm_i32_ty], [IntrNoMem, ImmArg>, ImmArg>]>; class AdvSIMD_SVE_Saturating_N_Intrinsic - : Intrinsic<[T], + : DefaultAttrsIntrinsic<[T], [T, llvm_anyvector_ty], [IntrNoMem]>; class AdvSIMD_SVE_SaturatingWithPattern_N_Intrinsic - : Intrinsic<[T], + : DefaultAttrsIntrinsic<[T], [T, llvm_i32_ty, llvm_i32_ty], [IntrNoMem, ImmArg>, ImmArg>]>; class AdvSIMD_SVE_CNT_Intrinsic - : Intrinsic<[LLVMVectorOfBitcastsToInt<0>], + : DefaultAttrsIntrinsic<[LLVMVectorOfBitcastsToInt<0>], [LLVMVectorOfBitcastsToInt<0>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyvector_ty], [IntrNoMem]>; class AdvSIMD_SVE_ReduceWithInit_Intrinsic - : Intrinsic<[LLVMVectorElementType<0>], + : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>], [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMVectorElementType<0>, llvm_anyvector_ty], [IntrNoMem]>; class AdvSIMD_SVE_ShiftByImm_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMMatchType<0>, llvm_i32_ty], [IntrNoMem, ImmArg>]>; class AdvSIMD_SVE_ShiftWide_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMMatchType<0>, llvm_nxv2i64_ty], [IntrNoMem]>; class AdvSIMD_SVE_Unpack_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMSubdivide2VectorType<0>], [IntrNoMem]>; class AdvSIMD_SVE_CADD_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMMatchType<0>, LLVMMatchType<0>, @@ -1023,7 +1034,7 @@ [IntrNoMem, ImmArg>]>; class AdvSIMD_SVE_CMLA_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMMatchType<0>, LLVMMatchType<0>, @@ -1032,7 +1043,7 @@ [IntrNoMem, ImmArg>]>; class AdvSIMD_SVE_CMLA_LANE_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>, @@ -1041,96 +1052,96 @@ [IntrNoMem, ImmArg>, ImmArg>]>; class AdvSIMD_SVE_DUP_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMVectorElementType<0>], [IntrNoMem]>; class AdvSIMD_SVE_DUP_Unpred_Intrinsic - : Intrinsic<[llvm_anyvector_ty], [LLVMVectorElementType<0>], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMVectorElementType<0>], [IntrNoMem]>; class AdvSIMD_SVE_DUPQ_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, llvm_i64_ty], [IntrNoMem]>; class AdvSIMD_SVE_EXPA_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMVectorOfBitcastsToInt<0>], [IntrNoMem]>; class AdvSIMD_SVE_FCVT_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyvector_ty], [IntrNoMem]>; class AdvSIMD_SVE_FCVTZS_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMVectorOfBitcastsToInt<0>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyvector_ty], [IntrNoMem]>; class AdvSIMD_SVE_INSR_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMVectorElementType<0>], [IntrNoMem]>; class AdvSIMD_SVE_PTRUE_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_i32_ty], [IntrNoMem, ImmArg>]>; class AdvSIMD_SVE_PUNPKHI_Intrinsic - : Intrinsic<[LLVMHalfElementsVectorType<0>], + : DefaultAttrsIntrinsic<[LLVMHalfElementsVectorType<0>], [llvm_anyvector_ty], [IntrNoMem]>; class AdvSIMD_SVE_SCALE_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMMatchType<0>, LLVMVectorOfBitcastsToInt<0>], [IntrNoMem]>; class AdvSIMD_SVE_SCVTF_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyvector_ty], [IntrNoMem]>; class AdvSIMD_SVE_TSMUL_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMVectorOfBitcastsToInt<0>], [IntrNoMem]>; class AdvSIMD_SVE_CNTB_Intrinsic - : Intrinsic<[llvm_i64_ty], + : DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_i32_ty], [IntrNoMem, ImmArg>]>; class AdvSIMD_SVE_CNTP_Intrinsic - : Intrinsic<[llvm_i64_ty], + : DefaultAttrsIntrinsic<[llvm_i64_ty], [llvm_anyvector_ty, LLVMMatchType<0>], [IntrNoMem]>; class AdvSIMD_SVE_DOT_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMSubdivide4VectorType<0>, LLVMSubdivide4VectorType<0>], [IntrNoMem]>; class AdvSIMD_SVE_DOT_Indexed_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMSubdivide4VectorType<0>, LLVMSubdivide4VectorType<0>, @@ -1138,65 +1149,65 @@ [IntrNoMem, ImmArg>]>; class AdvSIMD_SVE_PTEST_Intrinsic - : Intrinsic<[llvm_i1_ty], + : DefaultAttrsIntrinsic<[llvm_i1_ty], [llvm_anyvector_ty, LLVMMatchType<0>], [IntrNoMem]>; class AdvSIMD_SVE_TBL_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMVectorOfBitcastsToInt<0>], [IntrNoMem]>; class AdvSIMD_SVE2_TBX_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>, LLVMVectorOfBitcastsToInt<0>], [IntrNoMem]>; class SVE2_1VectorArg_Long_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMSubdivide2VectorType<0>, llvm_i32_ty], [IntrNoMem, ImmArg>]>; class SVE2_2VectorArg_Long_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMSubdivide2VectorType<0>, LLVMSubdivide2VectorType<0>], [IntrNoMem]>; class SVE2_2VectorArgIndexed_Long_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMSubdivide2VectorType<0>, LLVMSubdivide2VectorType<0>, llvm_i32_ty], [IntrNoMem, ImmArg>]>; class SVE2_2VectorArg_Wide_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMSubdivide2VectorType<0>], [IntrNoMem]>; class SVE2_2VectorArg_Pred_Long_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMMatchType<0>, LLVMSubdivide2VectorType<0>], [IntrNoMem]>; class SVE2_3VectorArg_Long_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMSubdivide2VectorType<0>, LLVMSubdivide2VectorType<0>], [IntrNoMem]>; class SVE2_3VectorArgIndexed_Long_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMSubdivide2VectorType<0>, LLVMSubdivide2VectorType<0>, @@ -1204,45 +1215,45 @@ [IntrNoMem, ImmArg>]>; class SVE2_1VectorArg_Narrowing_Intrinsic - : Intrinsic<[LLVMSubdivide2VectorType<0>], + : DefaultAttrsIntrinsic<[LLVMSubdivide2VectorType<0>], [llvm_anyvector_ty], [IntrNoMem]>; class SVE2_Merged1VectorArg_Narrowing_Intrinsic - : Intrinsic<[LLVMSubdivide2VectorType<0>], + : DefaultAttrsIntrinsic<[LLVMSubdivide2VectorType<0>], [LLVMSubdivide2VectorType<0>, llvm_anyvector_ty], [IntrNoMem]>; class SVE2_2VectorArg_Narrowing_Intrinsic - : Intrinsic< + : DefaultAttrsIntrinsic< [LLVMSubdivide2VectorType<0>], [llvm_anyvector_ty, LLVMMatchType<0>], [IntrNoMem]>; class SVE2_Merged2VectorArg_Narrowing_Intrinsic - : Intrinsic< + : DefaultAttrsIntrinsic< [LLVMSubdivide2VectorType<0>], [LLVMSubdivide2VectorType<0>, llvm_anyvector_ty, LLVMMatchType<0>], [IntrNoMem]>; class SVE2_1VectorArg_Imm_Narrowing_Intrinsic - : Intrinsic<[LLVMSubdivide2VectorType<0>], + : DefaultAttrsIntrinsic<[LLVMSubdivide2VectorType<0>], [llvm_anyvector_ty, llvm_i32_ty], [IntrNoMem, ImmArg>]>; class SVE2_2VectorArg_Imm_Narrowing_Intrinsic - : Intrinsic<[LLVMSubdivide2VectorType<0>], + : DefaultAttrsIntrinsic<[LLVMSubdivide2VectorType<0>], [LLVMSubdivide2VectorType<0>, llvm_anyvector_ty, llvm_i32_ty], [IntrNoMem, ImmArg>]>; class SVE2_CONFLICT_DETECT_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMAnyPointerType, LLVMMatchType<1>]>; class SVE2_3VectorArg_Indexed_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMSubdivide2VectorType<0>, LLVMSubdivide2VectorType<0>, @@ -1250,7 +1261,7 @@ [IntrNoMem, ImmArg>]>; class AdvSIMD_SVE_CDOT_LANE_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMSubdivide4VectorType<0>, LLVMSubdivide4VectorType<0>, @@ -1267,7 +1278,7 @@ // This class of intrinsics are not intended to be useful within LLVM IR but // are instead here to support some of the more regid parts of the ACLE. class Builtin_SVCVT - : Intrinsic<[OUT], [OUT, PRED, IN], [IntrNoMem]>; + : DefaultAttrsIntrinsic<[OUT], [OUT, PRED, IN], [IntrNoMem]>; } //===----------------------------------------------------------------------===// @@ -1276,24 +1287,24 @@ let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.". class AdvSIMD_SVE_Reduce_Intrinsic - : Intrinsic<[LLVMVectorElementType<0>], + : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>], [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyvector_ty], [IntrNoMem]>; class AdvSIMD_SVE_SADDV_Reduce_Intrinsic - : Intrinsic<[llvm_i64_ty], + : DefaultAttrsIntrinsic<[llvm_i64_ty], [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyvector_ty], [IntrNoMem]>; class AdvSIMD_SVE_WHILE_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_anyint_ty, LLVMMatchType<1>], [IntrNoMem]>; class AdvSIMD_GatherLoad_SV_64b_Offsets_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMPointerToElt<0>, @@ -1302,7 +1313,7 @@ [IntrReadMem, IntrArgMemOnly]>; class AdvSIMD_GatherLoad_SV_32b_Offsets_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMPointerToElt<0>, @@ -1311,7 +1322,7 @@ [IntrReadMem, IntrArgMemOnly]>; class AdvSIMD_GatherLoad_VS_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyvector_ty, @@ -1320,7 +1331,7 @@ [IntrReadMem]>; class AdvSIMD_ScatterStore_SV_64b_Offsets_Intrinsic - : Intrinsic<[], + : DefaultAttrsIntrinsic<[], [ llvm_anyvector_ty, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, @@ -1330,7 +1341,7 @@ [IntrWriteMem, IntrArgMemOnly]>; class AdvSIMD_ScatterStore_SV_32b_Offsets_Intrinsic - : Intrinsic<[], + : DefaultAttrsIntrinsic<[], [ llvm_anyvector_ty, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, @@ -1340,7 +1351,7 @@ [IntrWriteMem, IntrArgMemOnly]>; class AdvSIMD_ScatterStore_VS_Intrinsic - : Intrinsic<[], + : DefaultAttrsIntrinsic<[], [ llvm_anyvector_ty, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, @@ -1350,7 +1361,7 @@ class SVE_gather_prf_SV - : Intrinsic<[], + : DefaultAttrsIntrinsic<[], [ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, // Predicate llvm_ptr_ty, // Base address @@ -1360,7 +1371,7 @@ [IntrInaccessibleMemOrArgMemOnly, NoCapture>, ImmArg>]>; class SVE_gather_prf_VS - : Intrinsic<[], + : DefaultAttrsIntrinsic<[], [ LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, // Predicate llvm_anyvector_ty, // Base addresses @@ -1370,17 +1381,17 @@ [IntrInaccessibleMemOrArgMemOnly, ImmArg>]>; class SVE_MatMul_Intrinsic - : Intrinsic<[llvm_anyvector_ty], + : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMSubdivide4VectorType<0>, LLVMSubdivide4VectorType<0>], [IntrNoMem]>; class SVE_4Vec_BF16 - : Intrinsic<[llvm_nxv4f32_ty], + : DefaultAttrsIntrinsic<[llvm_nxv4f32_ty], [llvm_nxv4f32_ty, llvm_nxv8bf16_ty, llvm_nxv8bf16_ty], [IntrNoMem]>; class SVE_4Vec_BF16_Indexed - : Intrinsic<[llvm_nxv4f32_ty], + : DefaultAttrsIntrinsic<[llvm_nxv4f32_ty], [llvm_nxv4f32_ty, llvm_nxv8bf16_ty, llvm_nxv8bf16_ty, llvm_i64_ty], [IntrNoMem, ImmArg>]>; @@ -1432,7 +1443,7 @@ // def int_aarch64_sve_prf - : Intrinsic<[], [llvm_anyvector_ty, llvm_ptr_ty, llvm_i32_ty], + : DefaultAttrsIntrinsic<[], [llvm_anyvector_ty, llvm_ptr_ty, llvm_i32_ty], [IntrArgMemOnly, ImmArg>]>; // Scalar + 32-bit scaled offset vector, zero extend, packed and @@ -1596,10 +1607,10 @@ // FFR manipulation // -def int_aarch64_sve_rdffr : GCCBuiltin<"__builtin_sve_svrdffr">, Intrinsic<[llvm_nxv16i1_ty], []>; -def int_aarch64_sve_rdffr_z : GCCBuiltin<"__builtin_sve_svrdffr_z">, Intrinsic<[llvm_nxv16i1_ty], [llvm_nxv16i1_ty]>; -def int_aarch64_sve_setffr : GCCBuiltin<"__builtin_sve_svsetffr">, Intrinsic<[], []>; -def int_aarch64_sve_wrffr : GCCBuiltin<"__builtin_sve_svwrffr">, Intrinsic<[], [llvm_nxv16i1_ty]>; +def int_aarch64_sve_rdffr : GCCBuiltin<"__builtin_sve_svrdffr">, DefaultAttrsIntrinsic<[llvm_nxv16i1_ty], []>; +def int_aarch64_sve_rdffr_z : GCCBuiltin<"__builtin_sve_svrdffr_z">, DefaultAttrsIntrinsic<[llvm_nxv16i1_ty], [llvm_nxv16i1_ty]>; +def int_aarch64_sve_setffr : GCCBuiltin<"__builtin_sve_svsetffr">, DefaultAttrsIntrinsic<[], []>; +def int_aarch64_sve_wrffr : GCCBuiltin<"__builtin_sve_svwrffr">, DefaultAttrsIntrinsic<[], [llvm_nxv16i1_ty]>; // // Saturating scalar arithmetic @@ -1912,11 +1923,11 @@ // Reinterpreting data // -def int_aarch64_sve_convert_from_svbool : Intrinsic<[llvm_anyvector_ty], +def int_aarch64_sve_convert_from_svbool : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [llvm_nxv16i1_ty], [IntrNoMem]>; -def int_aarch64_sve_convert_to_svbool : Intrinsic<[llvm_nxv16i1_ty], +def int_aarch64_sve_convert_to_svbool : DefaultAttrsIntrinsic<[llvm_nxv16i1_ty], [llvm_anyvector_ty], [IntrNoMem]>; @@ -2331,31 +2342,31 @@ // def int_aarch64_sve_aesd : GCCBuiltin<"__builtin_sve_svaesd_u8">, - Intrinsic<[llvm_nxv16i8_ty], + DefaultAttrsIntrinsic<[llvm_nxv16i8_ty], [llvm_nxv16i8_ty, llvm_nxv16i8_ty], [IntrNoMem]>; def int_aarch64_sve_aesimc : GCCBuiltin<"__builtin_sve_svaesimc_u8">, - Intrinsic<[llvm_nxv16i8_ty], + DefaultAttrsIntrinsic<[llvm_nxv16i8_ty], [llvm_nxv16i8_ty], [IntrNoMem]>; def int_aarch64_sve_aese : GCCBuiltin<"__builtin_sve_svaese_u8">, - Intrinsic<[llvm_nxv16i8_ty], + DefaultAttrsIntrinsic<[llvm_nxv16i8_ty], [llvm_nxv16i8_ty, llvm_nxv16i8_ty], [IntrNoMem]>; def int_aarch64_sve_aesmc : GCCBuiltin<"__builtin_sve_svaesmc_u8">, - Intrinsic<[llvm_nxv16i8_ty], + DefaultAttrsIntrinsic<[llvm_nxv16i8_ty], [llvm_nxv16i8_ty], [IntrNoMem]>; def int_aarch64_sve_rax1 : GCCBuiltin<"__builtin_sve_svrax1_u64">, - Intrinsic<[llvm_nxv2i64_ty], + DefaultAttrsIntrinsic<[llvm_nxv2i64_ty], [llvm_nxv2i64_ty, llvm_nxv2i64_ty], [IntrNoMem]>; def int_aarch64_sve_sm4e : GCCBuiltin<"__builtin_sve_svsm4e_u32">, - Intrinsic<[llvm_nxv4i32_ty], + DefaultAttrsIntrinsic<[llvm_nxv4i32_ty], [llvm_nxv4i32_ty, llvm_nxv4i32_ty], [IntrNoMem]>; def int_aarch64_sve_sm4ekey : GCCBuiltin<"__builtin_sve_svsm4ekey_u32">, - Intrinsic<[llvm_nxv4i32_ty], + DefaultAttrsIntrinsic<[llvm_nxv4i32_ty], [llvm_nxv4i32_ty, llvm_nxv4i32_ty], [IntrNoMem]>; // diff --git a/llvm/test/Assembler/aarch64-intrinsics-attributes.ll b/llvm/test/Assembler/aarch64-intrinsics-attributes.ll --- a/llvm/test/Assembler/aarch64-intrinsics-attributes.ll +++ b/llvm/test/Assembler/aarch64-intrinsics-attributes.ll @@ -4,23 +4,23 @@ ; Make sure some AArch64 intrinsics have the expected attributes. -; CHECK: declare i64 @llvm.aarch64.ldxr.p0i64(i64*) [[NOUNWIND:#[0-9]+]] +; CHECK: declare i64 @llvm.aarch64.ldxr.p0i64(i64*) [[NOFREE_NOUNWIND_WILLRETURN:#[0-9]+]] declare i64 @llvm.aarch64.ldxr.p0i64(i64*) -; CHECK: declare i32 @llvm.aarch64.stxp(i64, i64, i32*) [[NOUNWIND]] +; CHECK: declare i32 @llvm.aarch64.stxp(i64, i64, i32*) [[NOFREE_NOUNWIND_WILLRETURN]] declare i32 @llvm.aarch64.stxp(i64, i64, i32*) -; CHECK: declare i32 @llvm.aarch64.dsb(i32) [[NOUNWIND]] +; CHECK: declare i32 @llvm.aarch64.dsb(i32) [[NOFREE_NOUNWIND_WILLRETURN]] declare i32 @llvm.aarch64.dsb(i32) -; CHECK: declare i64 @llvm.aarch64.neon.sqdmulls.scalar(i32, i32) [[NOUNWIND_READNONE:#[0-9]+]] +; CHECK: declare i64 @llvm.aarch64.neon.sqdmulls.scalar(i32, i32) [[NOFREE_NOSYNC_NOUNWIND_READNONE_WILLRETURN:#[0-9]+]] declare i64 @llvm.aarch64.neon.sqdmulls.scalar(i32, i32) -; CHECK: declare <4 x i32> @llvm.aarch64.neon.shadd.v4i32(<4 x i32>, <4 x i32>) [[NOUNWIND_READNONE]] +; CHECK: declare <4 x i32> @llvm.aarch64.neon.shadd.v4i32(<4 x i32>, <4 x i32>) [[NOFREE_NOSYNC_NOUNWIND_READNONE_WILLRETURN]] declare <4 x i32> @llvm.aarch64.neon.shadd.v4i32(<4 x i32>, <4 x i32>) -; CHECK: declare @llvm.aarch64.sve.dup.nxv4i32(, , i32) [[NOUNWIND_READNONE]] +; CHECK: declare @llvm.aarch64.sve.dup.nxv4i32(, , i32) [[NOFREE_NOSYNC_NOUNWIND_READNONE_WILLRETURN]] declare @llvm.aarch64.sve.dup.nxv4i32(, , i32) -; CHECK: attributes [[NOUNWIND]] = { nounwind } -; CHECK: attributes [[NOUNWIND_READNONE]] = { nounwind readnone } +; CHECK: attributes [[NOFREE_NOUNWIND_WILLRETURN]] = { nofree nounwind willreturn } +; CHECK: attributes [[NOFREE_NOSYNC_NOUNWIND_READNONE_WILLRETURN]] = { nofree nosync nounwind readnone willreturn }