diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -370,8 +370,8 @@
 } // Predicates = [HasStdExtZbp]
 
 let Predicates = [HasStdExtZbb, IsRV64] in {
-def SLLIUW : RVBShift_ri<0b00001, 0b001, OPC_OP_IMM_32, "slliu.w">, Sched<[]>;
-def ADDUW : ALUW_rr<0b0000100, 0b000, "addu.w">, Sched<[]>;
+def SLLIUW : RVBShift_ri<0b00001, 0b001, OPC_OP_IMM_32, "slli.uw">, Sched<[]>;
+def ADDUW : ALUW_rr<0b0000100, 0b000, "add.uw">, Sched<[]>;
 } // Predicates = [HasStdExtZbb, IsRV64]
 
 let Predicates = [HasStdExtZbb, IsRV64] in {
diff --git a/llvm/test/CodeGen/RISCV/rv64Zbb.ll b/llvm/test/CodeGen/RISCV/rv64Zbb.ll
--- a/llvm/test/CodeGen/RISCV/rv64Zbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64Zbb.ll
@@ -1000,12 +1000,12 @@
 ;
 ; RV64IB-LABEL: slliuw:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    slliu.w a0, a0, 1
+; RV64IB-NEXT:    slli.uw a0, a0, 1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBB-LABEL: slliuw:
 ; RV64IBB:       # %bb.0:
-; RV64IBB-NEXT:    slliu.w a0, a0, 1
+; RV64IBB-NEXT:    slli.uw a0, a0, 1
 ; RV64IBB-NEXT:    ret
   %conv1 = shl i64 %a, 1
   %shl = and i64 %conv1, 8589934590
@@ -1025,7 +1025,7 @@
 ;
 ; RV64IB-LABEL: slliuw_2:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    slliu.w a0, a0, 4
+; RV64IB-NEXT:    slli.uw a0, a0, 4
 ; RV64IB-NEXT:    add a1, a1, a0
 ; RV64IB-NEXT:    ld a0, 0(a1)
 ; RV64IB-NEXT:    ld a1, 8(a1)
@@ -1033,7 +1033,7 @@
 ;
 ; RV64IBB-LABEL: slliuw_2:
 ; RV64IBB:       # %bb.0:
-; RV64IBB-NEXT:    slliu.w a0, a0, 4
+; RV64IBB-NEXT:    slli.uw a0, a0, 4
 ; RV64IBB-NEXT:    add a1, a1, a0
 ; RV64IBB-NEXT:    ld a0, 0(a1)
 ; RV64IBB-NEXT:    ld a1, 8(a1)
@@ -1054,12 +1054,12 @@
 ;
 ; RV64IB-LABEL: adduw:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    addu.w a0, a0, a1
+; RV64IB-NEXT:    add.uw a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBB-LABEL: adduw:
 ; RV64IBB:       # %bb.0:
-; RV64IBB-NEXT:    addu.w a0, a0, a1
+; RV64IBB-NEXT:    add.uw a0, a0, a1
 ; RV64IBB-NEXT:    ret
   %and = and i64 %b, 4294967295
   %add = add i64 %and, %a
@@ -1077,13 +1077,13 @@
 ;
 ; RV64IB-LABEL: adduw_2:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    addu.w a0, a1, a0
+; RV64IB-NEXT:    add.uw a0, a1, a0
 ; RV64IB-NEXT:    lb a0, 0(a0)
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBB-LABEL: adduw_2:
 ; RV64IBB:       # %bb.0:
-; RV64IBB-NEXT:    addu.w a0, a1, a0
+; RV64IBB-NEXT:    add.uw a0, a1, a0
 ; RV64IBB-NEXT:    lb a0, 0(a0)
 ; RV64IBB-NEXT:    ret
   %3 = zext i32 %0 to i64
diff --git a/llvm/test/MC/RISCV/rv64zbb-invalid.s b/llvm/test/MC/RISCV/rv64zbb-invalid.s
--- a/llvm/test/MC/RISCV/rv64zbb-invalid.s
+++ b/llvm/test/MC/RISCV/rv64zbb-invalid.s
@@ -1,12 +1,12 @@
 # RUN: not llvm-mc -triple riscv64 -mattr=+experimental-b,experimental-zbb < %s 2>&1 | FileCheck %s
 
 # Too few operands
-slliu.w t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+slli.uw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Immediate operand out of range
-slliu.w t0, t1, 64 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 63]
-slliu.w t0, t1, -1 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 63]
+slli.uw t0, t1, 64 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 63]
+slli.uw t0, t1, -1 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 63]
 # Too few operands
-addu.w t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+add.uw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
 slow t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 # Too few operands
diff --git a/llvm/test/MC/RISCV/rv64zbb-valid.s b/llvm/test/MC/RISCV/rv64zbb-valid.s
--- a/llvm/test/MC/RISCV/rv64zbb-valid.s
+++ b/llvm/test/MC/RISCV/rv64zbb-valid.s
@@ -12,12 +12,12 @@
 # RUN:     | llvm-objdump --mattr=+experimental-zbb -d -r - \
 # RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
 
-# CHECK-ASM-AND-OBJ: slliu.w t0, t1, 0
+# CHECK-ASM-AND-OBJ: slli.uw t0, t1, 0
 # CHECK-ASM: encoding: [0x9b,0x12,0x03,0x08]
-slliu.w t0, t1, 0
-# CHECK-ASM-AND-OBJ: addu.w t0, t1, t2
+slli.uw t0, t1, 0
+# CHECK-ASM-AND-OBJ: add.uw t0, t1, t2
 # CHECK-ASM: encoding: [0xbb,0x02,0x73,0x08]
-addu.w t0, t1, t2
+add.uw t0, t1, t2
 # CHECK-ASM-AND-OBJ: slow t0, t1, t2
 # CHECK-ASM: encoding: [0xbb,0x12,0x73,0x20]
 slow t0, t1, t2