This patch added the MC layer support of P extension.
Authored-by: Shao-Ce Sun
achieveartificialintelligence on Jan 12 2021, 7:38 PM.Authored by
Please make sure there are tests for invalid instructions (especially checking you have the immediate ranges and predicates correct).
I have not looked at the draft P spec so these are all shallow comments from glancing over the diff.
It seems lack of invalid operand handling for new added operand (uimm3, uimm4) in AsmParser/RISCVAsmParser.cpp:MatchAndEmitInstruction.
Thanks for submitting this. It doesn't apply against current HEAD, could you please rebase?
One minor request before reviewing in detail - could you please confirm the version of the spec this is meant to implement? Is it 0.9.1 at https://github.com/riscv/riscv-p-spec/blob/master/P-ext-proposal.adoc#revision-history ? It would also be good to indicate this version number in RISCVInstrInfoP.td just as we do for RISCVInstrInfoB.td.
The registers used in most 'P' instruction should have v4i8 and v2i16 types for RV32 or v8i8 and v4i16 for RV64.
Per our discussion in the RISC-V community call today, this patch is intended as more of a "request for comment" at this stage given the P extension encoding issues, and PLCT Lab + Andes are going to reach out to each other to try to coordinate these MC layer and future codegen patches (thanks!).