Page MenuHomePhabricator

[AArch64] Add some missing fusion subtarget features
ClosedPublic

Authored by porglezomp on Jan 11 2021, 2:55 PM.

Details

Summary

Referencing ARM's software optimization guides:

A65 - 4.8 Instruction fusion

Address, AES, and MOVZ/MOVK literals

A72 - 4.11 Fast literal generation

  • 4.12 PC-relative address calculation

A76 - 4.6. AES Encryption/Decryption
A77/A78/A78C/X1 - 4.13 Instruction fusion

CMP/CMN, TST, BICS + B.cond fusion
AES fusion

[AArch64] Make Cortex B.cc fusions more precise

The ArithmeticBccFusion feature expects to be able to fuse general
flag-updating arithmetic with a B.cc, for example an arbitrary SUBS
instructions and not just a CMP.

Since the Cortex cores are documented as fusing CMP/CMN/TST, and the A77
optimization guide specifies that BICS fusion must have a destination of
XZR or WZR, these cores should use a separate subtarget feature for
specifically fusing only comparisons with B.cc.

Diff Detail

Event Timeline

porglezomp created this revision.Jan 11 2021, 2:55 PM
porglezomp requested review of this revision.Jan 11 2021, 2:55 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 11 2021, 2:55 PM

The existing fusion tests seem a little bit weak—the machine scheduler with the base Cortex-A57 machine models that most of those use seemed to pass the address and literal fusion on its own (by coincidence?) without the explicit features requested. I was unable to make that test case stronger to see the A57 machine model not exploiting those fusion pairs when the feature was disabled. Is that worth worrying about?

SjoerdMeijer accepted this revision.Jan 21 2021, 6:10 AM
SjoerdMeijer added a subscriber: SjoerdMeijer.

Thank, LGTM.

The existing fusion tests seem a little bit weak—the machine scheduler with the base Cortex-A57 machine models that most of those use seemed to pass the address and literal fusion on its own (by coincidence?) without the explicit features requested. I was unable to make that test case stronger to see the A57 machine model not exploiting those fusion pairs when the feature was disabled. Is that worth worrying about?

Yeah, perhaps there's room for improvement, it's not something that worries me very much.

llvm/lib/Target/AArch64/AArch64.td
221

Yep, makes sense I think.

624

Check

637

Check

669

Check

683

Check

694

Check

711

Check

739

Check

This revision is now accepted and ready to land.Jan 21 2021, 6:10 AM

I don't have commit access, so could someone commit the change for me? Thanks.

Thanks for contributing this. I have committed this on your behalf in rG815dd4b29208.
If you plan to do more LLVM work, you can always consider requesting an account so you can commit patches yourself (but am of course happy to do it on your behalf).