Referencing ARM's software optimization guides:
A65 - 4.8 Instruction fusion
Address, AES, and MOVZ/MOVK literals
A72 - 4.11 Fast literal generation
- 4.12 PC-relative address calculation
A76 - 4.6. AES Encryption/Decryption
A77/A78/A78C/X1 - 4.13 Instruction fusion
CMP/CMN, TST, BICS + B.cond fusion AES fusion
[AArch64] Make Cortex B.cc fusions more precise
The ArithmeticBccFusion feature expects to be able to fuse general
flag-updating arithmetic with a B.cc, for example an arbitrary SUBS
instructions and not just a CMP.
Since the Cortex cores are documented as fusing CMP/CMN/TST, and the A77
optimization guide specifies that BICS fusion must have a destination of
XZR or WZR, these cores should use a separate subtarget feature for
specifically fusing only comparisons with B.cc.