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Differential D94450

[LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of SETONE/SETUEQ on targets without SETO/SETUO.
ClosedPublic

Authored by craig.topper on Jan 11 2021, 1:55 PM.

Details

Reviewers
frasercrmck
efriedma
arsenm
evandro
asb
lenary
tlively
nemanjai
Commits
rG03c8d6a0c4bd: [LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of…
Summary

If SETO/SETUO aren't legal, they'll be expanded and we'll end up
with 3 comparisons.

SETONE is equivalent to (SETOGT || SETOLT)
so if one of those operations is supported use that expansion. We
don't need both since we can commute the operands to make the other.

SETUEQ can be implemented with !(SETOGT || SETOLT) or (SETULE && SETUGE).
I've only implemented the first because it didn't look like most of the
affected targets had legal SETULE/SETUGE.

Diff Detail

Event Timeline

craig.topper created this revision.Jan 11 2021, 1:55 PM
Herald added subscribers: NickHung, ecnelises, kerbowa and 38 others. · View Herald TranscriptJan 11 2021, 1:55 PM
craig.topper requested review of this revision.Jan 11 2021, 1:55 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 11 2021, 1:55 PM
Herald added subscribers: MaskRay, aheejin, wdng. · View Herald Transcript
tlively accepted this revision.Jan 11 2021, 2:53 PM

Nice! this looks like a good improvement for WebAssembly at least.

This revision is now accepted and ready to land.Jan 11 2021, 2:53 PM
Harbormaster completed remote builds in B84757: Diff 315930.Jan 11 2021, 3:04 PM
frasercrmck accepted this revision.Jan 12 2021, 2:37 AM

LGTM other than my suggestion.

llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
1747

Minor, but maybe we could put into the comments the part of the commit message explaining why only one of OGT/OLT have to be legal for this to be worthwhile? I think that's quite useful background for anyone coming across this in the future.

nemanjai accepted this revision.Jan 12 2021, 4:54 AM

LGTM for PPC. Thanks for this improvement.

lenary added a comment.Jan 12 2021, 9:38 AM

Looking good on the RISC-V side.

Would you mind removing the out-of-date TODOs? They were out of date before, but with this change they're even more out of date.

llvm/test/CodeGen/RISCV/double-br-fcmp.ll
307–308

Please can you remove this TODO, as it is no longer relevant?

llvm/test/CodeGen/RISCV/double-select-fcmp.ll
208–209

And here.

llvm/test/CodeGen/RISCV/float-br-fcmp.ll
284–285

and here

llvm/test/CodeGen/RISCV/float-select-fcmp.ll
167–168

And this one

llvm/test/CodeGen/RISCV/half-br-fcmp.ll
260–261

And here!

llvm/test/CodeGen/RISCV/half-select-fcmp.ll
137–138

and here!

This revision was landed with ongoing or failed builds.Jan 12 2021, 10:52 AM
Closed by commit rG03c8d6a0c4bd: [LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of… (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG03c8d6a0c4bd: [LegalizeDAG][RISCV][PowerPC][AMDGPU][WebAssembly] Improve expansion of….
lenary mentioned this in D94535: [RISCV] Optimize Branch Comparisons.Jan 12 2021, 11:22 AM
bjope added a subscriber: bjope.Jan 14 2021, 11:03 AM
bjope added inline comments.
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
3964

NeedInvert is not handled here so this assert started to fail for our OOT target.

Haven't really investigate it yet. But should the code here support NeedInvert (or one should tell LegalizeSetCCCondCode above that legalization using NeedInvert isn't allowed).

craig.topper added inline comments.Jan 14 2021, 11:21 AM
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
3964

I think it's not possible to invert it if Tmp4.getNode() is true below. But I think it should be false for the case this patch introduced.

So I think we can move the assert into the if at line 3969. And pick ISD::SETEQ instead of ISD::SETNE on line 3973 if NeedInvert is true.

bjope added inline comments.Jan 14 2021, 12:10 PM
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
3964

Right. Thanks!
I'll play around with that tomorrow.

lenary mentioned this in rG141e45b99ca0: [RISCV] Optimize Branch Comparisons.Jan 15 2021, 3:29 AM
bjope added inline comments.Jan 15 2021, 4:00 AM
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
3964

Proposed a fix: https://reviews.llvm.org/D94762

Revision Contents

PathSize
llvm/
lib/
CodeGen/
SelectionDAG/
19 lines
test/
CodeGen/
AMDGPU/
16 lines
PowerPC/
49 lines
40 lines
RISCV/
53 lines
48 lines
51 lines
51 lines
46 lines
43 lines
43 lines
38 lines
39 lines
rvv/
156 lines
156 lines
WebAssembly/
28 lines
28 lines
68 lines

Diff 316164

llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Show First 20 Lines • Show All 1,735 Lines • ▼ Show 20 Lines case ISD::SETUO:
assert(TLI.isCondCodeLegal(ISD::SETOEQ, OpVT) && assert(TLI.isCondCodeLegal(ISD::SETOEQ, OpVT) &&
"If SETUE is expanded, SETOEQ or SETUNE must be legal!"); "If SETUE is expanded, SETOEQ or SETUNE must be legal!");
NeedInvert = true; NeedInvert = true;
LLVM_FALLTHROUGH; LLVM_FALLTHROUGH;
case ISD::SETO: case ISD::SETO:
assert(TLI.isCondCodeLegal(ISD::SETOEQ, OpVT) assert(TLI.isCondCodeLegal(ISD::SETOEQ, OpVT)
&& "If SETO is expanded, SETOEQ must be legal!"); && "If SETO is expanded, SETOEQ must be legal!");
CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break; CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
case ISD::SETONE:
case ISD::SETUEQ:
// If the SETUO or SETO CC isn't legal, we might be able to use
// SETOGT || SETOLT, inverting the result for SETUEQ. We only need one
frasercrmckUnsubmitted
Not Done
ReplyInline Actions

Minor, but maybe we could put into the comments the part of the commit message explaining why only one of OGT/OLT have to be legal for this to be worthwhile? I think that's quite useful background for anyone coming across this in the future.

frasercrmck: Minor, but maybe we could put into the comments the part of the commit message explaining why…
// of SETOGT/SETOLT to be legal, the other can be emulated by swapping
// the operands.
CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
if (!TLI.isCondCodeLegal(CC2, OpVT) &&
(TLI.isCondCodeLegal(ISD::SETOGT, OpVT) ||
TLI.isCondCodeLegal(ISD::SETOLT, OpVT))) {
CC1 = ISD::SETOGT;
CC2 = ISD::SETOLT;
Opc = ISD::OR;
NeedInvert = ((unsigned)CCCode & 0x8U);
break;
}
LLVM_FALLTHROUGH;
case ISD::SETOEQ: case ISD::SETOEQ:
case ISD::SETOGT: case ISD::SETOGT:
case ISD::SETOGE: case ISD::SETOGE:
case ISD::SETOLT: case ISD::SETOLT:
case ISD::SETOLE: case ISD::SETOLE:
case ISD::SETONE:
case ISD::SETUEQ:
case ISD::SETUNE: case ISD::SETUNE:
case ISD::SETUGT: case ISD::SETUGT:
case ISD::SETUGE: case ISD::SETUGE:
case ISD::SETULT: case ISD::SETULT:
case ISD::SETULE: case ISD::SETULE:
// If we are floating point, assign and break, otherwise fall through. // If we are floating point, assign and break, otherwise fall through.
if (!OpVT.isInteger()) { if (!OpVT.isInteger()) {
// We can use the 4th bit to tell if we are the unordered // We can use the 4th bit to tell if we are the unordered
▲ Show 20 Lines • Show All 2,182 Lines • ▼ Show 20 Lines case ISD::BR_CC: {
Tmp4 = Node->getOperand(1); // CC Tmp4 = Node->getOperand(1); // CC
bool Legalized = bool Legalized =
LegalizeSetCCCondCode(getSetCCResultType(Tmp2.getValueType()), Tmp2, LegalizeSetCCCondCode(getSetCCResultType(Tmp2.getValueType()), Tmp2,
Tmp3, Tmp4, NeedInvert, dl, Chain); Tmp3, Tmp4, NeedInvert, dl, Chain);
(void)Legalized; (void)Legalized;
assert(Legalized && "Can't legalize BR_CC with legal condition!"); assert(Legalized && "Can't legalize BR_CC with legal condition!");
assert(!NeedInvert && "Don't know how to invert BR_CC!"); assert(!NeedInvert && "Don't know how to invert BR_CC!");
bjopeUnsubmitted
Not Done
ReplyInline Actions

NeedInvert is not handled here so this assert started to fail for our OOT target.

Haven't really investigate it yet. But should the code here support NeedInvert (or one should tell LegalizeSetCCCondCode above that legalization using NeedInvert isn't allowed).

bjope: NeedInvert is not handled here so this assert started to fail for our OOT target. Haven't…
craig.topperAuthorUnsubmitted
Done
ReplyInline Actions

I think it's not possible to invert it if Tmp4.getNode() is true below. But I think it should be false for the case this patch introduced.

So I think we can move the assert into the if at line 3969. And pick ISD::SETEQ instead of ISD::SETNE on line 3973 if NeedInvert is true.

craig.topper: I think it's not possible to invert it if Tmp4.getNode() is true below. But I think it should…
bjopeUnsubmitted
Not Done
ReplyInline Actions

Right. Thanks!
I'll play around with that tomorrow.

bjope: Right. Thanks! I'll play around with that tomorrow.
bjopeUnsubmitted
Not Done
ReplyInline Actions

Proposed a fix: https://reviews.llvm.org/D94762

bjope: Proposed a fix: https://reviews.llvm.org/D94762
// If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
// node. // node.
if (Tmp4.getNode()) { if (Tmp4.getNode()) {
Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
Tmp4, Tmp2, Tmp3, Node->getOperand(4)); Tmp4, Tmp2, Tmp3, Node->getOperand(4));
} else { } else {
Tmp3 = DAG.getConstant(0, dl, Tmp2.getValueType()); Tmp3 = DAG.getConstant(0, dl, Tmp2.getValueType());
▲ Show 20 Lines • Show All 1,231 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/setcc.ll

Show First 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
entry: entry:
%0 = fcmp ole float %a, %b %0 = fcmp ole float %a, %b
%1 = sext i1 %0 to i32 %1 = sext i1 %0 to i32
store i32 %1, i32 addrspace(1)* %out store i32 %1, i32 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}f32_one: ; FUNC-LABEL: {{^}}f32_one:
; R600-DAG: SETE_DX10 ; R600-DAG: SETGT_DX10
; R600-DAG: SETE_DX10 ; R600-DAG: SETGT_DX10
; R600-DAG: AND_INT ; R600-DAG: OR_INT
; R600-DAG: SETNE_DX10
; R600-DAG: AND_INT
; R600-DAG: SETNE_INT ; R600-DAG: SETNE_INT
; GCN: v_cmp_lg_f32_e32 vcc ; GCN: v_cmp_lg_f32_e32 vcc
; GCN-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc ; GCN-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
define amdgpu_kernel void @f32_one(i32 addrspace(1)* %out, float %a, float %b) #0 { define amdgpu_kernel void @f32_one(i32 addrspace(1)* %out, float %a, float %b) #0 {
entry: entry:
%0 = fcmp one float %a, %b %0 = fcmp one float %a, %b
%1 = sext i1 %0 to i32 %1 = sext i1 %0 to i32
Show All 11 Lines
entry: entry:
%0 = fcmp ord float %a, %b %0 = fcmp ord float %a, %b
%1 = sext i1 %0 to i32 %1 = sext i1 %0 to i32
store i32 %1, i32 addrspace(1)* %out store i32 %1, i32 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}f32_ueq: ; FUNC-LABEL: {{^}}f32_ueq:
; R600-DAG: SETNE_DX10 ; R600-DAG: SETGT_DX10
; R600-DAG: SETNE_DX10 ; R600-DAG: SETGT_DX10
; R600-DAG: OR_INT
; R600-DAG: SETE_DX10
; R600-DAG: OR_INT ; R600-DAG: OR_INT
; R600-DAG: SETNE_INT ; R600-DAG: SETE_INT
; GCN: v_cmp_nlg_f32_e32 vcc ; GCN: v_cmp_nlg_f32_e32 vcc
; GCN-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc ; GCN-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
define amdgpu_kernel void @f32_ueq(i32 addrspace(1)* %out, float %a, float %b) #0 { define amdgpu_kernel void @f32_ueq(i32 addrspace(1)* %out, float %a, float %b) #0 {
entry: entry:
%0 = fcmp ueq float %a, %b %0 = fcmp ueq float %a, %b
%1 = sext i1 %0 to i32 %1 = sext i1 %0 to i32
store i32 %1, i32 addrspace(1)* %out store i32 %1, i32 addrspace(1)* %out
▲ Show 20 Lines • Show All 327 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/spe.ll

Show First 20 Lines • Show All 291 Lines • ▼ Show 20 Lines; CHECK-NEXT: blr
entry: entry:
%r = fcmp ord float %a, %b %r = fcmp ord float %a, %b
ret i1 %r ret i1 %r
} }
define i1 @test_fcmpueq(float %a, float %b) #0 { define i1 @test_fcmpueq(float %a, float %b) #0 {
; CHECK-LABEL: test_fcmpueq: ; CHECK-LABEL: test_fcmpueq:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: efscmpeq 0, 3, 3 ; CHECK-NEXT: efscmpgt 0, 3, 4
; CHECK-NEXT: efscmpeq 1, 4, 4 ; CHECK-NEXT: efscmplt 1, 3, 4
; CHECK-NEXT: crnand 20, 5, 1
; CHECK-NEXT: efscmpeq 0, 3, 4
; CHECK-NEXT: li 5, 1 ; CHECK-NEXT: li 5, 1
; CHECK-NEXT: crnor 20, 1, 20 ; CHECK-NEXT: cror 20, 5, 1
; CHECK-NEXT: bc 12, 20, .LBB14_2 ; CHECK-NEXT: bc 12, 20, .LBB14_2
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: ori 3, 5, 0 ; CHECK-NEXT: ori 3, 5, 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-NEXT: .LBB14_2: # %entry ; CHECK-NEXT: .LBB14_2: # %entry
; CHECK-NEXT: li 3, 0 ; CHECK-NEXT: li 3, 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%r = fcmp ueq float %a, %b %r = fcmp ueq float %a, %b
ret i1 %r ret i1 %r
} }
define i1 @test_fcmpne(float %a, float %b) #0 { define i1 @test_fcmpne(float %a, float %b) #0 {
; CHECK-LABEL: test_fcmpne: ; CHECK-LABEL: test_fcmpne:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: efscmpeq 0, 4, 4 ; CHECK-NEXT: efscmplt 0, 3, 4
; CHECK-NEXT: efscmpeq 1, 3, 3 ; CHECK-NEXT: efscmpgt 1, 3, 4
; CHECK-NEXT: crand 20, 5, 1
; CHECK-NEXT: efscmpeq 0, 3, 4
; CHECK-NEXT: li 5, 1 ; CHECK-NEXT: li 5, 1
; CHECK-NEXT: crorc 20, 1, 20 ; CHECK-NEXT: crnor 20, 5, 1
; CHECK-NEXT: bc 12, 20, .LBB15_2 ; CHECK-NEXT: bc 12, 20, .LBB15_2
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: ori 3, 5, 0 ; CHECK-NEXT: ori 3, 5, 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-NEXT: .LBB15_2: # %entry ; CHECK-NEXT: .LBB15_2: # %entry
; CHECK-NEXT: li 3, 0 ; CHECK-NEXT: li 3, 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
▲ Show 20 Lines • Show All 777 Lines • ▼ Show 20 Linesret:
%0 = load i32, i32* %r, align 4 %0 = load i32, i32* %r, align 4
ret i32 %0 ret i32 %0
} }
define i32 @test_dcmpueq(double %a, double %b) #0 { define i32 @test_dcmpueq(double %a, double %b) #0 {
; SPE-LABEL: test_dcmpueq: ; SPE-LABEL: test_dcmpueq:
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: stwu 1, -16(1) ; SPE-NEXT: stwu 1, -16(1)
; SPE-NEXT: evmergelo 5, 5, 6
; SPE-NEXT: evmergelo 3, 3, 4 ; SPE-NEXT: evmergelo 3, 3, 4
; SPE-NEXT: evmergelo 4, 5, 6 ; SPE-NEXT: efdcmplt 0, 3, 5
; SPE-NEXT: efdcmpeq 0, 4, 4 ; SPE-NEXT: bc 12, 1, .LBB16_3
; SPE-NEXT: bc 4, 1, .LBB16_4
; SPE-NEXT: # %bb.1: # %entry ; SPE-NEXT: # %bb.1: # %entry
; SPE-NEXT: efdcmpeq 0, 3, 3 ; SPE-NEXT: efdcmpgt 0, 3, 5
; SPE-NEXT: bc 4, 1, .LBB16_4 ; SPE-NEXT: bc 12, 1, .LBB16_3
; SPE-NEXT: # %bb.2: # %entry ; SPE-NEXT: # %bb.2: # %tr
; SPE-NEXT: efdcmpeq 0, 3, 4
; SPE-NEXT: bc 12, 1, .LBB16_4
; SPE-NEXT: # %bb.3: # %fa
; SPE-NEXT: li 3, 0
; SPE-NEXT: b .LBB16_5
; SPE-NEXT: .LBB16_4: # %tr
; SPE-NEXT: li 3, 1 ; SPE-NEXT: li 3, 1
; SPE-NEXT: .LBB16_5: # %ret ; SPE-NEXT: b .LBB16_4
; SPE-NEXT: .LBB16_3: # %fa
; SPE-NEXT: li 3, 0
; SPE-NEXT: .LBB16_4: # %ret
; SPE-NEXT: stw 3, 12(1) ; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1) ; SPE-NEXT: lwz 3, 12(1)
; SPE-NEXT: addi 1, 1, 16 ; SPE-NEXT: addi 1, 1, 16
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
; EFPU2-LABEL: test_dcmpueq: ; EFPU2-LABEL: test_dcmpueq:
; EFPU2: # %bb.0: # %entry ; EFPU2: # %bb.0: # %entry
; EFPU2-NEXT: mflr 0 ; EFPU2-NEXT: mflr 0
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
ret: ret:
%0 = load i32, i32* %r, align 4 %0 = load i32, i32* %r, align 4
ret i32 %0 ret i32 %0
} }
define i1 @test_dcmpne(double %a, double %b) #0 { define i1 @test_dcmpne(double %a, double %b) #0 {
; SPE-LABEL: test_dcmpne: ; SPE-LABEL: test_dcmpne:
; SPE: # %bb.0: # %entry ; SPE: # %bb.0: # %entry
; SPE-NEXT: evmergelo 5, 5, 6
; SPE-NEXT: evmergelo 3, 3, 4 ; SPE-NEXT: evmergelo 3, 3, 4
; SPE-NEXT: evmergelo 4, 5, 6
; SPE-NEXT: li 7, 1 ; SPE-NEXT: li 7, 1
; SPE-NEXT: efdcmpeq 0, 4, 4 ; SPE-NEXT: efdcmplt 0, 3, 5
; SPE-NEXT: efdcmpeq 1, 3, 3 ; SPE-NEXT: efdcmpgt 1, 3, 5
; SPE-NEXT: efdcmpeq 5, 3, 4 ; SPE-NEXT: crnor 20, 5, 1
; SPE-NEXT: crand 24, 5, 1
; SPE-NEXT: crorc 20, 21, 24
; SPE-NEXT: bc 12, 20, .LBB17_2 ; SPE-NEXT: bc 12, 20, .LBB17_2
; SPE-NEXT: # %bb.1: # %entry ; SPE-NEXT: # %bb.1: # %entry
; SPE-NEXT: ori 3, 7, 0 ; SPE-NEXT: ori 3, 7, 0
; SPE-NEXT: blr ; SPE-NEXT: blr
; SPE-NEXT: .LBB17_2: # %entry ; SPE-NEXT: .LBB17_2: # %entry
; SPE-NEXT: li 3, 0 ; SPE-NEXT: li 3, 0
; SPE-NEXT: blr ; SPE-NEXT: blr
; ;
▲ Show 20 Lines • Show All 868 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/vsx.ll

Show First 20 Lines • Show All 618 Lines • ▼ Show 20 Lines
} }
define <4 x float> @test22(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) { define <4 x float> @test22(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) {
; CHECK-LABEL: test22: ; CHECK-LABEL: test22:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xvcmpeqsp vs0, v5, v5 ; CHECK-NEXT: xvcmpgtsp vs0, v5, v4
; CHECK-NEXT: xvcmpeqsp vs1, v4, v4 ; CHECK-NEXT: xvcmpgtsp vs1, v4, v5
; CHECK-NEXT: xvcmpeqsp vs2, v4, v5 ; CHECK-NEXT: xxlnor vs0, vs1, vs0
; CHECK-NEXT: xxlnor vs0, vs0, vs0
; CHECK-NEXT: xxlnor vs1, vs1, vs1
; CHECK-NEXT: xxlor vs0, vs1, vs0
; CHECK-NEXT: xxlor vs0, vs2, vs0
; CHECK-NEXT: xxsel v2, v3, v2, vs0 ; CHECK-NEXT: xxsel v2, v3, v2, vs0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-REG-LABEL: test22: ; CHECK-REG-LABEL: test22:
; CHECK-REG: # %bb.0: # %entry ; CHECK-REG: # %bb.0: # %entry
; CHECK-REG-NEXT: xvcmpeqsp vs0, v5, v5 ; CHECK-REG-NEXT: xvcmpgtsp vs0, v5, v4
; CHECK-REG-NEXT: xvcmpeqsp vs1, v4, v4 ; CHECK-REG-NEXT: xvcmpgtsp vs1, v4, v5
; CHECK-REG-NEXT: xvcmpeqsp vs2, v4, v5 ; CHECK-REG-NEXT: xxlnor vs0, vs1, vs0
; CHECK-REG-NEXT: xxlnor vs0, vs0, vs0
; CHECK-REG-NEXT: xxlnor vs1, vs1, vs1
; CHECK-REG-NEXT: xxlor vs0, vs1, vs0
; CHECK-REG-NEXT: xxlor vs0, vs2, vs0
; CHECK-REG-NEXT: xxsel v2, v3, v2, vs0 ; CHECK-REG-NEXT: xxsel v2, v3, v2, vs0
; CHECK-REG-NEXT: blr ; CHECK-REG-NEXT: blr
; ;
; CHECK-FISL-LABEL: test22: ; CHECK-FISL-LABEL: test22:
; CHECK-FISL: # %bb.0: # %entry ; CHECK-FISL: # %bb.0: # %entry
; CHECK-FISL-NEXT: xvcmpeqsp vs0, v4, v5 ; CHECK-FISL-NEXT: xvcmpgtsp vs1, v5, v4
; CHECK-FISL-NEXT: xvcmpeqsp vs1, v5, v5 ; CHECK-FISL-NEXT: xvcmpgtsp vs0, v4, v5
; CHECK-FISL-NEXT: xxlnor vs2, vs1, vs1 ; CHECK-FISL-NEXT: xxlnor vs0, vs0, vs1
; CHECK-FISL-NEXT: xvcmpeqsp vs1, v4, v4
; CHECK-FISL-NEXT: xxlnor vs1, vs1, vs1
; CHECK-FISL-NEXT: xxlor vs1, vs1, vs2
; CHECK-FISL-NEXT: xxlor vs0, vs0, vs1
; CHECK-FISL-NEXT: xxsel v2, v3, v2, vs0 ; CHECK-FISL-NEXT: xxsel v2, v3, v2, vs0
; CHECK-FISL-NEXT: blr ; CHECK-FISL-NEXT: blr
; ;
; CHECK-LE-LABEL: test22: ; CHECK-LE-LABEL: test22:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: xvcmpeqsp vs0, v5, v5 ; CHECK-LE-NEXT: xvcmpgtsp vs0, v5, v4
; CHECK-LE-NEXT: xvcmpeqsp vs1, v4, v4 ; CHECK-LE-NEXT: xvcmpgtsp vs1, v4, v5
; CHECK-LE-NEXT: xvcmpeqsp vs2, v4, v5 ; CHECK-LE-NEXT: xxlnor vs0, vs1, vs0
; CHECK-LE-NEXT: xxlnor vs0, vs0, vs0
; CHECK-LE-NEXT: xxlnor vs1, vs1, vs1
; CHECK-LE-NEXT: xxlor vs0, vs1, vs0
; CHECK-LE-NEXT: xxlor vs0, vs2, vs0
; CHECK-LE-NEXT: xxsel v2, v3, v2, vs0 ; CHECK-LE-NEXT: xxsel v2, v3, v2, vs0
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%m = fcmp ueq <4 x float> %c, %d %m = fcmp ueq <4 x float> %c, %d
%v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b
ret <4 x float> %v ret <4 x float> %v
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llvm/test/CodeGen/RISCV/double-br-fcmp.ll

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%1 = fcmp ole double %a, %b %1 = fcmp ole double %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
; TODO: feq.s+sltiu+bne -> feq.s+beq
define void @br_fcmp_one(double %a, double %b) nounwind { define void @br_fcmp_one(double %a, double %b) nounwind {
lenaryUnsubmitted
Not Done
ReplyInline Actions

Please can you remove this TODO, as it is no longer relevant?

lenary: Please can you remove this TODO, as it is no longer relevant?
; RV32IFD-LABEL: br_fcmp_one: ; RV32IFD-LABEL: br_fcmp_one:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: sw a2, 0(sp) ; RV32IFD-NEXT: sw a2, 0(sp)
; RV32IFD-NEXT: sw a3, 4(sp) ; RV32IFD-NEXT: sw a3, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft1, 0(sp) ; RV32IFD-NEXT: fld ft1, 0(sp)
; RV32IFD-NEXT: feq.d a0, ft1, ft1 ; RV32IFD-NEXT: flt.d a0, ft1, ft0
; RV32IFD-NEXT: feq.d a1, ft0, ft0 ; RV32IFD-NEXT: flt.d a1, ft0, ft1
; RV32IFD-NEXT: and a0, a1, a0 ; RV32IFD-NEXT: or a0, a1, a0
; RV32IFD-NEXT: feq.d a1, ft0, ft1
; RV32IFD-NEXT: not a1, a1
; RV32IFD-NEXT: and a0, a1, a0
; RV32IFD-NEXT: bnez a0, .LBB7_2 ; RV32IFD-NEXT: bnez a0, .LBB7_2
; RV32IFD-NEXT: # %bb.1: # %if.else ; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB7_2: # %if.then ; RV32IFD-NEXT: .LBB7_2: # %if.then
; RV32IFD-NEXT: call abort@plt ; RV32IFD-NEXT: call abort@plt
; ;
; RV64IFD-LABEL: br_fcmp_one: ; RV64IFD-LABEL: br_fcmp_one:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a1 ; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: feq.d a0, ft1, ft1 ; RV64IFD-NEXT: flt.d a0, ft1, ft0
; RV64IFD-NEXT: feq.d a1, ft0, ft0 ; RV64IFD-NEXT: flt.d a1, ft0, ft1
; RV64IFD-NEXT: and a0, a1, a0 ; RV64IFD-NEXT: or a0, a1, a0
; RV64IFD-NEXT: feq.d a1, ft0, ft1
; RV64IFD-NEXT: not a1, a1
; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: bnez a0, .LBB7_2 ; RV64IFD-NEXT: bnez a0, .LBB7_2
; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB7_2: # %if.then ; RV64IFD-NEXT: .LBB7_2: # %if.then
; RV64IFD-NEXT: call abort@plt ; RV64IFD-NEXT: call abort@plt
%1 = fcmp one double %a, %b %1 = fcmp one double %a, %b
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; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a2, 0(sp) ; RV32IFD-NEXT: sw a2, 0(sp)
; RV32IFD-NEXT: sw a3, 4(sp) ; RV32IFD-NEXT: sw a3, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp) ; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft1, 0(sp) ; RV32IFD-NEXT: fld ft1, 0(sp)
; RV32IFD-NEXT: feq.d a0, ft1, ft0 ; RV32IFD-NEXT: flt.d a0, ft1, ft0
; RV32IFD-NEXT: feq.d a1, ft0, ft0 ; RV32IFD-NEXT: flt.d a1, ft0, ft1
; RV32IFD-NEXT: feq.d a2, ft1, ft1 ; RV32IFD-NEXT: or a0, a1, a0
; RV32IFD-NEXT: and a1, a2, a1 ; RV32IFD-NEXT: addi a1, zero, 1
; RV32IFD-NEXT: xori a1, a1, 1 ; RV32IFD-NEXT: bne a0, a1, .LBB9_2
; RV32IFD-NEXT: or a0, a0, a1
; RV32IFD-NEXT: bnez a0, .LBB9_2
; RV32IFD-NEXT: # %bb.1: # %if.else ; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB9_2: # %if.then ; RV32IFD-NEXT: .LBB9_2: # %if.then
; RV32IFD-NEXT: call abort@plt ; RV32IFD-NEXT: call abort@plt
; ;
; RV64IFD-LABEL: br_fcmp_ueq: ; RV64IFD-LABEL: br_fcmp_ueq:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d.x ft0, a1 ; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0 ; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: feq.d a0, ft1, ft0 ; RV64IFD-NEXT: flt.d a0, ft1, ft0
; RV64IFD-NEXT: feq.d a1, ft0, ft0 ; RV64IFD-NEXT: flt.d a1, ft0, ft1
; RV64IFD-NEXT: feq.d a2, ft1, ft1 ; RV64IFD-NEXT: or a0, a1, a0
; RV64IFD-NEXT: and a1, a2, a1 ; RV64IFD-NEXT: addi a1, zero, 1
; RV64IFD-NEXT: xori a1, a1, 1 ; RV64IFD-NEXT: bne a0, a1, .LBB9_2
; RV64IFD-NEXT: or a0, a0, a1
; RV64IFD-NEXT: bnez a0, .LBB9_2
; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB9_2: # %if.then ; RV64IFD-NEXT: .LBB9_2: # %if.then
; RV64IFD-NEXT: call abort@plt ; RV64IFD-NEXT: call abort@plt
%1 = fcmp ueq double %a, %b %1 = fcmp ueq double %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
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llvm/test/CodeGen/RISCV/double-fcmp.ll

Show First 20 Lines • Show All 142 Lines • ▼ Show 20 Lines; RV64IFD-NEXT: ret
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_one(double %a, double %b) nounwind { define i32 @fcmp_one(double %a, double %b) nounwind {
; RV32IFD-LABEL: fcmp_one: ; RV32IFD-LABEL: fcmp_one:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: sw a2, 8(sp) ; RV32IFD-NEXT: sw a2, 8(sp)
; RV32IFD-NEXT: sw a3, 12(sp) ; RV32IFD-NEXT: sw a3, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp) ; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: feq.d a0, ft1, ft1 ; RV32IFD-NEXT: flt.d a0, ft1, ft0
; RV32IFD-NEXT: feq.d a1, ft0, ft0 ; RV32IFD-NEXT: flt.d a1, ft0, ft1
; RV32IFD-NEXT: and a0, a1, a0 ; RV32IFD-NEXT: or a0, a1, a0
; RV32IFD-NEXT: feq.d a1, ft0, ft1
; RV32IFD-NEXT: not a1, a1
; RV32IFD-NEXT: and a0, a1, a0
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fcmp_one: ; RV64IFD-LABEL: fcmp_one:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a1 ; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: feq.d a0, ft1, ft1 ; RV64IFD-NEXT: flt.d a0, ft1, ft0
; RV64IFD-NEXT: feq.d a1, ft0, ft0 ; RV64IFD-NEXT: flt.d a1, ft0, ft1
; RV64IFD-NEXT: and a0, a1, a0 ; RV64IFD-NEXT: or a0, a1, a0
; RV64IFD-NEXT: feq.d a1, ft0, ft1
; RV64IFD-NEXT: not a1, a1
; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = fcmp one double %a, %b %1 = fcmp one double %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_ord(double %a, double %b) nounwind { define i32 @fcmp_ord(double %a, double %b) nounwind {
; RV32IFD-LABEL: fcmp_ord: ; RV32IFD-LABEL: fcmp_ord:
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; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw a2, 8(sp) ; RV32IFD-NEXT: sw a2, 8(sp)
; RV32IFD-NEXT: sw a3, 12(sp) ; RV32IFD-NEXT: sw a3, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp) ; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: sw a0, 8(sp) ; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp) ; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp) ; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: feq.d a0, ft1, ft0 ; RV32IFD-NEXT: flt.d a0, ft1, ft0
; RV32IFD-NEXT: feq.d a1, ft0, ft0 ; RV32IFD-NEXT: flt.d a1, ft0, ft1
; RV32IFD-NEXT: feq.d a2, ft1, ft1 ; RV32IFD-NEXT: or a0, a1, a0
; RV32IFD-NEXT: and a1, a2, a1 ; RV32IFD-NEXT: xori a0, a0, 1
; RV32IFD-NEXT: xori a1, a1, 1
; RV32IFD-NEXT: or a0, a0, a1
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: fcmp_ueq: ; RV64IFD-LABEL: fcmp_ueq:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a1 ; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0 ; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: feq.d a0, ft1, ft0 ; RV64IFD-NEXT: flt.d a0, ft1, ft0
; RV64IFD-NEXT: feq.d a1, ft0, ft0 ; RV64IFD-NEXT: flt.d a1, ft0, ft1
; RV64IFD-NEXT: feq.d a2, ft1, ft1 ; RV64IFD-NEXT: or a0, a1, a0
; RV64IFD-NEXT: and a1, a2, a1 ; RV64IFD-NEXT: xori a0, a0, 1
; RV64IFD-NEXT: xori a1, a1, 1
; RV64IFD-NEXT: or a0, a0, a1
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = fcmp ueq double %a, %b %1 = fcmp ueq double %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_ugt(double %a, double %b) nounwind { define i32 @fcmp_ugt(double %a, double %b) nounwind {
; RV32IFD-LABEL: fcmp_ugt: ; RV32IFD-LABEL: fcmp_ugt:
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llvm/test/CodeGen/RISCV/double-select-fcmp.ll

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; RV64IFD-NEXT: .LBB5_2: ; RV64IFD-NEXT: .LBB5_2:
; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = fcmp ole double %a, %b %1 = fcmp ole double %a, %b
%2 = select i1 %1, double %a, double %b %2 = select i1 %1, double %a, double %b
ret double %2 ret double %2
} }
define double @select_fcmp_one(double %a, double %b) nounwind { define double @select_fcmp_one(double %a, double %b) nounwind {
; TODO: feq.s+sltiu+bne sequence could be optimised
; RV32IFD-LABEL: select_fcmp_one: ; RV32IFD-LABEL: select_fcmp_one:
lenaryUnsubmitted
Not Done
ReplyInline Actions

And here.

lenary: And here.
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: sw a2, 8(sp) ; RV32IFD-NEXT: sw a2, 8(sp)
; RV32IFD-NEXT: sw a3, 12(sp) ; RV32IFD-NEXT: sw a3, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp) ; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: feq.d a0, ft1, ft1 ; RV32IFD-NEXT: flt.d a0, ft1, ft0
; RV32IFD-NEXT: feq.d a1, ft0, ft0 ; RV32IFD-NEXT: flt.d a1, ft0, ft1
; RV32IFD-NEXT: and a0, a1, a0 ; RV32IFD-NEXT: or a0, a1, a0
; RV32IFD-NEXT: feq.d a1, ft0, ft1
; RV32IFD-NEXT: not a1, a1
; RV32IFD-NEXT: and a0, a1, a0
; RV32IFD-NEXT: bnez a0, .LBB6_2 ; RV32IFD-NEXT: bnez a0, .LBB6_2
; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: fmv.d ft0, ft1 ; RV32IFD-NEXT: fmv.d ft1, ft0
; RV32IFD-NEXT: .LBB6_2: ; RV32IFD-NEXT: .LBB6_2:
; RV32IFD-NEXT: fsd ft0, 8(sp) ; RV32IFD-NEXT: fsd ft1, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp) ; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: select_fcmp_one: ; RV64IFD-LABEL: select_fcmp_one:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fmv.d.x ft1, a1 ; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: feq.d a0, ft1, ft1 ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: feq.d a1, ft0, ft0 ; RV64IFD-NEXT: flt.d a0, ft0, ft1
; RV64IFD-NEXT: and a0, a1, a0 ; RV64IFD-NEXT: flt.d a1, ft1, ft0
; RV64IFD-NEXT: feq.d a1, ft0, ft1 ; RV64IFD-NEXT: or a0, a1, a0
; RV64IFD-NEXT: not a1, a1
; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: bnez a0, .LBB6_2 ; RV64IFD-NEXT: bnez a0, .LBB6_2
; RV64IFD-NEXT: # %bb.1: ; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fmv.d ft0, ft1 ; RV64IFD-NEXT: fmv.d ft0, ft1
; RV64IFD-NEXT: .LBB6_2: ; RV64IFD-NEXT: .LBB6_2:
; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = fcmp one double %a, %b %1 = fcmp one double %a, %b
%2 = select i1 %1, double %a, double %b %2 = select i1 %1, double %a, double %b
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; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw a2, 8(sp) ; RV32IFD-NEXT: sw a2, 8(sp)
; RV32IFD-NEXT: sw a3, 12(sp) ; RV32IFD-NEXT: sw a3, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp) ; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: sw a0, 8(sp) ; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp) ; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp) ; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: feq.d a0, ft1, ft0 ; RV32IFD-NEXT: flt.d a0, ft1, ft0
; RV32IFD-NEXT: feq.d a1, ft0, ft0 ; RV32IFD-NEXT: flt.d a1, ft0, ft1
; RV32IFD-NEXT: feq.d a2, ft1, ft1 ; RV32IFD-NEXT: or a0, a1, a0
; RV32IFD-NEXT: and a1, a2, a1 ; RV32IFD-NEXT: xori a0, a0, 1
; RV32IFD-NEXT: xori a1, a1, 1
; RV32IFD-NEXT: or a0, a0, a1
; RV32IFD-NEXT: bnez a0, .LBB8_2 ; RV32IFD-NEXT: bnez a0, .LBB8_2
; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: fmv.d ft1, ft0 ; RV32IFD-NEXT: fmv.d ft1, ft0
; RV32IFD-NEXT: .LBB8_2: ; RV32IFD-NEXT: .LBB8_2:
; RV32IFD-NEXT: fsd ft1, 8(sp) ; RV32IFD-NEXT: fsd ft1, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp) ; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp) ; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: select_fcmp_ueq: ; RV64IFD-LABEL: select_fcmp_ueq:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft1, a1 ; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: feq.d a0, ft0, ft1 ; RV64IFD-NEXT: flt.d a0, ft0, ft1
; RV64IFD-NEXT: feq.d a1, ft1, ft1 ; RV64IFD-NEXT: flt.d a1, ft1, ft0
; RV64IFD-NEXT: feq.d a2, ft0, ft0 ; RV64IFD-NEXT: or a0, a1, a0
; RV64IFD-NEXT: and a1, a2, a1 ; RV64IFD-NEXT: xori a0, a0, 1
; RV64IFD-NEXT: xori a1, a1, 1
; RV64IFD-NEXT: or a0, a0, a1
; RV64IFD-NEXT: bnez a0, .LBB8_2 ; RV64IFD-NEXT: bnez a0, .LBB8_2
; RV64IFD-NEXT: # %bb.1: ; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fmv.d ft0, ft1 ; RV64IFD-NEXT: fmv.d ft0, ft1
; RV64IFD-NEXT: .LBB8_2: ; RV64IFD-NEXT: .LBB8_2:
; RV64IFD-NEXT: fmv.x.d a0, ft0 ; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
%1 = fcmp ueq double %a, %b %1 = fcmp ueq double %a, %b
%2 = select i1 %1, double %a, double %b %2 = select i1 %1, double %a, double %b
▲ Show 20 Lines • Show All 290 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/float-br-fcmp.ll

Show First 20 Lines • Show All 275 Lines • ▼ Show 20 Lines; RV64IF-NEXT: call abort@plt
%1 = fcmp ole float %a, %b %1 = fcmp ole float %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
; TODO: feq.s+sltiu+bne -> feq.s+beq
define void @br_fcmp_one(float %a, float %b) nounwind { define void @br_fcmp_one(float %a, float %b) nounwind {
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and here

lenary: and here
; RV32IF-LABEL: br_fcmp_one: ; RV32IF-LABEL: br_fcmp_one:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: fmv.w.x ft1, a1 ; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: feq.s a0, ft1, ft1 ; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: feq.s a1, ft0, ft0 ; RV32IF-NEXT: flt.s a1, ft0, ft1
; RV32IF-NEXT: and a0, a1, a0 ; RV32IF-NEXT: or a0, a1, a0
; RV32IF-NEXT: feq.s a1, ft0, ft1
; RV32IF-NEXT: not a1, a1
; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: bnez a0, .LBB7_2 ; RV32IF-NEXT: bnez a0, .LBB7_2
; RV32IF-NEXT: # %bb.1: # %if.else ; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB7_2: # %if.then ; RV32IF-NEXT: .LBB7_2: # %if.then
; RV32IF-NEXT: call abort@plt ; RV32IF-NEXT: call abort@plt
; ;
; RV64IF-LABEL: br_fcmp_one: ; RV64IF-LABEL: br_fcmp_one:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: fmv.w.x ft1, a1 ; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: feq.s a0, ft1, ft1 ; RV64IF-NEXT: flt.s a0, ft1, ft0
; RV64IF-NEXT: feq.s a1, ft0, ft0 ; RV64IF-NEXT: flt.s a1, ft0, ft1
; RV64IF-NEXT: and a0, a1, a0 ; RV64IF-NEXT: or a0, a1, a0
; RV64IF-NEXT: feq.s a1, ft0, ft1
; RV64IF-NEXT: not a1, a1
; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: bnez a0, .LBB7_2 ; RV64IF-NEXT: bnez a0, .LBB7_2
; RV64IF-NEXT: # %bb.1: # %if.else ; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB7_2: # %if.then ; RV64IF-NEXT: .LBB7_2: # %if.then
; RV64IF-NEXT: call abort@plt ; RV64IF-NEXT: call abort@plt
%1 = fcmp one float %a, %b %1 = fcmp one float %a, %b
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
define void @br_fcmp_ueq(float %a, float %b) nounwind { define void @br_fcmp_ueq(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_ueq: ; RV32IF-LABEL: br_fcmp_ueq:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.w.x ft0, a1 ; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: fmv.w.x ft1, a0 ; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: feq.s a0, ft1, ft0 ; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: feq.s a1, ft0, ft0 ; RV32IF-NEXT: flt.s a1, ft0, ft1
; RV32IF-NEXT: feq.s a2, ft1, ft1 ; RV32IF-NEXT: or a0, a1, a0
; RV32IF-NEXT: and a1, a2, a1 ; RV32IF-NEXT: addi a1, zero, 1
; RV32IF-NEXT: xori a1, a1, 1 ; RV32IF-NEXT: bne a0, a1, .LBB9_2
; RV32IF-NEXT: or a0, a0, a1
; RV32IF-NEXT: bnez a0, .LBB9_2
; RV32IF-NEXT: # %bb.1: # %if.else ; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB9_2: # %if.then ; RV32IF-NEXT: .LBB9_2: # %if.then
; RV32IF-NEXT: call abort@plt ; RV32IF-NEXT: call abort@plt
; ;
; RV64IF-LABEL: br_fcmp_ueq: ; RV64IF-LABEL: br_fcmp_ueq:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: fmv.w.x ft0, a1 ; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: fmv.w.x ft1, a0 ; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: feq.s a0, ft1, ft0 ; RV64IF-NEXT: flt.s a0, ft1, ft0
; RV64IF-NEXT: feq.s a1, ft0, ft0 ; RV64IF-NEXT: flt.s a1, ft0, ft1
; RV64IF-NEXT: feq.s a2, ft1, ft1 ; RV64IF-NEXT: or a0, a1, a0
; RV64IF-NEXT: and a1, a2, a1 ; RV64IF-NEXT: addi a1, zero, 1
; RV64IF-NEXT: xori a1, a1, 1 ; RV64IF-NEXT: bne a0, a1, .LBB9_2
; RV64IF-NEXT: or a0, a0, a1
; RV64IF-NEXT: bnez a0, .LBB9_2
; RV64IF-NEXT: # %bb.1: # %if.else ; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB9_2: # %if.then ; RV64IF-NEXT: .LBB9_2: # %if.then
; RV64IF-NEXT: call abort@plt ; RV64IF-NEXT: call abort@plt
%1 = fcmp ueq float %a, %b %1 = fcmp ueq float %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
▲ Show 20 Lines • Show All 373 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/float-fcmp.ll

Show First 20 Lines • Show All 111 Lines • ▼ Show 20 Lines; RV64IF-NEXT: ret
%1 = fcmp ole float %a, %b %1 = fcmp ole float %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_one(float %a, float %b) nounwind { define i32 @fcmp_one(float %a, float %b) nounwind {
; RV32IF-LABEL: fcmp_one: ; RV32IF-LABEL: fcmp_one:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: fmv.w.x ft1, a1 ; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: feq.s a0, ft1, ft1 ; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: feq.s a1, ft0, ft0 ; RV32IF-NEXT: flt.s a1, ft0, ft1
; RV32IF-NEXT: and a0, a1, a0 ; RV32IF-NEXT: or a0, a1, a0
; RV32IF-NEXT: feq.s a1, ft0, ft1
; RV32IF-NEXT: not a1, a1
; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fcmp_one: ; RV64IF-LABEL: fcmp_one:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: fmv.w.x ft1, a1 ; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: feq.s a0, ft1, ft1 ; RV64IF-NEXT: flt.s a0, ft1, ft0
; RV64IF-NEXT: feq.s a1, ft0, ft0 ; RV64IF-NEXT: flt.s a1, ft0, ft1
; RV64IF-NEXT: and a0, a1, a0 ; RV64IF-NEXT: or a0, a1, a0
; RV64IF-NEXT: feq.s a1, ft0, ft1
; RV64IF-NEXT: not a1, a1
; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fcmp one float %a, %b %1 = fcmp one float %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_ord(float %a, float %b) nounwind { define i32 @fcmp_ord(float %a, float %b) nounwind {
; RV32IF-LABEL: fcmp_ord: ; RV32IF-LABEL: fcmp_ord:
Show All 18 Lines; RV64IF-NEXT: ret
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_ueq(float %a, float %b) nounwind { define i32 @fcmp_ueq(float %a, float %b) nounwind {
; RV32IF-LABEL: fcmp_ueq: ; RV32IF-LABEL: fcmp_ueq:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a1 ; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: fmv.w.x ft1, a0 ; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: feq.s a0, ft1, ft0 ; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: feq.s a1, ft0, ft0 ; RV32IF-NEXT: flt.s a1, ft0, ft1
; RV32IF-NEXT: feq.s a2, ft1, ft1 ; RV32IF-NEXT: or a0, a1, a0
; RV32IF-NEXT: and a1, a2, a1 ; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: xori a1, a1, 1
; RV32IF-NEXT: or a0, a0, a1
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: fcmp_ueq: ; RV64IF-LABEL: fcmp_ueq:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a1 ; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: fmv.w.x ft1, a0 ; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: feq.s a0, ft1, ft0 ; RV64IF-NEXT: flt.s a0, ft1, ft0
; RV64IF-NEXT: feq.s a1, ft0, ft0 ; RV64IF-NEXT: flt.s a1, ft0, ft1
; RV64IF-NEXT: feq.s a2, ft1, ft1 ; RV64IF-NEXT: or a0, a1, a0
; RV64IF-NEXT: and a1, a2, a1 ; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: xori a1, a1, 1
; RV64IF-NEXT: or a0, a0, a1
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fcmp ueq float %a, %b %1 = fcmp ueq float %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_ugt(float %a, float %b) nounwind { define i32 @fcmp_ugt(float %a, float %b) nounwind {
; RV32IF-LABEL: fcmp_ugt: ; RV32IF-LABEL: fcmp_ugt:
▲ Show 20 Lines • Show All 142 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/float-select-fcmp.ll

Show First 20 Lines • Show All 158 Lines • ▼ Show 20 Lines
; RV64IF-NEXT: .LBB5_2: ; RV64IF-NEXT: .LBB5_2:
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fcmp ole float %a, %b %1 = fcmp ole float %a, %b
%2 = select i1 %1, float %a, float %b %2 = select i1 %1, float %a, float %b
ret float %2 ret float %2
} }
define float @select_fcmp_one(float %a, float %b) nounwind { define float @select_fcmp_one(float %a, float %b) nounwind {
; TODO: feq.s+sltiu+bne sequence could be optimised
; RV32IF-LABEL: select_fcmp_one: ; RV32IF-LABEL: select_fcmp_one:
lenaryUnsubmitted
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And this one

lenary: And this one
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fmv.w.x ft1, a1 ; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: feq.s a0, ft1, ft1 ; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: feq.s a1, ft0, ft0 ; RV32IF-NEXT: flt.s a0, ft0, ft1
; RV32IF-NEXT: and a0, a1, a0 ; RV32IF-NEXT: flt.s a1, ft1, ft0
; RV32IF-NEXT: feq.s a1, ft0, ft1 ; RV32IF-NEXT: or a0, a1, a0
; RV32IF-NEXT: not a1, a1
; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: bnez a0, .LBB6_2 ; RV32IF-NEXT: bnez a0, .LBB6_2
; RV32IF-NEXT: # %bb.1: ; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fmv.s ft0, ft1 ; RV32IF-NEXT: fmv.s ft0, ft1
; RV32IF-NEXT: .LBB6_2: ; RV32IF-NEXT: .LBB6_2:
; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: select_fcmp_one: ; RV64IF-LABEL: select_fcmp_one:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fmv.w.x ft1, a1 ; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: feq.s a0, ft1, ft1 ; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: feq.s a1, ft0, ft0 ; RV64IF-NEXT: flt.s a0, ft0, ft1
; RV64IF-NEXT: and a0, a1, a0 ; RV64IF-NEXT: flt.s a1, ft1, ft0
; RV64IF-NEXT: feq.s a1, ft0, ft1 ; RV64IF-NEXT: or a0, a1, a0
; RV64IF-NEXT: not a1, a1
; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: bnez a0, .LBB6_2 ; RV64IF-NEXT: bnez a0, .LBB6_2
; RV64IF-NEXT: # %bb.1: ; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fmv.s ft0, ft1 ; RV64IF-NEXT: fmv.s ft0, ft1
; RV64IF-NEXT: .LBB6_2: ; RV64IF-NEXT: .LBB6_2:
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fcmp one float %a, %b %1 = fcmp one float %a, %b
%2 = select i1 %1, float %a, float %b %2 = select i1 %1, float %a, float %b
Show All 33 Lines; RV64IF-NEXT: ret
ret float %2 ret float %2
} }
define float @select_fcmp_ueq(float %a, float %b) nounwind { define float @select_fcmp_ueq(float %a, float %b) nounwind {
; RV32IF-LABEL: select_fcmp_ueq: ; RV32IF-LABEL: select_fcmp_ueq:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft1, a1 ; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: feq.s a0, ft0, ft1 ; RV32IF-NEXT: flt.s a0, ft0, ft1
; RV32IF-NEXT: feq.s a1, ft1, ft1 ; RV32IF-NEXT: flt.s a1, ft1, ft0
; RV32IF-NEXT: feq.s a2, ft0, ft0 ; RV32IF-NEXT: or a0, a1, a0
; RV32IF-NEXT: and a1, a2, a1 ; RV32IF-NEXT: xori a0, a0, 1
; RV32IF-NEXT: xori a1, a1, 1
; RV32IF-NEXT: or a0, a0, a1
; RV32IF-NEXT: bnez a0, .LBB8_2 ; RV32IF-NEXT: bnez a0, .LBB8_2
; RV32IF-NEXT: # %bb.1: ; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fmv.s ft0, ft1 ; RV32IF-NEXT: fmv.s ft0, ft1
; RV32IF-NEXT: .LBB8_2: ; RV32IF-NEXT: .LBB8_2:
; RV32IF-NEXT: fmv.x.w a0, ft0 ; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: select_fcmp_ueq: ; RV64IF-LABEL: select_fcmp_ueq:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft1, a1 ; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: feq.s a0, ft0, ft1 ; RV64IF-NEXT: flt.s a0, ft0, ft1
; RV64IF-NEXT: feq.s a1, ft1, ft1 ; RV64IF-NEXT: flt.s a1, ft1, ft0
; RV64IF-NEXT: feq.s a2, ft0, ft0 ; RV64IF-NEXT: or a0, a1, a0
; RV64IF-NEXT: and a1, a2, a1 ; RV64IF-NEXT: xori a0, a0, 1
; RV64IF-NEXT: xori a1, a1, 1
; RV64IF-NEXT: or a0, a0, a1
; RV64IF-NEXT: bnez a0, .LBB8_2 ; RV64IF-NEXT: bnez a0, .LBB8_2
; RV64IF-NEXT: # %bb.1: ; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fmv.s ft0, ft1 ; RV64IF-NEXT: fmv.s ft0, ft1
; RV64IF-NEXT: .LBB8_2: ; RV64IF-NEXT: .LBB8_2:
; RV64IF-NEXT: fmv.x.w a0, ft0 ; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
%1 = fcmp ueq float %a, %b %1 = fcmp ueq float %a, %b
%2 = select i1 %1, float %a, float %b %2 = select i1 %1, float %a, float %b
▲ Show 20 Lines • Show All 236 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/half-br-fcmp.ll

Show First 20 Lines • Show All 251 Lines • ▼ Show 20 Lines; RV64IZFH-NEXT: call abort@plt
%1 = fcmp ole half %a, %b %1 = fcmp ole half %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
; TODO: feq.h+sltiu+bne -> feq.h+beq
define void @br_fcmp_one(half %a, half %b) nounwind { define void @br_fcmp_one(half %a, half %b) nounwind {
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And here!

lenary: And here!
; RV32IZFH-LABEL: br_fcmp_one: ; RV32IZFH-LABEL: br_fcmp_one:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: feq.h a0, fa1, fa1 ; RV32IZFH-NEXT: flt.h a0, fa0, fa1
; RV32IZFH-NEXT: feq.h a1, fa0, fa0 ; RV32IZFH-NEXT: flt.h a1, fa1, fa0
; RV32IZFH-NEXT: and a0, a1, a0 ; RV32IZFH-NEXT: or a0, a1, a0
; RV32IZFH-NEXT: feq.h a1, fa0, fa1
; RV32IZFH-NEXT: not a1, a1
; RV32IZFH-NEXT: and a0, a1, a0
; RV32IZFH-NEXT: bnez a0, .LBB7_2 ; RV32IZFH-NEXT: bnez a0, .LBB7_2
; RV32IZFH-NEXT: # %bb.1: # %if.else ; RV32IZFH-NEXT: # %bb.1: # %if.else
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; RV32IZFH-NEXT: .LBB7_2: # %if.then ; RV32IZFH-NEXT: .LBB7_2: # %if.then
; RV32IZFH-NEXT: call abort@plt ; RV32IZFH-NEXT: call abort@plt
; ;
; RV64IZFH-LABEL: br_fcmp_one: ; RV64IZFH-LABEL: br_fcmp_one:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: feq.h a0, fa1, fa1 ; RV64IZFH-NEXT: flt.h a0, fa0, fa1
; RV64IZFH-NEXT: feq.h a1, fa0, fa0 ; RV64IZFH-NEXT: flt.h a1, fa1, fa0
; RV64IZFH-NEXT: and a0, a1, a0 ; RV64IZFH-NEXT: or a0, a1, a0
; RV64IZFH-NEXT: feq.h a1, fa0, fa1
; RV64IZFH-NEXT: not a1, a1
; RV64IZFH-NEXT: and a0, a1, a0
; RV64IZFH-NEXT: bnez a0, .LBB7_2 ; RV64IZFH-NEXT: bnez a0, .LBB7_2
; RV64IZFH-NEXT: # %bb.1: # %if.else ; RV64IZFH-NEXT: # %bb.1: # %if.else
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; RV64IZFH-NEXT: .LBB7_2: # %if.then ; RV64IZFH-NEXT: .LBB7_2: # %if.then
; RV64IZFH-NEXT: call abort@plt ; RV64IZFH-NEXT: call abort@plt
%1 = fcmp one half %a, %b %1 = fcmp one half %a, %b
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Linesif.then:
unreachable unreachable
} }
define void @br_fcmp_ueq(half %a, half %b) nounwind { define void @br_fcmp_ueq(half %a, half %b) nounwind {
; RV32IZFH-LABEL: br_fcmp_ueq: ; RV32IZFH-LABEL: br_fcmp_ueq:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: feq.h a0, fa0, fa1 ; RV32IZFH-NEXT: flt.h a0, fa0, fa1
; RV32IZFH-NEXT: feq.h a1, fa1, fa1 ; RV32IZFH-NEXT: flt.h a1, fa1, fa0
; RV32IZFH-NEXT: feq.h a2, fa0, fa0 ; RV32IZFH-NEXT: or a0, a1, a0
; RV32IZFH-NEXT: and a1, a2, a1 ; RV32IZFH-NEXT: addi a1, zero, 1
; RV32IZFH-NEXT: xori a1, a1, 1 ; RV32IZFH-NEXT: bne a0, a1, .LBB9_2
; RV32IZFH-NEXT: or a0, a0, a1
; RV32IZFH-NEXT: bnez a0, .LBB9_2
; RV32IZFH-NEXT: # %bb.1: # %if.else ; RV32IZFH-NEXT: # %bb.1: # %if.else
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; RV32IZFH-NEXT: .LBB9_2: # %if.then ; RV32IZFH-NEXT: .LBB9_2: # %if.then
; RV32IZFH-NEXT: call abort@plt ; RV32IZFH-NEXT: call abort@plt
; ;
; RV64IZFH-LABEL: br_fcmp_ueq: ; RV64IZFH-LABEL: br_fcmp_ueq:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: feq.h a0, fa0, fa1 ; RV64IZFH-NEXT: flt.h a0, fa0, fa1
; RV64IZFH-NEXT: feq.h a1, fa1, fa1 ; RV64IZFH-NEXT: flt.h a1, fa1, fa0
; RV64IZFH-NEXT: feq.h a2, fa0, fa0 ; RV64IZFH-NEXT: or a0, a1, a0
; RV64IZFH-NEXT: and a1, a2, a1 ; RV64IZFH-NEXT: addi a1, zero, 1
; RV64IZFH-NEXT: xori a1, a1, 1 ; RV64IZFH-NEXT: bne a0, a1, .LBB9_2
; RV64IZFH-NEXT: or a0, a0, a1
; RV64IZFH-NEXT: bnez a0, .LBB9_2
; RV64IZFH-NEXT: # %bb.1: # %if.else ; RV64IZFH-NEXT: # %bb.1: # %if.else
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; RV64IZFH-NEXT: .LBB9_2: # %if.then ; RV64IZFH-NEXT: .LBB9_2: # %if.then
; RV64IZFH-NEXT: call abort@plt ; RV64IZFH-NEXT: call abort@plt
%1 = fcmp ueq half %a, %b %1 = fcmp ueq half %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
▲ Show 20 Lines • Show All 268 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/half-fcmp.ll

Show First 20 Lines • Show All 91 Lines • ▼ Show 20 Lines; RV64IZFH-NEXT: ret
%1 = fcmp ole half %a, %b %1 = fcmp ole half %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_one(half %a, half %b) nounwind { define i32 @fcmp_one(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_one: ; RV32IZFH-LABEL: fcmp_one:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: feq.h a0, fa1, fa1 ; RV32IZFH-NEXT: flt.h a0, fa0, fa1
; RV32IZFH-NEXT: feq.h a1, fa0, fa0 ; RV32IZFH-NEXT: flt.h a1, fa1, fa0
; RV32IZFH-NEXT: and a0, a1, a0 ; RV32IZFH-NEXT: or a0, a1, a0
; RV32IZFH-NEXT: feq.h a1, fa0, fa1
; RV32IZFH-NEXT: not a1, a1
; RV32IZFH-NEXT: and a0, a1, a0
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fcmp_one: ; RV64IZFH-LABEL: fcmp_one:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa1, fa1 ; RV64IZFH-NEXT: flt.h a0, fa0, fa1
; RV64IZFH-NEXT: feq.h a1, fa0, fa0 ; RV64IZFH-NEXT: flt.h a1, fa1, fa0
; RV64IZFH-NEXT: and a0, a1, a0 ; RV64IZFH-NEXT: or a0, a1, a0
; RV64IZFH-NEXT: feq.h a1, fa0, fa1
; RV64IZFH-NEXT: not a1, a1
; RV64IZFH-NEXT: and a0, a1, a0
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
%1 = fcmp one half %a, %b %1 = fcmp one half %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_ord(half %a, half %b) nounwind { define i32 @fcmp_ord(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_ord: ; RV32IZFH-LABEL: fcmp_ord:
Show All 12 Lines; RV64IZFH-NEXT: ret
%1 = fcmp ord half %a, %b %1 = fcmp ord half %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_ueq(half %a, half %b) nounwind { define i32 @fcmp_ueq(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_ueq: ; RV32IZFH-LABEL: fcmp_ueq:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: feq.h a0, fa0, fa1 ; RV32IZFH-NEXT: flt.h a0, fa0, fa1
; RV32IZFH-NEXT: feq.h a1, fa1, fa1 ; RV32IZFH-NEXT: flt.h a1, fa1, fa0
; RV32IZFH-NEXT: feq.h a2, fa0, fa0 ; RV32IZFH-NEXT: or a0, a1, a0
; RV32IZFH-NEXT: and a1, a2, a1 ; RV32IZFH-NEXT: xori a0, a0, 1
; RV32IZFH-NEXT: xori a1, a1, 1
; RV32IZFH-NEXT: or a0, a0, a1
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: fcmp_ueq: ; RV64IZFH-LABEL: fcmp_ueq:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa0, fa1 ; RV64IZFH-NEXT: flt.h a0, fa0, fa1
; RV64IZFH-NEXT: feq.h a1, fa1, fa1 ; RV64IZFH-NEXT: flt.h a1, fa1, fa0
; RV64IZFH-NEXT: feq.h a2, fa0, fa0 ; RV64IZFH-NEXT: or a0, a1, a0
; RV64IZFH-NEXT: and a1, a2, a1 ; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: xori a1, a1, 1
; RV64IZFH-NEXT: or a0, a0, a1
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
%1 = fcmp ueq half %a, %b %1 = fcmp ueq half %a, %b
%2 = zext i1 %1 to i32 %2 = zext i1 %1 to i32
ret i32 %2 ret i32 %2
} }
define i32 @fcmp_ugt(half %a, half %b) nounwind { define i32 @fcmp_ugt(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_ugt: ; RV32IZFH-LABEL: fcmp_ugt:
▲ Show 20 Lines • Show All 118 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/half-select-fcmp.ll

Show First 20 Lines • Show All 128 Lines • ▼ Show 20 Lines
; RV64IZFH-NEXT: fmv.h fa0, fa1 ; RV64IZFH-NEXT: fmv.h fa0, fa1
; RV64IZFH-NEXT: .LBB5_2: ; RV64IZFH-NEXT: .LBB5_2:
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
%1 = fcmp ole half %a, %b %1 = fcmp ole half %a, %b
%2 = select i1 %1, half %a, half %b %2 = select i1 %1, half %a, half %b
ret half %2 ret half %2
} }
define half @select_fcmp_one(half %a, half %b) nounwind { define half @select_fcmp_one(half %a, half %b) nounwind {
; TODO: feq.h+sltiu+bne sequence could be optimised
; RV32IZFH-LABEL: select_fcmp_one: ; RV32IZFH-LABEL: select_fcmp_one:
lenaryUnsubmitted
Not Done
ReplyInline Actions

and here!

lenary: and here!
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: feq.h a0, fa1, fa1 ; RV32IZFH-NEXT: flt.h a0, fa0, fa1
; RV32IZFH-NEXT: feq.h a1, fa0, fa0 ; RV32IZFH-NEXT: flt.h a1, fa1, fa0
; RV32IZFH-NEXT: and a0, a1, a0 ; RV32IZFH-NEXT: or a0, a1, a0
; RV32IZFH-NEXT: feq.h a1, fa0, fa1
; RV32IZFH-NEXT: not a1, a1
; RV32IZFH-NEXT: and a0, a1, a0
; RV32IZFH-NEXT: bnez a0, .LBB6_2 ; RV32IZFH-NEXT: bnez a0, .LBB6_2
; RV32IZFH-NEXT: # %bb.1: ; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: fmv.h fa0, fa1 ; RV32IZFH-NEXT: fmv.h fa0, fa1
; RV32IZFH-NEXT: .LBB6_2: ; RV32IZFH-NEXT: .LBB6_2:
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: select_fcmp_one: ; RV64IZFH-LABEL: select_fcmp_one:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa1, fa1 ; RV64IZFH-NEXT: flt.h a0, fa0, fa1
; RV64IZFH-NEXT: feq.h a1, fa0, fa0 ; RV64IZFH-NEXT: flt.h a1, fa1, fa0
; RV64IZFH-NEXT: and a0, a1, a0 ; RV64IZFH-NEXT: or a0, a1, a0
; RV64IZFH-NEXT: feq.h a1, fa0, fa1
; RV64IZFH-NEXT: not a1, a1
; RV64IZFH-NEXT: and a0, a1, a0
; RV64IZFH-NEXT: bnez a0, .LBB6_2 ; RV64IZFH-NEXT: bnez a0, .LBB6_2
; RV64IZFH-NEXT: # %bb.1: ; RV64IZFH-NEXT: # %bb.1:
; RV64IZFH-NEXT: fmv.h fa0, fa1 ; RV64IZFH-NEXT: fmv.h fa0, fa1
; RV64IZFH-NEXT: .LBB6_2: ; RV64IZFH-NEXT: .LBB6_2:
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
%1 = fcmp one half %a, %b %1 = fcmp one half %a, %b
%2 = select i1 %1, half %a, half %b %2 = select i1 %1, half %a, half %b
ret half %2 ret half %2
Show All 24 Lines; RV64IZFH-NEXT: ret
%1 = fcmp ord half %a, %b %1 = fcmp ord half %a, %b
%2 = select i1 %1, half %a, half %b %2 = select i1 %1, half %a, half %b
ret half %2 ret half %2
} }
define half @select_fcmp_ueq(half %a, half %b) nounwind { define half @select_fcmp_ueq(half %a, half %b) nounwind {
; RV32IZFH-LABEL: select_fcmp_ueq: ; RV32IZFH-LABEL: select_fcmp_ueq:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: feq.h a0, fa0, fa1 ; RV32IZFH-NEXT: flt.h a0, fa0, fa1
; RV32IZFH-NEXT: feq.h a1, fa1, fa1 ; RV32IZFH-NEXT: flt.h a1, fa1, fa0
; RV32IZFH-NEXT: feq.h a2, fa0, fa0 ; RV32IZFH-NEXT: or a0, a1, a0
; RV32IZFH-NEXT: and a1, a2, a1 ; RV32IZFH-NEXT: xori a0, a0, 1
; RV32IZFH-NEXT: xori a1, a1, 1
; RV32IZFH-NEXT: or a0, a0, a1
; RV32IZFH-NEXT: bnez a0, .LBB8_2 ; RV32IZFH-NEXT: bnez a0, .LBB8_2
; RV32IZFH-NEXT: # %bb.1: ; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: fmv.h fa0, fa1 ; RV32IZFH-NEXT: fmv.h fa0, fa1
; RV32IZFH-NEXT: .LBB8_2: ; RV32IZFH-NEXT: .LBB8_2:
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
; RV64IZFH-LABEL: select_fcmp_ueq: ; RV64IZFH-LABEL: select_fcmp_ueq:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa0, fa1 ; RV64IZFH-NEXT: flt.h a0, fa0, fa1
; RV64IZFH-NEXT: feq.h a1, fa1, fa1 ; RV64IZFH-NEXT: flt.h a1, fa1, fa0
; RV64IZFH-NEXT: feq.h a2, fa0, fa0 ; RV64IZFH-NEXT: or a0, a1, a0
; RV64IZFH-NEXT: and a1, a2, a1 ; RV64IZFH-NEXT: xori a0, a0, 1
; RV64IZFH-NEXT: xori a1, a1, 1
; RV64IZFH-NEXT: or a0, a0, a1
; RV64IZFH-NEXT: bnez a0, .LBB8_2 ; RV64IZFH-NEXT: bnez a0, .LBB8_2
; RV64IZFH-NEXT: # %bb.1: ; RV64IZFH-NEXT: # %bb.1:
; RV64IZFH-NEXT: fmv.h fa0, fa1 ; RV64IZFH-NEXT: fmv.h fa0, fa1
; RV64IZFH-NEXT: .LBB8_2: ; RV64IZFH-NEXT: .LBB8_2:
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
%1 = fcmp ueq half %a, %b %1 = fcmp ueq half %a, %b
%2 = select i1 %1, half %a, half %b %2 = select i1 %1, half %a, half %b
ret half %2 ret half %2
▲ Show 20 Lines • Show All 193 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll

Show First 20 Lines • Show All 298 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%vc = fcmp ole <vscale x 8 x half> %va, %splat %vc = fcmp ole <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_one_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) { define <vscale x 8 x i1> @fcmp_one_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: fcmp_one_vv_nxv8f16: ; CHECK-LABEL: fcmp_one_vv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfne.vv v25, v16, v18 ; CHECK-NEXT: vmflt.vv v25, v16, v18
; CHECK-NEXT: vmfeq.vv v26, v18, v18 ; CHECK-NEXT: vmflt.vv v26, v18, v16
; CHECK-NEXT: vmfeq.vv v27, v16, v16
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmand.mm v26, v27, v26 ; CHECK-NEXT: vmor.mm v0, v26, v25
; CHECK-NEXT: vmand.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp one <vscale x 8 x half> %va, %vb %vc = fcmp one <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_one_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_one_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_one_vf_nxv8f16: ; CHECK-LABEL: fcmp_one_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vmflt.vf v25, v16, fa0
; CHECK-NEXT: vmfne.vf v25, v16, fa0 ; CHECK-NEXT: vmfgt.vf v26, v16, fa0
; CHECK-NEXT: vmfeq.vf v28, v26, fa0
; CHECK-NEXT: vmfeq.vv v26, v16, v16
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmand.mm v26, v26, v28 ; CHECK-NEXT: vmor.mm v0, v26, v25
; CHECK-NEXT: vmand.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp one <vscale x 8 x half> %va, %splat %vc = fcmp one <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_one_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_one_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_one_fv_nxv8f16: ; CHECK-LABEL: fcmp_one_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vmfgt.vf v25, v16, fa0
; CHECK-NEXT: vmfne.vf v25, v16, fa0 ; CHECK-NEXT: vmflt.vf v26, v16, fa0
; CHECK-NEXT: vmfeq.vf v28, v26, fa0
; CHECK-NEXT: vmfeq.vv v26, v16, v16
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmand.mm v26, v28, v26 ; CHECK-NEXT: vmor.mm v0, v26, v25
; CHECK-NEXT: vmand.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp one <vscale x 8 x half> %splat, %va %vc = fcmp one <vscale x 8 x half> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_one_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 { define <vscale x 8 x i1> @fcmp_one_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%vc = fcmp ord <vscale x 8 x half> %va, %splat %vc = fcmp ord <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) { define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: fcmp_ueq_vv_nxv8f16: ; CHECK-LABEL: fcmp_ueq_vv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfeq.vv v25, v16, v18 ; CHECK-NEXT: vmflt.vv v25, v16, v18
; CHECK-NEXT: vmfne.vv v26, v18, v18 ; CHECK-NEXT: vmflt.vv v26, v18, v16
; CHECK-NEXT: vmfne.vv v27, v16, v16
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmor.mm v26, v27, v26 ; CHECK-NEXT: vmnor.mm v0, v26, v25
; CHECK-NEXT: vmor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ueq <vscale x 8 x half> %va, %vb %vc = fcmp ueq <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ueq_vf_nxv8f16: ; CHECK-LABEL: fcmp_ueq_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vmflt.vf v25, v16, fa0
; CHECK-NEXT: vmfeq.vf v25, v16, fa0 ; CHECK-NEXT: vmfgt.vf v26, v16, fa0
; CHECK-NEXT: vmfne.vf v28, v26, fa0
; CHECK-NEXT: vmfne.vv v26, v16, v16
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmor.mm v26, v26, v28 ; CHECK-NEXT: vmnor.mm v0, v26, v25
; CHECK-NEXT: vmor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ueq <vscale x 8 x half> %va, %splat %vc = fcmp ueq <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ueq_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ueq_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ueq_fv_nxv8f16: ; CHECK-LABEL: fcmp_ueq_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vmfgt.vf v25, v16, fa0
; CHECK-NEXT: vmfeq.vf v25, v16, fa0 ; CHECK-NEXT: vmflt.vf v26, v16, fa0
; CHECK-NEXT: vmfne.vf v28, v26, fa0
; CHECK-NEXT: vmfne.vv v26, v16, v16
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmor.mm v26, v28, v26 ; CHECK-NEXT: vmnor.mm v0, v26, v25
; CHECK-NEXT: vmor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ueq <vscale x 8 x half> %splat, %va %vc = fcmp ueq <vscale x 8 x half> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 { define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
▲ Show 20 Lines • Show All 706 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%vc = fcmp ole <vscale x 8 x float> %va, %splat %vc = fcmp ole <vscale x 8 x float> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_one_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) { define <vscale x 8 x i1> @fcmp_one_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
; CHECK-LABEL: fcmp_one_vv_nxv8f32: ; CHECK-LABEL: fcmp_one_vv_nxv8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vmfne.vv v25, v16, v20 ; CHECK-NEXT: vmflt.vv v25, v16, v20
; CHECK-NEXT: vmfeq.vv v26, v20, v20 ; CHECK-NEXT: vmflt.vv v26, v20, v16
; CHECK-NEXT: vmfeq.vv v27, v16, v16
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmand.mm v26, v27, v26 ; CHECK-NEXT: vmor.mm v0, v26, v25
; CHECK-NEXT: vmand.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp one <vscale x 8 x float> %va, %vb %vc = fcmp one <vscale x 8 x float> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_one_vf_nxv8f32(<vscale x 8 x float> %va, float %b) { define <vscale x 8 x i1> @fcmp_one_vf_nxv8f32(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: fcmp_one_vf_nxv8f32: ; CHECK-LABEL: fcmp_one_vf_nxv8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vfmv.v.f v28, fa0 ; CHECK-NEXT: vmflt.vf v25, v16, fa0
; CHECK-NEXT: vmfne.vf v25, v16, fa0 ; CHECK-NEXT: vmfgt.vf v26, v16, fa0
; CHECK-NEXT: vmfeq.vf v26, v28, fa0
; CHECK-NEXT: vmfeq.vv v27, v16, v16
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmand.mm v26, v27, v26 ; CHECK-NEXT: vmor.mm v0, v26, v25
; CHECK-NEXT: vmand.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0 %head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp one <vscale x 8 x float> %va, %splat %vc = fcmp one <vscale x 8 x float> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_one_fv_nxv8f32(<vscale x 8 x float> %va, float %b) { define <vscale x 8 x i1> @fcmp_one_fv_nxv8f32(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: fcmp_one_fv_nxv8f32: ; CHECK-LABEL: fcmp_one_fv_nxv8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vfmv.v.f v28, fa0 ; CHECK-NEXT: vmfgt.vf v25, v16, fa0
; CHECK-NEXT: vmfne.vf v25, v16, fa0 ; CHECK-NEXT: vmflt.vf v26, v16, fa0
; CHECK-NEXT: vmfeq.vf v26, v28, fa0
; CHECK-NEXT: vmfeq.vv v27, v16, v16
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmand.mm v26, v26, v27 ; CHECK-NEXT: vmor.mm v0, v26, v25
; CHECK-NEXT: vmand.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0 %head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp one <vscale x 8 x float> %splat, %va %vc = fcmp one <vscale x 8 x float> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_one_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) #0 { define <vscale x 8 x i1> @fcmp_one_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) #0 {
▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%vc = fcmp ord <vscale x 8 x float> %va, %splat %vc = fcmp ord <vscale x 8 x float> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) { define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
; CHECK-LABEL: fcmp_ueq_vv_nxv8f32: ; CHECK-LABEL: fcmp_ueq_vv_nxv8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vmfeq.vv v25, v16, v20 ; CHECK-NEXT: vmflt.vv v25, v16, v20
; CHECK-NEXT: vmfne.vv v26, v20, v20 ; CHECK-NEXT: vmflt.vv v26, v20, v16
; CHECK-NEXT: vmfne.vv v27, v16, v16
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmor.mm v26, v27, v26 ; CHECK-NEXT: vmnor.mm v0, v26, v25
; CHECK-NEXT: vmor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ueq <vscale x 8 x float> %va, %vb %vc = fcmp ueq <vscale x 8 x float> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f32(<vscale x 8 x float> %va, float %b) { define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f32(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: fcmp_ueq_vf_nxv8f32: ; CHECK-LABEL: fcmp_ueq_vf_nxv8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vfmv.v.f v28, fa0 ; CHECK-NEXT: vmflt.vf v25, v16, fa0
; CHECK-NEXT: vmfeq.vf v25, v16, fa0 ; CHECK-NEXT: vmfgt.vf v26, v16, fa0
; CHECK-NEXT: vmfne.vf v26, v28, fa0
; CHECK-NEXT: vmfne.vv v27, v16, v16
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmor.mm v26, v27, v26 ; CHECK-NEXT: vmnor.mm v0, v26, v25
; CHECK-NEXT: vmor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0 %head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ueq <vscale x 8 x float> %va, %splat %vc = fcmp ueq <vscale x 8 x float> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ueq_fv_nxv8f32(<vscale x 8 x float> %va, float %b) { define <vscale x 8 x i1> @fcmp_ueq_fv_nxv8f32(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: fcmp_ueq_fv_nxv8f32: ; CHECK-LABEL: fcmp_ueq_fv_nxv8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vfmv.v.f v28, fa0 ; CHECK-NEXT: vmfgt.vf v25, v16, fa0
; CHECK-NEXT: vmfeq.vf v25, v16, fa0 ; CHECK-NEXT: vmflt.vf v26, v16, fa0
; CHECK-NEXT: vmfne.vf v26, v28, fa0
; CHECK-NEXT: vmfne.vv v27, v16, v16
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmor.mm v26, v26, v27 ; CHECK-NEXT: vmnor.mm v0, v26, v25
; CHECK-NEXT: vmor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0 %head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ueq <vscale x 8 x float> %splat, %va %vc = fcmp ueq <vscale x 8 x float> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) #0 { define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) #0 {
▲ Show 20 Lines • Show All 698 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_one_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) { define <vscale x 8 x i1> @fcmp_one_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) {
; CHECK-LABEL: fcmp_one_vv_nxv8f64: ; CHECK-LABEL: fcmp_one_vv_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfne.vv v25, v16, v8 ; CHECK-NEXT: vmflt.vv v25, v16, v8
; CHECK-NEXT: vmfeq.vv v26, v16, v16 ; CHECK-NEXT: vmflt.vv v26, v8, v16
; CHECK-NEXT: vmfeq.vv v27, v8, v8
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmand.mm v26, v26, v27 ; CHECK-NEXT: vmor.mm v0, v26, v25
; CHECK-NEXT: vmand.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp one <vscale x 8 x double> %va, %vb %vc = fcmp one <vscale x 8 x double> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_one_vf_nxv8f64(<vscale x 8 x double> %va, double %b) { define <vscale x 8 x i1> @fcmp_one_vf_nxv8f64(<vscale x 8 x double> %va, double %b) {
; CHECK-LABEL: fcmp_one_vf_nxv8f64: ; CHECK-LABEL: fcmp_one_vf_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: vmflt.vf v25, v16, fa0
; CHECK-NEXT: vmfne.vf v25, v16, fa0 ; CHECK-NEXT: vmfgt.vf v26, v16, fa0
; CHECK-NEXT: vmfeq.vf v26, v8, fa0
; CHECK-NEXT: vmfeq.vv v27, v16, v16
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmand.mm v26, v27, v26 ; CHECK-NEXT: vmor.mm v0, v26, v25
; CHECK-NEXT: vmand.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0 %head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp one <vscale x 8 x double> %va, %splat %vc = fcmp one <vscale x 8 x double> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_one_fv_nxv8f64(<vscale x 8 x double> %va, double %b) { define <vscale x 8 x i1> @fcmp_one_fv_nxv8f64(<vscale x 8 x double> %va, double %b) {
; CHECK-LABEL: fcmp_one_fv_nxv8f64: ; CHECK-LABEL: fcmp_one_fv_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: vmfgt.vf v25, v16, fa0
; CHECK-NEXT: vmfne.vf v25, v16, fa0 ; CHECK-NEXT: vmflt.vf v26, v16, fa0
; CHECK-NEXT: vmfeq.vf v26, v8, fa0
; CHECK-NEXT: vmfeq.vv v27, v16, v16
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmand.mm v26, v26, v27 ; CHECK-NEXT: vmor.mm v0, v26, v25
; CHECK-NEXT: vmand.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0 %head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp one <vscale x 8 x double> %splat, %va %vc = fcmp one <vscale x 8 x double> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_one_vv_nxv8f64_nonans(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) #0 { define <vscale x 8 x i1> @fcmp_one_vv_nxv8f64_nonans(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) #0 {
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ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) { define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) {
; CHECK-LABEL: fcmp_ueq_vv_nxv8f64: ; CHECK-LABEL: fcmp_ueq_vv_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfeq.vv v25, v16, v8 ; CHECK-NEXT: vmflt.vv v25, v16, v8
; CHECK-NEXT: vmfne.vv v26, v16, v16 ; CHECK-NEXT: vmflt.vv v26, v8, v16
; CHECK-NEXT: vmfne.vv v27, v8, v8
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmor.mm v26, v26, v27 ; CHECK-NEXT: vmnor.mm v0, v26, v25
; CHECK-NEXT: vmor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ueq <vscale x 8 x double> %va, %vb %vc = fcmp ueq <vscale x 8 x double> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f64(<vscale x 8 x double> %va, double %b) { define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f64(<vscale x 8 x double> %va, double %b) {
; CHECK-LABEL: fcmp_ueq_vf_nxv8f64: ; CHECK-LABEL: fcmp_ueq_vf_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: vmflt.vf v25, v16, fa0
; CHECK-NEXT: vmfeq.vf v25, v16, fa0 ; CHECK-NEXT: vmfgt.vf v26, v16, fa0
; CHECK-NEXT: vmfne.vf v26, v8, fa0
; CHECK-NEXT: vmfne.vv v27, v16, v16
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmor.mm v26, v27, v26 ; CHECK-NEXT: vmnor.mm v0, v26, v25
; CHECK-NEXT: vmor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0 %head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ueq <vscale x 8 x double> %va, %splat %vc = fcmp ueq <vscale x 8 x double> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ueq_fv_nxv8f64(<vscale x 8 x double> %va, double %b) { define <vscale x 8 x i1> @fcmp_ueq_fv_nxv8f64(<vscale x 8 x double> %va, double %b) {
; CHECK-LABEL: fcmp_ueq_fv_nxv8f64: ; CHECK-LABEL: fcmp_ueq_fv_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: vmfgt.vf v25, v16, fa0
; CHECK-NEXT: vmfeq.vf v25, v16, fa0 ; CHECK-NEXT: vmflt.vf v26, v16, fa0
; CHECK-NEXT: vmfne.vf v26, v8, fa0
; CHECK-NEXT: vmfne.vv v27, v16, v16
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmor.mm v26, v26, v27 ; CHECK-NEXT: vmnor.mm v0, v26, v25
; CHECK-NEXT: vmor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0 %head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ueq <vscale x 8 x double> %splat, %va %vc = fcmp ueq <vscale x 8 x double> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f64_nonans(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) #0 { define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f64_nonans(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) #0 {
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llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll

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%vc = fcmp ole <vscale x 8 x half> %va, %splat %vc = fcmp ole <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_one_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) { define <vscale x 8 x i1> @fcmp_one_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: fcmp_one_vv_nxv8f16: ; CHECK-LABEL: fcmp_one_vv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfne.vv v25, v16, v18 ; CHECK-NEXT: vmflt.vv v25, v16, v18
; CHECK-NEXT: vmfeq.vv v26, v18, v18 ; CHECK-NEXT: vmflt.vv v26, v18, v16
; CHECK-NEXT: vmfeq.vv v27, v16, v16
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmand.mm v26, v27, v26 ; CHECK-NEXT: vmor.mm v0, v26, v25
; CHECK-NEXT: vmand.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp one <vscale x 8 x half> %va, %vb %vc = fcmp one <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_one_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_one_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_one_vf_nxv8f16: ; CHECK-LABEL: fcmp_one_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vmflt.vf v25, v16, fa0
; CHECK-NEXT: vmfne.vf v25, v16, fa0 ; CHECK-NEXT: vmfgt.vf v26, v16, fa0
; CHECK-NEXT: vmfeq.vf v28, v26, fa0
; CHECK-NEXT: vmfeq.vv v26, v16, v16
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmand.mm v26, v26, v28 ; CHECK-NEXT: vmor.mm v0, v26, v25
; CHECK-NEXT: vmand.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp one <vscale x 8 x half> %va, %splat %vc = fcmp one <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_one_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_one_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_one_fv_nxv8f16: ; CHECK-LABEL: fcmp_one_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vmfgt.vf v25, v16, fa0
; CHECK-NEXT: vmfne.vf v25, v16, fa0 ; CHECK-NEXT: vmflt.vf v26, v16, fa0
; CHECK-NEXT: vmfeq.vf v28, v26, fa0
; CHECK-NEXT: vmfeq.vv v26, v16, v16
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmand.mm v26, v28, v26 ; CHECK-NEXT: vmor.mm v0, v26, v25
; CHECK-NEXT: vmand.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp one <vscale x 8 x half> %splat, %va %vc = fcmp one <vscale x 8 x half> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_one_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 { define <vscale x 8 x i1> @fcmp_one_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
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%vc = fcmp ord <vscale x 8 x half> %va, %splat %vc = fcmp ord <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) { define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) {
; CHECK-LABEL: fcmp_ueq_vv_nxv8f16: ; CHECK-LABEL: fcmp_ueq_vv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmfeq.vv v25, v16, v18 ; CHECK-NEXT: vmflt.vv v25, v16, v18
; CHECK-NEXT: vmfne.vv v26, v18, v18 ; CHECK-NEXT: vmflt.vv v26, v18, v16
; CHECK-NEXT: vmfne.vv v27, v16, v16
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmor.mm v26, v27, v26 ; CHECK-NEXT: vmnor.mm v0, v26, v25
; CHECK-NEXT: vmor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ueq <vscale x 8 x half> %va, %vb %vc = fcmp ueq <vscale x 8 x half> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ueq_vf_nxv8f16: ; CHECK-LABEL: fcmp_ueq_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vmflt.vf v25, v16, fa0
; CHECK-NEXT: vmfeq.vf v25, v16, fa0 ; CHECK-NEXT: vmfgt.vf v26, v16, fa0
; CHECK-NEXT: vmfne.vf v28, v26, fa0
; CHECK-NEXT: vmfne.vv v26, v16, v16
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmor.mm v26, v26, v28 ; CHECK-NEXT: vmnor.mm v0, v26, v25
; CHECK-NEXT: vmor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ueq <vscale x 8 x half> %va, %splat %vc = fcmp ueq <vscale x 8 x half> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ueq_fv_nxv8f16(<vscale x 8 x half> %va, half %b) { define <vscale x 8 x i1> @fcmp_ueq_fv_nxv8f16(<vscale x 8 x half> %va, half %b) {
; CHECK-LABEL: fcmp_ueq_fv_nxv8f16: ; CHECK-LABEL: fcmp_ueq_fv_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f ; CHECK-NEXT: # kill: def $f10_h killed $f10_h def $f10_f
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfmv.v.f v26, fa0 ; CHECK-NEXT: vmfgt.vf v25, v16, fa0
; CHECK-NEXT: vmfeq.vf v25, v16, fa0 ; CHECK-NEXT: vmflt.vf v26, v16, fa0
; CHECK-NEXT: vmfne.vf v28, v26, fa0
; CHECK-NEXT: vmfne.vv v26, v16, v16
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmor.mm v26, v28, v26 ; CHECK-NEXT: vmnor.mm v0, v26, v25
; CHECK-NEXT: vmor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x half> undef, half %b, i32 0 %head = insertelement <vscale x 8 x half> undef, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ueq <vscale x 8 x half> %splat, %va %vc = fcmp ueq <vscale x 8 x half> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 { define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f16_nonans(<vscale x 8 x half> %va, <vscale x 8 x half> %vb) #0 {
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%vc = fcmp ole <vscale x 8 x float> %va, %splat %vc = fcmp ole <vscale x 8 x float> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_one_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) { define <vscale x 8 x i1> @fcmp_one_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
; CHECK-LABEL: fcmp_one_vv_nxv8f32: ; CHECK-LABEL: fcmp_one_vv_nxv8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vmfne.vv v25, v16, v20 ; CHECK-NEXT: vmflt.vv v25, v16, v20
; CHECK-NEXT: vmfeq.vv v26, v20, v20 ; CHECK-NEXT: vmflt.vv v26, v20, v16
; CHECK-NEXT: vmfeq.vv v27, v16, v16
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmand.mm v26, v27, v26 ; CHECK-NEXT: vmor.mm v0, v26, v25
; CHECK-NEXT: vmand.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp one <vscale x 8 x float> %va, %vb %vc = fcmp one <vscale x 8 x float> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_one_vf_nxv8f32(<vscale x 8 x float> %va, float %b) { define <vscale x 8 x i1> @fcmp_one_vf_nxv8f32(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: fcmp_one_vf_nxv8f32: ; CHECK-LABEL: fcmp_one_vf_nxv8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vfmv.v.f v28, fa0 ; CHECK-NEXT: vmflt.vf v25, v16, fa0
; CHECK-NEXT: vmfne.vf v25, v16, fa0 ; CHECK-NEXT: vmfgt.vf v26, v16, fa0
; CHECK-NEXT: vmfeq.vf v26, v28, fa0
; CHECK-NEXT: vmfeq.vv v27, v16, v16
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmand.mm v26, v27, v26 ; CHECK-NEXT: vmor.mm v0, v26, v25
; CHECK-NEXT: vmand.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0 %head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp one <vscale x 8 x float> %va, %splat %vc = fcmp one <vscale x 8 x float> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_one_fv_nxv8f32(<vscale x 8 x float> %va, float %b) { define <vscale x 8 x i1> @fcmp_one_fv_nxv8f32(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: fcmp_one_fv_nxv8f32: ; CHECK-LABEL: fcmp_one_fv_nxv8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vfmv.v.f v28, fa0 ; CHECK-NEXT: vmfgt.vf v25, v16, fa0
; CHECK-NEXT: vmfne.vf v25, v16, fa0 ; CHECK-NEXT: vmflt.vf v26, v16, fa0
; CHECK-NEXT: vmfeq.vf v26, v28, fa0
; CHECK-NEXT: vmfeq.vv v27, v16, v16
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmand.mm v26, v26, v27 ; CHECK-NEXT: vmor.mm v0, v26, v25
; CHECK-NEXT: vmand.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0 %head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp one <vscale x 8 x float> %splat, %va %vc = fcmp one <vscale x 8 x float> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_one_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) #0 { define <vscale x 8 x i1> @fcmp_one_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) #0 {
▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%vc = fcmp ord <vscale x 8 x float> %va, %splat %vc = fcmp ord <vscale x 8 x float> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) { define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
; CHECK-LABEL: fcmp_ueq_vv_nxv8f32: ; CHECK-LABEL: fcmp_ueq_vv_nxv8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vmfeq.vv v25, v16, v20 ; CHECK-NEXT: vmflt.vv v25, v16, v20
; CHECK-NEXT: vmfne.vv v26, v20, v20 ; CHECK-NEXT: vmflt.vv v26, v20, v16
; CHECK-NEXT: vmfne.vv v27, v16, v16
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmor.mm v26, v27, v26 ; CHECK-NEXT: vmnor.mm v0, v26, v25
; CHECK-NEXT: vmor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ueq <vscale x 8 x float> %va, %vb %vc = fcmp ueq <vscale x 8 x float> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f32(<vscale x 8 x float> %va, float %b) { define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f32(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: fcmp_ueq_vf_nxv8f32: ; CHECK-LABEL: fcmp_ueq_vf_nxv8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vfmv.v.f v28, fa0 ; CHECK-NEXT: vmflt.vf v25, v16, fa0
; CHECK-NEXT: vmfeq.vf v25, v16, fa0 ; CHECK-NEXT: vmfgt.vf v26, v16, fa0
; CHECK-NEXT: vmfne.vf v26, v28, fa0
; CHECK-NEXT: vmfne.vv v27, v16, v16
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmor.mm v26, v27, v26 ; CHECK-NEXT: vmnor.mm v0, v26, v25
; CHECK-NEXT: vmor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0 %head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ueq <vscale x 8 x float> %va, %splat %vc = fcmp ueq <vscale x 8 x float> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ueq_fv_nxv8f32(<vscale x 8 x float> %va, float %b) { define <vscale x 8 x i1> @fcmp_ueq_fv_nxv8f32(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: fcmp_ueq_fv_nxv8f32: ; CHECK-LABEL: fcmp_ueq_fv_nxv8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vfmv.v.f v28, fa0 ; CHECK-NEXT: vmfgt.vf v25, v16, fa0
; CHECK-NEXT: vmfeq.vf v25, v16, fa0 ; CHECK-NEXT: vmflt.vf v26, v16, fa0
; CHECK-NEXT: vmfne.vf v26, v28, fa0
; CHECK-NEXT: vmfne.vv v27, v16, v16
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmor.mm v26, v26, v27 ; CHECK-NEXT: vmnor.mm v0, v26, v25
; CHECK-NEXT: vmor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> undef, float %b, i32 0 %head = insertelement <vscale x 8 x float> undef, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ueq <vscale x 8 x float> %splat, %va %vc = fcmp ueq <vscale x 8 x float> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) #0 { define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f32_nonans(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) #0 {
▲ Show 20 Lines • Show All 698 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_one_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) { define <vscale x 8 x i1> @fcmp_one_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) {
; CHECK-LABEL: fcmp_one_vv_nxv8f64: ; CHECK-LABEL: fcmp_one_vv_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfne.vv v25, v16, v8 ; CHECK-NEXT: vmflt.vv v25, v16, v8
; CHECK-NEXT: vmfeq.vv v26, v16, v16 ; CHECK-NEXT: vmflt.vv v26, v8, v16
; CHECK-NEXT: vmfeq.vv v27, v8, v8
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmand.mm v26, v26, v27 ; CHECK-NEXT: vmor.mm v0, v26, v25
; CHECK-NEXT: vmand.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp one <vscale x 8 x double> %va, %vb %vc = fcmp one <vscale x 8 x double> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_one_vf_nxv8f64(<vscale x 8 x double> %va, double %b) { define <vscale x 8 x i1> @fcmp_one_vf_nxv8f64(<vscale x 8 x double> %va, double %b) {
; CHECK-LABEL: fcmp_one_vf_nxv8f64: ; CHECK-LABEL: fcmp_one_vf_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: vmflt.vf v25, v16, fa0
; CHECK-NEXT: vmfne.vf v25, v16, fa0 ; CHECK-NEXT: vmfgt.vf v26, v16, fa0
; CHECK-NEXT: vmfeq.vf v26, v8, fa0
; CHECK-NEXT: vmfeq.vv v27, v16, v16
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmand.mm v26, v27, v26 ; CHECK-NEXT: vmor.mm v0, v26, v25
; CHECK-NEXT: vmand.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0 %head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp one <vscale x 8 x double> %va, %splat %vc = fcmp one <vscale x 8 x double> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_one_fv_nxv8f64(<vscale x 8 x double> %va, double %b) { define <vscale x 8 x i1> @fcmp_one_fv_nxv8f64(<vscale x 8 x double> %va, double %b) {
; CHECK-LABEL: fcmp_one_fv_nxv8f64: ; CHECK-LABEL: fcmp_one_fv_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: vmfgt.vf v25, v16, fa0
; CHECK-NEXT: vmfne.vf v25, v16, fa0 ; CHECK-NEXT: vmflt.vf v26, v16, fa0
; CHECK-NEXT: vmfeq.vf v26, v8, fa0
; CHECK-NEXT: vmfeq.vv v27, v16, v16
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmand.mm v26, v26, v27 ; CHECK-NEXT: vmor.mm v0, v26, v25
; CHECK-NEXT: vmand.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0 %head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp one <vscale x 8 x double> %splat, %va %vc = fcmp one <vscale x 8 x double> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_one_vv_nxv8f64_nonans(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) #0 { define <vscale x 8 x i1> @fcmp_one_vv_nxv8f64_nonans(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) #0 {
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) { define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) {
; CHECK-LABEL: fcmp_ueq_vv_nxv8f64: ; CHECK-LABEL: fcmp_ueq_vv_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vmfeq.vv v25, v16, v8 ; CHECK-NEXT: vmflt.vv v25, v16, v8
; CHECK-NEXT: vmfne.vv v26, v16, v16 ; CHECK-NEXT: vmflt.vv v26, v8, v16
; CHECK-NEXT: vmfne.vv v27, v8, v8
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmor.mm v26, v26, v27 ; CHECK-NEXT: vmnor.mm v0, v26, v25
; CHECK-NEXT: vmor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = fcmp ueq <vscale x 8 x double> %va, %vb %vc = fcmp ueq <vscale x 8 x double> %va, %vb
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f64(<vscale x 8 x double> %va, double %b) { define <vscale x 8 x i1> @fcmp_ueq_vf_nxv8f64(<vscale x 8 x double> %va, double %b) {
; CHECK-LABEL: fcmp_ueq_vf_nxv8f64: ; CHECK-LABEL: fcmp_ueq_vf_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: vmflt.vf v25, v16, fa0
; CHECK-NEXT: vmfeq.vf v25, v16, fa0 ; CHECK-NEXT: vmfgt.vf v26, v16, fa0
; CHECK-NEXT: vmfne.vf v26, v8, fa0
; CHECK-NEXT: vmfne.vv v27, v16, v16
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmor.mm v26, v27, v26 ; CHECK-NEXT: vmnor.mm v0, v26, v25
; CHECK-NEXT: vmor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0 %head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ueq <vscale x 8 x double> %va, %splat %vc = fcmp ueq <vscale x 8 x double> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ueq_fv_nxv8f64(<vscale x 8 x double> %va, double %b) { define <vscale x 8 x i1> @fcmp_ueq_fv_nxv8f64(<vscale x 8 x double> %va, double %b) {
; CHECK-LABEL: fcmp_ueq_fv_nxv8f64: ; CHECK-LABEL: fcmp_ueq_fv_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vfmv.v.f v8, fa0 ; CHECK-NEXT: vmfgt.vf v25, v16, fa0
; CHECK-NEXT: vmfeq.vf v25, v16, fa0 ; CHECK-NEXT: vmflt.vf v26, v16, fa0
; CHECK-NEXT: vmfne.vf v26, v8, fa0
; CHECK-NEXT: vmfne.vv v27, v16, v16
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmor.mm v26, v26, v27 ; CHECK-NEXT: vmnor.mm v0, v26, v25
; CHECK-NEXT: vmor.mm v0, v25, v26
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x double> undef, double %b, i32 0 %head = insertelement <vscale x 8 x double> undef, double %b, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> undef, <vscale x 8 x i32> zeroinitializer
%vc = fcmp ueq <vscale x 8 x double> %splat, %va %vc = fcmp ueq <vscale x 8 x double> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f64_nonans(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) #0 { define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f64_nonans(<vscale x 8 x double> %va, <vscale x 8 x double> %vb) #0 {
▲ Show 20 Lines • Show All 425 Lines • Show Last 20 Lines

llvm/test/CodeGen/WebAssembly/comparisons-f32.ll

Show First 20 Lines • Show All 96 Lines • ▼ Show 20 Lines
; Expanded comparisons, which also check for NaN. ; Expanded comparisons, which also check for NaN.
; These simply rely on SDAG's Expand cond code action. ; These simply rely on SDAG's Expand cond code action.
; CHECK-LABEL: ueq_f32: ; CHECK-LABEL: ueq_f32:
; CHECK-NEXT: .functype ueq_f32 (f32, f32) -> (i32){{$}} ; CHECK-NEXT: .functype ueq_f32 (f32, f32) -> (i32){{$}}
; CHECK-NEXT: local.get $push[[L0:[0-9]+]]=, 0{{$}} ; CHECK-NEXT: local.get $push[[L0:[0-9]+]]=, 0{{$}}
; CHECK-NEXT: local.get $push[[L1:[0-9]+]]=, 1{{$}} ; CHECK-NEXT: local.get $push[[L1:[0-9]+]]=, 1{{$}}
; CHECK-NEXT: f32.eq $push[[NUM0:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}} ; CHECK-NEXT: f32.gt $push[[NUM0:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
; CHECK-NEXT: local.get $push[[L2:[0-9]+]]=, 0{{$}} ; CHECK-NEXT: local.get $push[[L2:[0-9]+]]=, 0{{$}}
; CHECK-NEXT: local.get $push[[L3:[0-9]+]]=, 0{{$}} ; CHECK-NEXT: local.get $push[[L3:[0-9]+]]=, 1{{$}}
; CHECK-NEXT: f32.ne $push[[NUM1:[0-9]+]]=, $pop[[L2]], $pop[[L3]]{{$}} ; CHECK-NEXT: f32.lt $push[[NUM1:[0-9]+]]=, $pop[[L2]], $pop[[L3]]{{$}}
; CHECK-NEXT: local.get $push[[L4:[0-9]+]]=, 1{{$}} ; CHECK-NEXT: i32.or $push[[NUM2:[0-9]+]]=, $pop[[NUM0]], $pop[[NUM1]]{{$}}
; CHECK-NEXT: local.get $push[[L5:[0-9]+]]=, 1{{$}} ; CHECK-NEXT: i32.const $push[[C0:[0-9]+]]=, 1
; CHECK-NEXT: f32.ne $push[[NUM2:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}} ; CHECK-NEXT: i32.xor $push[[NUM3:[0-9]+]]=, $pop[[NUM2]], $pop[[C0]]{{$}}
; CHECK-NEXT: i32.or $push[[NUM3:[0-9]+]]=, $pop[[NUM1]], $pop[[NUM2]]{{$}} ; CHECK-NEXT: return $pop[[NUM3]]{{$}}
; CHECK-NEXT: i32.or $push[[NUM4:[0-9]+]]=, $pop[[NUM0]], $pop[[NUM3]]{{$}}
; CHECK-NEXT: return $pop[[NUM4]]{{$}}
define i32 @ueq_f32(float %x, float %y) { define i32 @ueq_f32(float %x, float %y) {
%a = fcmp ueq float %x, %y %a = fcmp ueq float %x, %y
%b = zext i1 %a to i32 %b = zext i1 %a to i32
ret i32 %b ret i32 %b
} }
; CHECK-LABEL: one_f32: ; CHECK-LABEL: one_f32:
; CHECK-NEXT: .functype one_f32 (f32, f32) -> (i32){{$}} ; CHECK-NEXT: .functype one_f32 (f32, f32) -> (i32){{$}}
; CHECK-NEXT: local.get $push[[L0:[0-9]+]]=, 0{{$}} ; CHECK-NEXT: local.get $push[[L0:[0-9]+]]=, 0{{$}}
; CHECK-NEXT: local.get $push[[L1:[0-9]+]]=, 1{{$}} ; CHECK-NEXT: local.get $push[[L1:[0-9]+]]=, 1{{$}}
; CHECK-NEXT: f32.ne $push[[NUM0:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}} ; CHECK-NEXT: f32.gt $push[[NUM0:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
; CHECK-NEXT: local.get $push[[L2:[0-9]+]]=, 0{{$}} ; CHECK-NEXT: local.get $push[[L2:[0-9]+]]=, 0{{$}}
; CHECK-NEXT: local.get $push[[L3:[0-9]+]]=, 0{{$}} ; CHECK-NEXT: local.get $push[[L3:[0-9]+]]=, 1{{$}}
; CHECK-NEXT: f32.eq $push[[NUM1:[0-9]+]]=, $pop[[L2]], $pop[[L3]]{{$}} ; CHECK-NEXT: f32.lt $push[[NUM1:[0-9]+]]=, $pop[[L2]], $pop[[L3]]{{$}}
; CHECK-NEXT: local.get $push[[L4:[0-9]+]]=, 1{{$}} ; CHECK-NEXT: i32.or $push[[NUM4:[0-9]+]]=, $pop[[NUM0]], $pop[[NUM1]]{{$}}
; CHECK-NEXT: local.get $push[[L5:[0-9]+]]=, 1{{$}}
; CHECK-NEXT: f32.eq $push[[NUM2:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}}
; CHECK-NEXT: i32.and $push[[NUM3:[0-9]+]]=, $pop[[NUM1]], $pop[[NUM2]]{{$}}
; CHECK-NEXT: i32.and $push[[NUM4:[0-9]+]]=, $pop[[NUM0]], $pop[[NUM3]]{{$}}
; CHECK-NEXT: return $pop[[NUM4]] ; CHECK-NEXT: return $pop[[NUM4]]
define i32 @one_f32(float %x, float %y) { define i32 @one_f32(float %x, float %y) {
%a = fcmp one float %x, %y %a = fcmp one float %x, %y
%b = zext i1 %a to i32 %b = zext i1 %a to i32
ret i32 %b ret i32 %b
} }
; CHECK-LABEL: ult_f32: ; CHECK-LABEL: ult_f32:
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines

llvm/test/CodeGen/WebAssembly/comparisons-f64.ll

Show First 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
} }
; Expanded comparisons, which also check for NaN. ; Expanded comparisons, which also check for NaN.
; CHECK-LABEL: ueq_f64: ; CHECK-LABEL: ueq_f64:
; CHECK-NEXT: .functype ueq_f64 (f64, f64) -> (i32){{$}} ; CHECK-NEXT: .functype ueq_f64 (f64, f64) -> (i32){{$}}
; CHECK-NEXT: local.get $push[[L0:[0-9]+]]=, 0{{$}} ; CHECK-NEXT: local.get $push[[L0:[0-9]+]]=, 0{{$}}
; CHECK-NEXT: local.get $push[[L1:[0-9]+]]=, 1{{$}} ; CHECK-NEXT: local.get $push[[L1:[0-9]+]]=, 1{{$}}
; CHECK-NEXT: f64.eq $push[[NUM0:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}} ; CHECK-NEXT: f64.gt $push[[NUM0:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
; CHECK-NEXT: local.get $push[[L2:[0-9]+]]=, 0{{$}} ; CHECK-NEXT: local.get $push[[L2:[0-9]+]]=, 0{{$}}
; CHECK-NEXT: local.get $push[[L3:[0-9]+]]=, 0{{$}} ; CHECK-NEXT: local.get $push[[L3:[0-9]+]]=, 1{{$}}
; CHECK-NEXT: f64.ne $push[[NUM1:[0-9]+]]=, $pop[[L2]], $pop[[L3]]{{$}} ; CHECK-NEXT: f64.lt $push[[NUM1:[0-9]+]]=, $pop[[L2]], $pop[[L3]]{{$}}
; CHECK-NEXT: local.get $push[[L4:[0-9]+]]=, 1{{$}} ; CHECK-NEXT: i32.or $push[[NUM2:[0-9]+]]=, $pop[[NUM0]], $pop[[NUM1]]{{$}}
; CHECK-NEXT: local.get $push[[L5:[0-9]+]]=, 1{{$}} ; CHECK-NEXT: i32.const $push[[C0:[0-9]+]]=, 1
; CHECK-NEXT: f64.ne $push[[NUM2:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}} ; CHECK-NEXT: i32.xor $push[[NUM3:[0-9]+]]=, $pop[[NUM2]], $pop[[C0]]{{$}}
; CHECK-NEXT: i32.or $push[[NUM3:[0-9]+]]=, $pop[[NUM1]], $pop[[NUM2]]{{$}} ; CHECK-NEXT: return $pop[[NUM3]]{{$}}
; CHECK-NEXT: i32.or $push[[NUM4:[0-9]+]]=, $pop[[NUM0]], $pop[[NUM3]]{{$}}
; CHECK-NEXT: return $pop[[NUM4]]{{$}}
define i32 @ueq_f64(double %x, double %y) { define i32 @ueq_f64(double %x, double %y) {
%a = fcmp ueq double %x, %y %a = fcmp ueq double %x, %y
%b = zext i1 %a to i32 %b = zext i1 %a to i32
ret i32 %b ret i32 %b
} }
; CHECK-LABEL: one_f64: ; CHECK-LABEL: one_f64:
; CHECK-NEXT: .functype one_f64 (f64, f64) -> (i32){{$}} ; CHECK-NEXT: .functype one_f64 (f64, f64) -> (i32){{$}}
; CHECK-NEXT: local.get $push[[L0:[0-9]+]]=, 0{{$}} ; CHECK-NEXT: local.get $push[[L0:[0-9]+]]=, 0{{$}}
; CHECK-NEXT: local.get $push[[L1:[0-9]+]]=, 1{{$}} ; CHECK-NEXT: local.get $push[[L1:[0-9]+]]=, 1{{$}}
; CHECK-NEXT: f64.ne $push[[NUM0:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}} ; CHECK-NEXT: f64.gt $push[[NUM0:[0-9]+]]=, $pop[[L0]], $pop[[L1]]{{$}}
; CHECK-NEXT: local.get $push[[L2:[0-9]+]]=, 0{{$}} ; CHECK-NEXT: local.get $push[[L2:[0-9]+]]=, 0{{$}}
; CHECK-NEXT: local.get $push[[L3:[0-9]+]]=, 0{{$}} ; CHECK-NEXT: local.get $push[[L3:[0-9]+]]=, 1{{$}}
; CHECK-NEXT: f64.eq $push[[NUM1:[0-9]+]]=, $pop[[L2]], $pop[[L3]]{{$}} ; CHECK-NEXT: f64.lt $push[[NUM1:[0-9]+]]=, $pop[[L2]], $pop[[L3]]{{$}}
; CHECK-NEXT: local.get $push[[L4:[0-9]+]]=, 1{{$}} ; CHECK-NEXT: i32.or $push[[NUM4:[0-9]+]]=, $pop[[NUM0]], $pop[[NUM1]]{{$}}
; CHECK-NEXT: local.get $push[[L5:[0-9]+]]=, 1{{$}}
; CHECK-NEXT: f64.eq $push[[NUM2:[0-9]+]]=, $pop[[L4]], $pop[[L5]]{{$}}
; CHECK-NEXT: i32.and $push[[NUM3:[0-9]+]]=, $pop[[NUM1]], $pop[[NUM2]]{{$}}
; CHECK-NEXT: i32.and $push[[NUM4:[0-9]+]]=, $pop[[NUM0]], $pop[[NUM3]]{{$}}
; CHECK-NEXT: return $pop[[NUM4]] ; CHECK-NEXT: return $pop[[NUM4]]
define i32 @one_f64(double %x, double %y) { define i32 @one_f64(double %x, double %y) {
%a = fcmp one double %x, %y %a = fcmp one double %x, %y
%b = zext i1 %a to i32 %b = zext i1 %a to i32
ret i32 %b ret i32 %b
} }
; CHECK-LABEL: ult_f64: ; CHECK-LABEL: ult_f64:
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines

llvm/test/CodeGen/WebAssembly/simd-comparisons.ll

Show First 20 Lines • Show All 994 Lines • ▼ Show 20 Linesdefine <4 x i32> @compare_sext_ole_nnan_v4f32 (<4 x float> %x, <4 x float> %y) {
%cmp = fcmp nnan ole <4 x float> %x, %y %cmp = fcmp nnan ole <4 x float> %x, %y
%res = sext <4 x i1> %cmp to <4 x i32> %res = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %res ret <4 x i32> %res
} }
; CHECK-LABEL: compare_one_v4f32: ; CHECK-LABEL: compare_one_v4f32:
; NO-SIMD128-NOT: f32x4 ; NO-SIMD128-NOT: f32x4
; SIMD128-NEXT: .functype compare_one_v4f32 (v128, v128) -> (v128){{$}} ; SIMD128-NEXT: .functype compare_one_v4f32 (v128, v128) -> (v128){{$}}
; SIMD128-NEXT: f32x4.ne $push[[T0:[0-9]+]]=, $0, $1{{$}} ; SIMD128-NEXT: f32x4.gt $push[[T0:[0-9]+]]=, $0, $1{{$}}
; SIMD128-NEXT: f32x4.eq $push[[T1:[0-9]+]]=, $0, $0{{$}} ; SIMD128-NEXT: f32x4.lt $push[[T1:[0-9]+]]=, $0, $1{{$}}
; SIMD128-NEXT: f32x4.eq $push[[T2:[0-9]+]]=, $1, $1{{$}} ; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
; SIMD128-NEXT: v128.and $push[[T3:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T3]]{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}} ; SIMD128-NEXT: return $pop[[R]]{{$}}
define <4 x i1> @compare_one_v4f32 (<4 x float> %x, <4 x float> %y) { define <4 x i1> @compare_one_v4f32 (<4 x float> %x, <4 x float> %y) {
%res = fcmp one <4 x float> %x, %y %res = fcmp one <4 x float> %x, %y
ret <4 x i1> %res ret <4 x i1> %res
} }
; CHECK-LABEL: compare_one_nnan_v4f32: ; CHECK-LABEL: compare_one_nnan_v4f32:
; NO-SIMD128-NOT: f32x4 ; NO-SIMD128-NOT: f32x4
; SIMD128-NEXT: .functype compare_one_nnan_v4f32 (v128, v128) -> (v128){{$}} ; SIMD128-NEXT: .functype compare_one_nnan_v4f32 (v128, v128) -> (v128){{$}}
; SIMD128-NEXT: f32x4.ne $push[[R:[0-9]+]]=, $0, $1{{$}} ; SIMD128-NEXT: f32x4.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}} ; SIMD128-NEXT: return $pop[[R]]{{$}}
define <4 x i1> @compare_one_nnan_v4f32 (<4 x float> %x, <4 x float> %y) { define <4 x i1> @compare_one_nnan_v4f32 (<4 x float> %x, <4 x float> %y) {
%res = fcmp nnan one <4 x float> %x, %y %res = fcmp nnan one <4 x float> %x, %y
ret <4 x i1> %res ret <4 x i1> %res
} }
; CHECK-LABEL: compare_sext_one_v4f32: ; CHECK-LABEL: compare_sext_one_v4f32:
; NO-SIMD128-NOT: f32x4 ; NO-SIMD128-NOT: f32x4
; SIMD128-NEXT: .functype compare_sext_one_v4f32 (v128, v128) -> (v128){{$}} ; SIMD128-NEXT: .functype compare_sext_one_v4f32 (v128, v128) -> (v128){{$}}
; SIMD128-NEXT: f32x4.ne $push[[T0:[0-9]+]]=, $0, $1{{$}} ; SIMD128-NEXT: f32x4.gt $push[[T0:[0-9]+]]=, $0, $1{{$}}
; SIMD128-NEXT: f32x4.eq $push[[T1:[0-9]+]]=, $0, $0{{$}} ; SIMD128-NEXT: f32x4.lt $push[[T1:[0-9]+]]=, $0, $1{{$}}
; SIMD128-NEXT: f32x4.eq $push[[T2:[0-9]+]]=, $1, $1{{$}} ; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
; SIMD128-NEXT: v128.and $push[[T3:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T3]]{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}} ; SIMD128-NEXT: return $pop[[R]]{{$}}
define <4 x i32> @compare_sext_one_v4f32 (<4 x float> %x, <4 x float> %y) { define <4 x i32> @compare_sext_one_v4f32 (<4 x float> %x, <4 x float> %y) {
%cmp = fcmp one <4 x float> %x, %y %cmp = fcmp one <4 x float> %x, %y
%res = sext <4 x i1> %cmp to <4 x i32> %res = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %res ret <4 x i32> %res
} }
; CHECK-LABEL: compare_sext_one_nnan_v4f32: ; CHECK-LABEL: compare_sext_one_nnan_v4f32:
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Linesdefine <4 x i32> @compare_sext_ord_nnan_v4f32 (<4 x float> %x, <4 x float> %y) {
%cmp = fcmp nnan ord <4 x float> %x, %y %cmp = fcmp nnan ord <4 x float> %x, %y
%res = sext <4 x i1> %cmp to <4 x i32> %res = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %res ret <4 x i32> %res
} }
; CHECK-LABEL: compare_ueq_v4f32: ; CHECK-LABEL: compare_ueq_v4f32:
; NO-SIMD128-NOT: f32x4 ; NO-SIMD128-NOT: f32x4
; SIMD128-NEXT: .functype compare_ueq_v4f32 (v128, v128) -> (v128){{$}} ; SIMD128-NEXT: .functype compare_ueq_v4f32 (v128, v128) -> (v128){{$}}
; SIMD128-NEXT: f32x4.eq $push[[T0:[0-9]+]]=, $0, $1{{$}} ; SIMD128-NEXT: f32x4.gt $push[[T0:[0-9]+]]=, $0, $1{{$}}
; SIMD128-NEXT: f32x4.ne $push[[T1:[0-9]+]]=, $0, $0{{$}} ; SIMD128-NEXT: f32x4.lt $push[[T1:[0-9]+]]=, $0, $1{{$}}
; SIMD128-NEXT: f32x4.ne $push[[T2:[0-9]+]]=, $1, $1{{$}} ; SIMD128-NEXT: v128.or $push[[T2:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
; SIMD128-NEXT: v128.or $push[[T3:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}} ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T2]]{{$}}
; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T3]]{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}} ; SIMD128-NEXT: return $pop[[R]]{{$}}
define <4 x i1> @compare_ueq_v4f32 (<4 x float> %x, <4 x float> %y) { define <4 x i1> @compare_ueq_v4f32 (<4 x float> %x, <4 x float> %y) {
%res = fcmp ueq <4 x float> %x, %y %res = fcmp ueq <4 x float> %x, %y
ret <4 x i1> %res ret <4 x i1> %res
} }
; CHECK-LABEL: compare_ueq_nnan_v4f32: ; CHECK-LABEL: compare_ueq_nnan_v4f32:
; NO-SIMD128-NOT: f32x4 ; NO-SIMD128-NOT: f32x4
; SIMD128-NEXT: .functype compare_ueq_nnan_v4f32 (v128, v128) -> (v128){{$}} ; SIMD128-NEXT: .functype compare_ueq_nnan_v4f32 (v128, v128) -> (v128){{$}}
; SIMD128-NEXT: f32x4.eq $push[[R:[0-9]+]]=, $0, $1{{$}} ; SIMD128-NEXT: f32x4.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}} ; SIMD128-NEXT: return $pop[[R]]{{$}}
define <4 x i1> @compare_ueq_nnan_v4f32 (<4 x float> %x, <4 x float> %y) { define <4 x i1> @compare_ueq_nnan_v4f32 (<4 x float> %x, <4 x float> %y) {
%res = fcmp nnan ueq <4 x float> %x, %y %res = fcmp nnan ueq <4 x float> %x, %y
ret <4 x i1> %res ret <4 x i1> %res
} }
; CHECK-LABEL: compare_sext_ueq_v4f32: ; CHECK-LABEL: compare_sext_ueq_v4f32:
; NO-SIMD128-NOT: f32x4 ; NO-SIMD128-NOT: f32x4
; SIMD128-NEXT: .functype compare_sext_ueq_v4f32 (v128, v128) -> (v128){{$}} ; SIMD128-NEXT: .functype compare_sext_ueq_v4f32 (v128, v128) -> (v128){{$}}
; SIMD128-NEXT: f32x4.eq $push[[T0:[0-9]+]]=, $0, $1{{$}} ; SIMD128-NEXT: f32x4.gt $push[[T0:[0-9]+]]=, $0, $1{{$}}
; SIMD128-NEXT: f32x4.ne $push[[T1:[0-9]+]]=, $0, $0{{$}} ; SIMD128-NEXT: f32x4.lt $push[[T1:[0-9]+]]=, $0, $1{{$}}
; SIMD128-NEXT: f32x4.ne $push[[T2:[0-9]+]]=, $1, $1{{$}} ; SIMD128-NEXT: v128.or $push[[T2:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
; SIMD128-NEXT: v128.or $push[[T3:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}} ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T2]]{{$}}
; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T3]]{{$}}
; SIMD128-NEXT: return $pop[[R]] ; SIMD128-NEXT: return $pop[[R]]
define <4 x i32> @compare_sext_ueq_v4f32 (<4 x float> %x, <4 x float> %y) { define <4 x i32> @compare_sext_ueq_v4f32 (<4 x float> %x, <4 x float> %y) {
%cmp = fcmp ueq <4 x float> %x, %y %cmp = fcmp ueq <4 x float> %x, %y
%res = sext <4 x i1> %cmp to <4 x i32> %res = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %res ret <4 x i32> %res
} }
; CHECK-LABEL: compare_sext_ueq_nnan_v4f32: ; CHECK-LABEL: compare_sext_ueq_nnan_v4f32:
▲ Show 20 Lines • Show All 483 Lines • ▼ Show 20 Linesdefine <2 x i64> @compare_sext_ole_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
%cmp = fcmp nnan ole <2 x double> %x, %y %cmp = fcmp nnan ole <2 x double> %x, %y
%res = sext <2 x i1> %cmp to <2 x i64> %res = sext <2 x i1> %cmp to <2 x i64>
ret <2 x i64> %res ret <2 x i64> %res
} }
; CHECK-LABEL: compare_one_v2f64: ; CHECK-LABEL: compare_one_v2f64:
; NO-SIMD128-NOT: f64x2 ; NO-SIMD128-NOT: f64x2
; SIMD128-NEXT: .functype compare_one_v2f64 (v128, v128) -> (v128){{$}} ; SIMD128-NEXT: .functype compare_one_v2f64 (v128, v128) -> (v128){{$}}
; SIMD128-NEXT: f64x2.ne $push[[T0:[0-9]+]]=, $0, $1{{$}} ; SIMD128-NEXT: f64x2.gt $push[[T0:[0-9]+]]=, $0, $1{{$}}
; SIMD128-NEXT: f64x2.eq $push[[T1:[0-9]+]]=, $0, $0{{$}} ; SIMD128-NEXT: f64x2.lt $push[[T1:[0-9]+]]=, $0, $1{{$}}
; SIMD128-NEXT: f64x2.eq $push[[T2:[0-9]+]]=, $1, $1{{$}} ; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
; SIMD128-NEXT: v128.and $push[[T3:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T3]]{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}} ; SIMD128-NEXT: return $pop[[R]]{{$}}
define <2 x i1> @compare_one_v2f64 (<2 x double> %x, <2 x double> %y) { define <2 x i1> @compare_one_v2f64 (<2 x double> %x, <2 x double> %y) {
%res = fcmp one <2 x double> %x, %y %res = fcmp one <2 x double> %x, %y
ret <2 x i1> %res ret <2 x i1> %res
} }
; CHECK-LABEL: compare_one_nnan_v2f64: ; CHECK-LABEL: compare_one_nnan_v2f64:
; NO-SIMD128-NOT: f64x2 ; NO-SIMD128-NOT: f64x2
; SIMD128-NEXT: .functype compare_one_nnan_v2f64 (v128, v128) -> (v128){{$}} ; SIMD128-NEXT: .functype compare_one_nnan_v2f64 (v128, v128) -> (v128){{$}}
; SIMD128-NEXT: f64x2.ne $push[[R:[0-9]+]]=, $0, $1{{$}} ; SIMD128-NEXT: f64x2.ne $push[[R:[0-9]+]]=, $0, $1{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}} ; SIMD128-NEXT: return $pop[[R]]{{$}}
define <2 x i1> @compare_one_nnan_v2f64 (<2 x double> %x, <2 x double> %y) { define <2 x i1> @compare_one_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
%res = fcmp nnan one <2 x double> %x, %y %res = fcmp nnan one <2 x double> %x, %y
ret <2 x i1> %res ret <2 x i1> %res
} }
; CHECK-LABEL: compare_sext_one_v2f64: ; CHECK-LABEL: compare_sext_one_v2f64:
; NO-SIMD128-NOT: f64x2 ; NO-SIMD128-NOT: f64x2
; SIMD128-NEXT: .functype compare_sext_one_v2f64 (v128, v128) -> (v128){{$}} ; SIMD128-NEXT: .functype compare_sext_one_v2f64 (v128, v128) -> (v128){{$}}
; SIMD128-NEXT: f64x2.ne $push[[T0:[0-9]+]]=, $0, $1{{$}} ; SIMD128-NEXT: f64x2.gt $push[[T0:[0-9]+]]=, $0, $1{{$}}
; SIMD128-NEXT: f64x2.eq $push[[T1:[0-9]+]]=, $0, $0{{$}} ; SIMD128-NEXT: f64x2.lt $push[[T1:[0-9]+]]=, $0, $1{{$}}
; SIMD128-NEXT: f64x2.eq $push[[T2:[0-9]+]]=, $1, $1{{$}} ; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
; SIMD128-NEXT: v128.and $push[[T3:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}}
; SIMD128-NEXT: v128.and $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T3]]{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}} ; SIMD128-NEXT: return $pop[[R]]{{$}}
define <2 x i64> @compare_sext_one_v2f64 (<2 x double> %x, <2 x double> %y) { define <2 x i64> @compare_sext_one_v2f64 (<2 x double> %x, <2 x double> %y) {
%cmp = fcmp one <2 x double> %x, %y %cmp = fcmp one <2 x double> %x, %y
%res = sext <2 x i1> %cmp to <2 x i64> %res = sext <2 x i1> %cmp to <2 x i64>
ret <2 x i64> %res ret <2 x i64> %res
} }
; CHECK-LABEL: compare_sext_one_nnan_v2f64: ; CHECK-LABEL: compare_sext_one_nnan_v2f64:
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Linesdefine <2 x i64> @compare_sext_ord_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
%cmp = fcmp nnan ord <2 x double> %x, %y %cmp = fcmp nnan ord <2 x double> %x, %y
%res = sext <2 x i1> %cmp to <2 x i64> %res = sext <2 x i1> %cmp to <2 x i64>
ret <2 x i64> %res ret <2 x i64> %res
} }
; CHECK-LABEL: compare_ueq_v2f64: ; CHECK-LABEL: compare_ueq_v2f64:
; NO-SIMD128-NOT: f64x2 ; NO-SIMD128-NOT: f64x2
; SIMD128-NEXT: .functype compare_ueq_v2f64 (v128, v128) -> (v128){{$}} ; SIMD128-NEXT: .functype compare_ueq_v2f64 (v128, v128) -> (v128){{$}}
; SIMD128-NEXT: f64x2.eq $push[[T0:[0-9]+]]=, $0, $1{{$}} ; SIMD128-NEXT: f64x2.gt $push[[T0:[0-9]+]]=, $0, $1{{$}}
; SIMD128-NEXT: f64x2.ne $push[[T1:[0-9]+]]=, $0, $0{{$}} ; SIMD128-NEXT: f64x2.lt $push[[T1:[0-9]+]]=, $0, $1{{$}}
; SIMD128-NEXT: f64x2.ne $push[[T2:[0-9]+]]=, $1, $1{{$}} ; SIMD128-NEXT: v128.or $push[[T2:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
; SIMD128-NEXT: v128.or $push[[T3:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}} ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T2]]{{$}}
; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T3]]{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}} ; SIMD128-NEXT: return $pop[[R]]{{$}}
define <2 x i1> @compare_ueq_v2f64 (<2 x double> %x, <2 x double> %y) { define <2 x i1> @compare_ueq_v2f64 (<2 x double> %x, <2 x double> %y) {
%res = fcmp ueq <2 x double> %x, %y %res = fcmp ueq <2 x double> %x, %y
ret <2 x i1> %res ret <2 x i1> %res
} }
; CHECK-LABEL: compare_ueq_nnan_v2f64: ; CHECK-LABEL: compare_ueq_nnan_v2f64:
; NO-SIMD128-NOT: f64x2 ; NO-SIMD128-NOT: f64x2
; SIMD128-NEXT: .functype compare_ueq_nnan_v2f64 (v128, v128) -> (v128){{$}} ; SIMD128-NEXT: .functype compare_ueq_nnan_v2f64 (v128, v128) -> (v128){{$}}
; SIMD128-NEXT: f64x2.eq $push[[R:[0-9]+]]=, $0, $1{{$}} ; SIMD128-NEXT: f64x2.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}} ; SIMD128-NEXT: return $pop[[R]]{{$}}
define <2 x i1> @compare_ueq_nnan_v2f64 (<2 x double> %x, <2 x double> %y) { define <2 x i1> @compare_ueq_nnan_v2f64 (<2 x double> %x, <2 x double> %y) {
%res = fcmp nnan ueq <2 x double> %x, %y %res = fcmp nnan ueq <2 x double> %x, %y
ret <2 x i1> %res ret <2 x i1> %res
} }
; CHECK-LABEL: compare_sext_ueq_v2f64: ; CHECK-LABEL: compare_sext_ueq_v2f64:
; NO-SIMD128-NOT: f64x2 ; NO-SIMD128-NOT: f64x2
; SIMD128-NEXT: .functype compare_sext_ueq_v2f64 (v128, v128) -> (v128){{$}} ; SIMD128-NEXT: .functype compare_sext_ueq_v2f64 (v128, v128) -> (v128){{$}}
; SIMD128-NEXT: f64x2.eq $push[[T0:[0-9]+]]=, $0, $1{{$}} ; SIMD128-NEXT: f64x2.gt $push[[T0:[0-9]+]]=, $0, $1{{$}}
; SIMD128-NEXT: f64x2.ne $push[[T1:[0-9]+]]=, $0, $0{{$}} ; SIMD128-NEXT: f64x2.lt $push[[T1:[0-9]+]]=, $0, $1{{$}}
; SIMD128-NEXT: f64x2.ne $push[[T2:[0-9]+]]=, $1, $1{{$}} ; SIMD128-NEXT: v128.or $push[[T2:[0-9]+]]=, $pop[[T0]], $pop[[T1]]{{$}}
; SIMD128-NEXT: v128.or $push[[T3:[0-9]+]]=, $pop[[T1]], $pop[[T2]]{{$}} ; SIMD128-NEXT: v128.not $push[[R:[0-9]+]]=, $pop[[T2]]{{$}}
; SIMD128-NEXT: v128.or $push[[R:[0-9]+]]=, $pop[[T0]], $pop[[T3]]{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}} ; SIMD128-NEXT: return $pop[[R]]{{$}}
define <2 x i64> @compare_sext_ueq_v2f64 (<2 x double> %x, <2 x double> %y) { define <2 x i64> @compare_sext_ueq_v2f64 (<2 x double> %x, <2 x double> %y) {
%cmp = fcmp ueq <2 x double> %x, %y %cmp = fcmp ueq <2 x double> %x, %y
%res = sext <2 x i1> %cmp to <2 x i64> %res = sext <2 x i1> %cmp to <2 x i64>
ret <2 x i64> %res ret <2 x i64> %res
} }
; CHECK-LABEL: compare_sext_ueq_nnan_v2f64: ; CHECK-LABEL: compare_sext_ueq_nnan_v2f64:
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