[ARM] Add uses for locals introduced for debug messages. NFC.

[herhut]

Summary

This adds uses for locals introduced for new debug messages for the load store optimizer. Those locals are only used on debug statements and otherwise create unused variable warnings.

[dmgreen]

Oh yeah. Sorry. Forgot about that.

LGTM. Thanks for the fix.

llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

if (isAM5) {
     auto MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc))
                    .addReg(Base, getDefRegState(true)) // WB base register
                    .addReg(Base, getKillRegState(isLd ? BaseKill : false))
                    .addImm(Pred)
                    .addReg(PredReg)
                    .addReg(MO.getReg(), (isLd ? getDefRegState(true)
                                               : getKillRegState(MO.isKill())))
                    .cloneMemRefs(*MI);
+    (void)MIB;
     LLVM_DEBUG(dbgs() << "  Added new instruction: " << *MIB);
   } else if (isLd) {
     if (isAM2) {
       // LDR_PRE, LDR_POST
       if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) {
         auto MIB =
             BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
                 .addReg(Base, RegState::Define)
                 .addReg(Base)
                 .addImm(Offset)
                 .addImm(Pred)
                 .addReg(PredReg)
                 .cloneMemRefs(*MI);
+        (void)MIB;
         LLVM_DEBUG(dbgs() << "  Added new instruction: " << *MIB);
       } else {
         int Imm = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift);
         auto MIB =
             BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
                 .addReg(Base, RegState::Define)
                 .addReg(Base)
                 .addReg(0)
                 .addImm(Imm)
                 .add(predOps(Pred, PredReg))
                 .cloneMemRefs(*MI);
+        (void)MIB;
         LLVM_DEBUG(dbgs() << "  Added new instruction: " << *MIB);
       }
     } else {
       // t2LDR_PRE, t2LDR_POST
       auto MIB =
           BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
               .addReg(Base, RegState::Define)
               .addReg(Base)
               .addImm(Offset)
               .add(predOps(Pred, PredReg))
               .cloneMemRefs(*MI);
+      (void)MIB;
       LLVM_DEBUG(dbgs() << "  Added new instruction: " << *MIB);
     }
   } else {
     MachineOperand &MO = MI->getOperand(0);
     // FIXME: post-indexed stores use am2offset_imm, which still encodes
     // the vestigal zero-reg offset register. When that's fixed, this clause
     // can be removed entirely.
     if (isAM2 && NewOpc == ARM::STR_POST_IMM) {
       int Imm = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift);
       // STR_PRE, STR_POST
       auto MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc), Base)
                      .addReg(MO.getReg(), getKillRegState(MO.isKill()))
                      .addReg(Base)
                      .addReg(0)
                      .addImm(Imm)
                      .add(predOps(Pred, PredReg))
                      .cloneMemRefs(*MI);
+      (void)MIB;
       LLVM_DEBUG(dbgs() << "  Added new instruction: " << *MIB);
     } else {
       // t2STR_PRE, t2STR_POST
       auto MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc), Base)
                      .addReg(MO.getReg(), getKillRegState(MO.isKill()))
                      .addReg(Base)
                      .addImm(Offset)
                      .add(predOps(Pred, PredReg))
                      .cloneMemRefs(*MI);
+      (void)MIB;
       LLVM_DEBUG(dbgs() << "  Added new instruction: " << *MIB);
     }
   }
   MBB.erase(MBBI);
 
   return true;
 }