diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td
--- a/llvm/lib/Target/X86/X86InstrInfo.td
+++ b/llvm/lib/Target/X86/X86InstrInfo.td
@@ -2924,6 +2924,34 @@
 def : InstAlias<"clzero\t{%eax|eax}", (CLZERO32r)>, Requires<[Not64BitMode]>;
 def : InstAlias<"clzero\t{%rax|rax}", (CLZERO64r)>, Requires<[In64BitMode]>;
 
+//===----------------------------------------------------------------------===//
+// INVLPGB Instruction
+// OPCODE 0F 01 FE
+//
+let SchedRW = [WriteSystem] in {
+  let Uses = [EAX, EDX] in
+  def INVLPGB32 : I<0x01, MRM_FE, (outs), (ins),
+                  "invlpgb}", []>,
+                  PS, Requires<[Not64BitMode]>;
+  let Uses = [RAX, EDX] in
+  def INVLPGB64 : I<0x01, MRM_FE, (outs), (ins),
+                  "invlpgb", []>,
+                  PS, Requires<[In64BitMode]>;
+} // SchedRW
+
+def : InstAlias<"invlpgb\t{%eax, %edx|eax, edx}", (INVLPGB32)>, Requires<[Not64BitMode]>;
+def : InstAlias<"invlpgb\t{%rax, %edx|rax, edx}", (INVLPGB64)>, Requires<[In64BitMode]>;
+
+//===----------------------------------------------------------------------===//
+// TLBSYNC Instruction
+// OPCODE 0F 01 FF
+//
+let SchedRW = [WriteSystem] in {
+  def TLBSYNC   : I<0x01, MRM_FF, (outs), (ins),
+                  "tlbsync", []>,
+                  PS, Requires<[]>;
+} // SchedRW
+
 //===----------------------------------------------------------------------===//
 // HRESET Instruction
 //
@@ -3126,6 +3154,7 @@
 
 include "X86InstrVMX.td"
 include "X86InstrSVM.td"
+include "X86InstrSNP.td"
 
 include "X86InstrTSX.td"
 include "X86InstrSGX.td"
diff --git a/llvm/lib/Target/X86/X86InstrSNP.td b/llvm/lib/Target/X86/X86InstrSNP.td
new file mode 100644
--- /dev/null
+++ b/llvm/lib/Target/X86/X86InstrSNP.td
@@ -0,0 +1,47 @@
+//===-- X86InstrSNP.td - SNP Instruction Set Extension -----*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the instructions that make up the AMD Secure Nested
+// Paging (SNP) instruction set.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// SNP instructions
+
+let SchedRW = [WriteSystem] in {
+// F3 0F 01 FF
+let Uses = [RAX] in
+def PSMASH: I<0x01, MRM_FF, (outs), (ins), "psmash", []>, XS,
+            Requires<[In64BitMode]>;
+
+// F2 0F 01 FF
+let Uses = [RAX] in
+def PVALIDATE64: I<0x01, MRM_FF, (outs), (ins), "pvalidate",[]>,
+                 XD, Requires<[In64BitMode]>;
+
+let Uses = [EAX] in
+def PVALIDATE32: I<0x01, MRM_FF, (outs), (ins), "pvalidate",[]>,
+                 XD, Requires<[Not64BitMode]>;
+
+// F2 0F 01 FE
+let Uses = [RAX] in
+def RMPUPDATE: I<0x01, MRM_FE, (outs), (ins), "rmpupdate", []>, XD,
+               Requires<[In64BitMode]>;
+
+// F3 0F 01 FE
+let Uses = [RAX] in
+def RMPADJUST: I<0x01, MRM_FE, (outs), (ins), "rmpadjust", []>, XS,
+               Requires<[In64BitMode]>;
+} // SchedRW
+
+def : InstAlias<"psmash\t{%rax|rax}", (PSMASH)>, Requires<[In64BitMode]>;
+def : InstAlias<"pvalidate\t{%rax|rax}", (PVALIDATE64)>, Requires<[In64BitMode]>;
+def : InstAlias<"pvalidate\t{%eax|eax}", (PVALIDATE32)>, Requires<[Not64BitMode]>;
+def : InstAlias<"rmpupdate\t{%rax|rax}", (RMPUPDATE)>, Requires<[In64BitMode]>;
+def : InstAlias<"rmpadjust\t{%rax|rax}", (RMPADJUST)>, Requires<[In64BitMode]>;
diff --git a/llvm/test/MC/Disassembler/X86/x86-32.txt b/llvm/test/MC/Disassembler/X86/x86-32.txt
--- a/llvm/test/MC/Disassembler/X86/x86-32.txt
+++ b/llvm/test/MC/Disassembler/X86/x86-32.txt
@@ -177,6 +177,12 @@
 # CHECK: clzero
 0x0f,0x01,0xfc
 
+# CHECK: tlbsync
+0x0f,0x01,0xff
+
+# CHECK: invlpgb
+0x0f,0x01,0xfe
+
 # CHECK: movl $0, -4(%ebp)
 0xc7 0x45 0xfc 0x00 0x00 0x00 0x00
 
@@ -1001,6 +1007,9 @@
 # CHECK: xresldtrk
 0xf2 0x0f 0x01 0xe9
 
+# CHECK: pvalidate
+0xf2 0x0f 0x01 0xff
+
 #CHECK: tdcall
 0x66 0x0f 0x01 0xcc
 
diff --git a/llvm/test/MC/Disassembler/X86/x86-64.txt b/llvm/test/MC/Disassembler/X86/x86-64.txt
--- a/llvm/test/MC/Disassembler/X86/x86-64.txt
+++ b/llvm/test/MC/Disassembler/X86/x86-64.txt
@@ -728,6 +728,18 @@
 # CHECK: stui
 0xf3,0x0f,0x01,0xef
 
+# CHECK: psmash
+0xf3 0x0f 0x01 0xff
+
+# CHECK: pvalidate
+0xf2 0x0f 0x01 0xff
+
+# CHECK: rmpupdate
+0xf2 0x0f 0x01 0xfe
+
+# CHECK: rmpadjust
+0xf3 0x0f 0x01 0xfe
+
 # CHECK: testui
 0xf3,0x0f,0x01,0xed
 
diff --git a/llvm/test/MC/X86/SNP-32.s b/llvm/test/MC/X86/SNP-32.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/X86/SNP-32.s
@@ -0,0 +1,9 @@
+// RUN: llvm-mc -triple i386-unknown-unknown --show-encoding %s | FileCheck %s
+
+// CHECK: pvalidate
+// CHECK: encoding: [0xf2,0x0f,0x01,0xff]
+pvalidate
+
+// CHECK: pvalidate
+// CHECK: encoding: [0xf2,0x0f,0x01,0xff]
+pvalidate	%eax
diff --git a/llvm/test/MC/X86/SNP-64.s b/llvm/test/MC/X86/SNP-64.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/X86/SNP-64.s
@@ -0,0 +1,33 @@
+// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
+
+// CHECK: rmpupdate
+// CHECK: encoding: [0xf2,0x0f,0x01,0xfe]
+rmpupdate
+
+// CHECK: psmash
+// CHECK: encoding: [0xf3,0x0f,0x01,0xff]
+psmash
+
+// CHECK: pvalidate
+// CHECK: encoding: [0xf2,0x0f,0x01,0xff]
+pvalidate
+
+// CHECK: rmpadjust
+// CHECK: encoding: [0xf3,0x0f,0x01,0xfe]
+rmpadjust
+
+// CHECK: rmpupdate
+// CHECK: encoding: [0xf2,0x0f,0x01,0xfe]
+rmpupdate %rax
+
+// CHECK: psmash
+// CHECK: encoding: [0xf3,0x0f,0x01,0xff]
+psmash %rax
+
+// CHECK: pvalidate
+// CHECK: encoding: [0xf2,0x0f,0x01,0xff]
+pvalidate %rax
+
+// CHECK: rmpadjust
+// CHECK: encoding: [0xf3,0x0f,0x01,0xfe]
+rmpadjust %rax
diff --git a/llvm/test/MC/X86/x86-32-coverage.s b/llvm/test/MC/X86/x86-32-coverage.s
--- a/llvm/test/MC/X86/x86-32-coverage.s
+++ b/llvm/test/MC/X86/x86-32-coverage.s
@@ -10744,6 +10744,14 @@
 // CHECK:  encoding: [0x0f,0x01,0xfc]
         	clzero
 
+// CHECK: 	tlbsync	
+// CHECK:  encoding: [0x0f,0x01,0xff]
+        	tlbsync
+
+// CHECK: 	invlpgb
+// CHECK:  encoding: [0x0f,0x01,0xfe]
+        	invlpgb %eax, %edx 
+
 // CHECK: lock addl %esi, (%edi)
 // INTEL: lock add dword ptr [edi], esi
 // CHECK:  encoding: [0xf0,0x01,0x37]
diff --git a/llvm/test/MC/X86/x86-32.s b/llvm/test/MC/X86/x86-32.s
--- a/llvm/test/MC/X86/x86-32.s
+++ b/llvm/test/MC/X86/x86-32.s
@@ -452,6 +452,14 @@
 // CHECK:  encoding: [0x0f,0x01,0xfc]
                 clzero %eax
 
+// CHECK:       tlbsync 
+// CHECK:  encoding: [0x0f,0x01,0xff]
+                tlbsync
+
+// CHECK:       invlpgb
+// CHECK:  encoding: [0x0f,0x01,0xfe]
+                invlpgb %eax, %edx
+
 // radr://8017522
 // CHECK: wait
 // CHECK:  encoding: [0x9b]
diff --git a/llvm/test/MC/X86/x86-64.s b/llvm/test/MC/X86/x86-64.s
--- a/llvm/test/MC/X86/x86-64.s
+++ b/llvm/test/MC/X86/x86-64.s
@@ -1538,6 +1538,14 @@
 // CHECK:  encoding: [0x0f,0x01,0xfc]
                 clzero %rax
 
+// CHECK:       tlbsync 
+// CHECK:  encoding: [0x0f,0x01,0xff]
+                tlbsync
+
+// CHECK:       invlpgb
+// CHECK:  encoding: [0x0f,0x01,0xfe]
+                invlpgb %rax, %edx 
+
 // CHECK: 	movl %r15d, (%r15,%r15)
 // CHECK:  encoding: [0x47,0x89,0x3c,0x3f]
 movl %r15d, (%r15,%r15)