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[AArch64] Add a Machine Value Type for 8 consecutive registers
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Authored by labrinea on Jan 5 2021, 8:42 AM.

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Summary

This patch adds a MVT named i64x8 needed for lowering inline asssembly operands which materialize a sequence of eight general purpose registers.

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Event Timeline

labrinea created this revision.Jan 5 2021, 8:42 AM
labrinea requested review of this revision.Jan 5 2021, 8:42 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 5 2021, 8:42 AM
Matt added a subscriber: Matt.Jun 24 2021, 11:06 AM
labrinea updated this revision to Diff 355929.Jul 1 2021, 10:19 AM
labrinea retitled this revision from [AArch64] Add a Machine Value Type for aarch64_ls64. to [AArch64] Add a Machine Value Type for 64-byte long loads and stores..
labrinea edited the summary of this revision. (Show Details)
labrinea added a reviewer: momchil.velikov.
labrinea updated this revision to Diff 360212.Jul 20 2021, 11:06 AM

The only change from the last revision is that getTypeForEVT() now returns i512 for MVT::i64x8 instead of [8 x i64].

labrinea retitled this revision from [AArch64] Add a Machine Value Type for 64-byte long loads and stores. to [AArch64] Add a Machine Value Type for 8 consecutive registers.Jul 29 2021, 1:17 AM
labrinea added a reviewer: eli.friedman.
labrinea edited reviewers, added: efriedma; removed: eli.friedman.Jul 29 2021, 3:09 PM
efriedma accepted this revision.Jul 30 2021, 2:31 PM

LGTM.

It's a little unfortunate we need a dedicated valuetype just for usage in inline asm, but I don't see a good alternative; at least, not without substantially rewriting the inline asm handling.

This revision is now accepted and ready to land.Jul 30 2021, 2:31 PM
This revision was landed with ongoing or failed builds.Jul 31 2021, 1:53 AM
This revision was automatically updated to reflect the committed changes.