[PowerPC] Expand BitPermutation to handle cases of the single immediate 'and'.

[Esme]

Summary

We have an overall procedure, the BitPermutation, to optimize ROTL, SHL, SRL, AND and OR. It builds up a list of collected and sorted bit groups and then ISel the entire permutation using a combination of masked rotations.

Currently BitPermutation excludes the input of a single immediate 'and', which will be transformed later through analyzing the patterns, ie. handled by the tryAs__() functions. However these patterns can only cover some specific cases, and for some other cases, BitPermutation can use fewer instructions for matching. Besides, I think it's reasonable to perform these transformations within BitPermutation since they have similar semantics with the BitPermutation.

This patch is trying to expand the BitPermutation to handle the case of single immediate 'and', therefore we can optimize more cases than the enumerated patterns.

[qiucf]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

1700

stratege -> strategy?

1714

Although it's nit, I believe it's better to remove +1 on both sides, and simply comment here that andc is needed for NumSelect case.

2119

Use if instead of else if? since each conditional block in this function always returns.

4517

This case "can't be handled by BitPerm" && "can't be handled by TableGen"?

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

public:
     }
 
 // Include the pieces autogenerated from the target description.
 #include "PPCGenDAGISel.inc"
 
 private:
     bool trySETCC(SDNode *N);
     bool tryAsSingleRLDICL(SDNode *N);
-    bool tryAsSingleRLDICR(SDNode *N);
-    bool tryAsSingleRLWINM(SDNode *N);
-    bool tryAsSingleRLWINM8(SDNode *N);
-    bool tryAsSingleRLWIMI(SDNode *N);
-    bool tryAsPairOfRLDICL(SDNode *N);
     bool tryAsSingleRLDIMI(SDNode *N);
 
     void PeepholePPC64();
     void PeepholePPC64ZExt();
     void PeepholeCROps();
 
     SDValue combineToCMPB(SDNode *N);
     void foldBoolExts(SDValue &Res, SDNode *&N);
case PPCISD::SRL:
         return std::make_pair(Interesting = true, &Bits);
       }
       break;
     case ISD::AND:
       if (isa<ConstantSDNode>(V.getOperand(1))) {
         uint64_t Mask = V.getConstantOperandVal(1);
 
         const SmallVector<ValueBit, 64> *LHSBits;
-        // Mark this as interesting, only if the LHS was also interesting. This
-        // prevents the overall procedure from matching a single immediate 'and'
-        // (which is non-optimal because such an and might be folded with other
-        // things if we don't select it here).
         std::tie(Interesting, LHSBits) = getValueBits(V.getOperand(0), NumBits);
 
         for (unsigned i = 0; i < NumBits; ++i)
           if (((Mask >> i) & 1) == 1)
             Bits[i] = (*LHSBits)[i];
           else {
             // AND instruction masks this bit. If the input is already zero,
             // we have nothing to do here. Otherwise, make the bit ConstZero.
             if ((*LHSBits)[i].isZero())
               Bits[i] = (*LHSBits)[i];
             else
               Bits[i] = ValueBit(ValueBit::ConstZero);
           }
-
-        return std::make_pair(Interesting, &Bits);
+        // If the LHS isn't interesting, we should take care whether it's
+        // optimal to handle such a single immediate `and` here. Record the 
+        // LHS of the `AND` instruction for later analyzing.
+        if (!Interesting)
+          LHSofSingleAnd = V.getOperand(0);
+        return std::make_pair(Interesting = true, &Bits);
       }
       break;
     case ISD::OR: {
       const auto &LHSBits = *getValueBits(V.getOperand(0), NumBits).second;
       const auto &RHSBits = *getValueBits(V.getOperand(1), NumBits).second;
 
       bool AllDisjoint = true;
       SDValue LastVal = SDValue();
for (unsigned i = 0; i < Bits.size(); ++i) {
       if (Bits[i].hasValue())
         continue;
       Mask |= (UINT64_C(1) << i);
     }
 
     return ~Mask;
   }
 
+  // This method checks if it's optimal to select the single `and` with
+  // bit-permutation-based stratege. Considering the cases where `and` can be
+  // folded with its LHS, determine which stratege use less instruction. Return
+  // true if bit-permutation-based stratege is optimal.
+  bool isBitPermOptimal(unsigned AndImm, unsigned NumSelectInsts,
+                        unsigned NumBitPermInsts) {
+    if (!LHSofSingleAnd)
+      return true;
+    switch (LHSofSingleAnd.getOpcode()) {
+    case ISD::XOR:
+      // Consider the transformation, and(not, AndImm) -> andc.
+      if (isa<ConstantSDNode>(LHSofSingleAnd.getOperand(1)) &&
+          cast<ConstantSDNode>(LHSofSingleAnd.getOperand(1))->getSExtValue() ==
+              -1)
+        // Compare which kind of conversion is better.
+        if ((NumBitPermInsts + /* xor */ 1) > (NumSelectInsts + /* andc */ 1))
+          return false;
+      break;
+    case ISD::ANY_EXTEND:
+      // and(any_extend(srl), AndImm) -> rldicl
+      if (isMask_64(AndImm) &&
+          LHSofSingleAnd.getOperand(0).getOpcode() == ISD::SRL)
+        return false;
+      break;
+    case ISD::ROTL:
+      // and(rotl, AndImm) -> rlwnm
+      if (isShiftedMask_32(AndImm) || isShiftedMask_32(~AndImm))
+        return false;
+      break;
+    }
+    return true;
+  }
+
   // This method extends an input value to 64 bit if input is 32-bit integer.
   // While selecting instructions in BitPermutationSelector in 64-bit mode,
   // an input value can be a 32-bit integer if a ZERO_EXTEND node is included.
   // In such case, we extend it to 64 bit to be consistent with other values.
   SDValue ExtendToInt64(SDValue V, const SDLoc &dl) {
     if (V.getValueSizeInBits() == 64)
       return V;
 
for (ValueRotInfo &VRI : ValueRotsVec) {
       // andi/andis in break-even cases.
 
       unsigned NumAndInsts = (unsigned) NeedsRotate +
                              (unsigned) (ANDIMask != 0) +
                              (unsigned) (ANDISMask != 0) +
                              (unsigned) (ANDIMask != 0 && ANDISMask != 0) +
                              (unsigned) (bool) Res;
 
+      unsigned NumSelectInsts = 0;
+      selectI64Imm(CurDAG, dl, Mask, &NumSelectInsts);
+      if (!isBitPermOptimal(Mask, NumSelectInsts,
+                            NumAndInsts < VRI.NumGroups ? NumAndInsts
+                                                        : VRI.NumGroups)) {
+        IsBitPermOptimal = false;
+        LLVM_DEBUG(dbgs() << "\t\t\t\tDon't use bit-permutation-based ISel.\n");
+        return;
+      }
+
       LLVM_DEBUG(dbgs() << "\t\trotation groups for " << VRI.V.getNode()
                         << " RL: " << VRI.RLAmt << ":"
                         << "\n\t\t\tisel using masking: " << NumAndInsts
                         << " using rotates: " << VRI.NumGroups << "\n");
 
       if (NumAndInsts >= VRI.NumGroups)
         continue;
 
class BitPermutationSelector {
   SDNode *Select32(SDNode *N, bool LateMask, unsigned *InstCnt) {
     SDLoc dl(N);
     SDValue Res;
 
     if (InstCnt) *InstCnt = 0;
 
     // Take care of cases that should use andi/andis first.
     SelectAndParts32(dl, Res, InstCnt);
+    // Check if it's optimal to handle the input instructions with
+    // bit-permutation-based ISel.
+    if (!IsBitPermOptimal)
+      return nullptr;
 
     // If we've not yet selected a 'starting' instruction, and we have no zeros
     // to fill in, select the (Value, RLAmt) with the highest priority (largest
     // number of groups), and start with this rotated value.
     if ((!NeedMask || LateMask) && !Res) {
       ValueRotInfo &VRI = ValueRotsVec[0];
       if (VRI.RLAmt) {
         if (InstCnt) *InstCnt += 1;
unsigned SelectRotMask64Count(unsigned RLAmt, bool Repl32,
     // because bits are counted from high to low order.
     unsigned InstMaskStart = 64 - MaskEnd - 1,
              InstMaskEnd   = 64 - MaskStart - 1;
 
     if (Repl32)
       return 1;
 
     if ((!IsIns && (InstMaskEnd == 63 || InstMaskStart == 0)) ||
-        InstMaskEnd == 63 - RLAmt)
+        InstMaskEnd == 63 - RLAmt ||
+        (InstMaskStart >= 32 && InstMaskStart <= InstMaskEnd))
       return 1;
 
     return 2;
   }
 
   // For 64-bit values, not all combinations of rotates and masks are
   // available. Produce one if it is available.
   SDValue SelectRotMask64(SDValue V, const SDLoc &dl, unsigned RLAmt,
SDValue SelectRotMask64(SDValue V, const SDLoc &dl, unsigned RLAmt,
 
     if (InstMaskEnd == 63 - RLAmt) {
       SDValue Ops[] =
         { ExtendToInt64(V, dl), getI32Imm(RLAmt, dl),
           getI32Imm(InstMaskStart, dl) };
       return SDValue(CurDAG->getMachineNode(PPC::RLDIC, dl, MVT::i64, Ops), 0);
     }
 
+    if (InstMaskStart >= 32 && InstMaskStart <= InstMaskEnd) {
+      SDValue Ops[] = {ExtendToInt64(V, dl), getI32Imm(RLAmt, dl),
+                       getI32Imm(InstMaskStart - 32, dl),
+                       getI32Imm(InstMaskEnd - 32, dl)};
+      return SDValue(CurDAG->getMachineNode(PPC::RLWINM8, dl, MVT::i64, Ops),
+                     0);
+    }
+
     // We cannot do this with a single instruction, so we'll use two. The
     // problem is that we're not free to choose both a rotation amount and mask
     // start and end independently. We can choose an arbitrary mask start and
     // end, but then the rotation amount is fixed. Rotation, however, can be
     // inverted, and so by applying an "inverse" rotation first, we can get the
     // desired result.
     if (InstCnt) *InstCnt += 1;
 
SDValue SelectRotMaskIns64(SDValue Base, SDValue V, const SDLoc &dl,
     // The first instruction must rotate V so that the overall rotation amount
     // is RLAmt.
     unsigned RLAmt1 = (64 + RLAmt - RLAmt2) % 64;
     if (RLAmt1)
       V = SelectRotMask64(V, dl, RLAmt1, false, 0, 63);
     return SelectRotMaskIns64(Base, V, dl, RLAmt2, false, MaskStart, MaskEnd);
   }
 
+  SDValue tryAsPairRot(BitGroup BG1, BitGroup BG2, const SDLoc &dl) {
+    if (BG1.RLAmt || BG2.RLAmt || BG1.StartIdx >= BG1.EndIdx ||
+        BG2.StartIdx >= BG2.EndIdx || BG1.EndIdx >= BG2.StartIdx)
+      return SDValue();
+    SDValue RotVal;
+    // RLDICL + RLDICL
+    if (BG1.StartIdx == 0) {
+      SDValue Ops1[] = {ExtendToInt64(BG1.V, dl),
+                        getI32Imm(64 - BG2.StartIdx, dl),
+                        getI32Imm(BG2.StartIdx - BG1.EndIdx - 1, dl)};
+      RotVal =
+          SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Ops1), 0);
+      SDValue Ops2[] = {ExtendToInt64(RotVal, dl), getI32Imm(BG2.StartIdx, dl),
+                        getI32Imm(63 - BG2.EndIdx, dl)};
+      return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Ops2),
+                     0);
+    }
+    // RLDICL + RLDICR
+    else if (BG2.EndIdx == 63) {
+      SDValue Ops1[] = {ExtendToInt64(BG1.V, dl),
+                        getI32Imm(64 - BG2.StartIdx, dl),
+                        getI32Imm(BG2.StartIdx - BG1.EndIdx - 1, dl)};
+      RotVal =
+          SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Ops1), 0);
+      SDValue Ops2[] = {ExtendToInt64(RotVal, dl), getI32Imm(BG2.StartIdx, dl),
+                        getI32Imm(63 - BG1.StartIdx, dl)};
+      return SDValue(CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, Ops2),
+                     0);
+    }
+    // RLWINM + RLWINM
+    else if (BG2.EndIdx < 32) {
+      SDValue Ops1[] = {ExtendToInt64(BG1.V, dl), getI32Imm(0, dl),
+                        getI32Imm(31 - BG1.EndIdx, dl),
+                        getI32Imm(31 - BG2.StartIdx, dl)};
+      RotVal =
+          SDValue(CurDAG->getMachineNode(PPC::RLWINM8, dl, MVT::i64, Ops1), 0);
+      SDValue Ops2[] = {ExtendToInt64(RotVal, dl), getI32Imm(0, dl),
+                        getI32Imm(31 - BG2.EndIdx, dl),
+                        getI32Imm(31 - BG1.StartIdx, dl)};
+      return SDValue(CurDAG->getMachineNode(PPC::RLWINM8, dl, MVT::i64, Ops2),
+                     0);
+    }
+    return SDValue();
+  }
+
   void SelectAndParts64(const SDLoc &dl, SDValue &Res, unsigned *InstCnt) {
     if (BPermRewriterNoMasking)
       return;
 
     // The idea here is the same as in the 32-bit version, but with additional
     // complications from the fact that Repl32 might be true. Because we
     // aggressively convert bit groups to Repl32 form (which, for small
     // rotation factors, involves no other change), and then coalesce, it might
     // be the case that a single 64-bit masking operation could handle both
     // some Repl32 groups and some non-Repl32 groups. If converting to Repl32
     // form allowed coalescing, then we must use a 32-bit rotaton in order to
     // completely capture the new combined bit group.
 
     for (ValueRotInfo &VRI : ValueRotsVec) {
       uint64_t Mask = 0;
+      SmallVector<BitGroup, 16> MatchingBitGroups;
 
       // We need to add to the mask all bits from the associated bit groups.
       // If Repl32 is false, we need to add bits from bit groups that have
       // Repl32 true, but are trivially convertable to Repl32 false. Such a
       // group is trivially convertable if it overlaps only with the lower 32
       // bits, and the group has not been coalesced.
       auto MatchingBG = [VRI](const BitGroup &BG) {
         if (VRI.V != BG.V)
for (ValueRotInfo &VRI : ValueRotsVec) {
 
         return VRI.RLAmt == EffRLAmt;
       };
 
       for (auto &BG : BitGroups) {
         if (!MatchingBG(BG))
           continue;
 
+        MatchingBitGroups.push_back(BG);
         if (BG.StartIdx <= BG.EndIdx) {
           for (unsigned i = BG.StartIdx; i <= BG.EndIdx; ++i)
             Mask |= (UINT64_C(1) << i);
         } else {
           for (unsigned i = BG.StartIdx; i < Bits.size(); ++i)
             Mask |= (UINT64_C(1) << i);
           for (unsigned i = 0; i <= BG.EndIdx; ++i)
             Mask |= (UINT64_C(1) << i);
for (ValueRotInfo &VRI : ValueRotsVec) {
           continue;
         }
         NumRLInsts +=
           SelectRotMask64Count(BG.RLAmt, BG.Repl32, BG.StartIdx, BG.EndIdx,
                                !FirstBG);
         FirstBG = false;
       }
 
+      // Take care of cases that should select a pair of bit groups directly
+      // with 2 instructions.
+      if (MatchingBitGroups.size() == 2 && NumAndInsts > 2) {
+        BitGroup BG1 = MatchingBitGroups[0], BG2 = MatchingBitGroups[1];
+        SDValue PairRotVal = tryAsPairRot(BG1, BG2, dl);
+        if (PairRotVal) {
+          if (InstCnt)
+            *InstCnt += 2;
+          if (!Res)
+            Res = PairRotVal;
+          else
+            Res =
+                SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
+                                               ExtendToInt64(Res, dl), PairRotVal),
+                        0);
+          // Now, remove all groups with this underlying value and rotation
+          // factor.
+          eraseMatchingBitGroups(MatchingBG);
+          continue;
+        }
+      }
+
+      if (!isBitPermOptimal(Mask, NumOfSelectInsts,
+                            NumAndInsts < NumRLInsts ? NumAndInsts
+                                                     : NumRLInsts)) {
+        IsBitPermOptimal = false;
+        LLVM_DEBUG(dbgs() << "\t\t\t\tDon't use bit-permutation-based ISel.\n");
+        return;
+      }
+
       LLVM_DEBUG(dbgs() << "\t\trotation groups for " << VRI.V.getNode()
                         << " RL: " << VRI.RLAmt << (VRI.Repl32 ? " (32):" : ":")
                         << "\n\t\t\tisel using masking: " << NumAndInsts
                         << " using rotates: " << NumRLInsts << "\n");
 
       // When we'd use andi/andis, we bias toward using the rotates (andi only
       // has a record form, and is cracked on POWER cores). However, when using
       // general 64-bit constant formation, bias toward the constant form,

   SDNode *Select64(SDNode *N, bool LateMask, unsigned *InstCnt) {
     SDLoc dl(N);
     SDValue Res;
 
     if (InstCnt) *InstCnt = 0;
 
     // Take care of cases that should use andi/andis first.
     SelectAndParts64(dl, Res, InstCnt);
+    // Check if it's optimal to handle the input instructions with
+    // bit-permutation-based ISel.
+    if (!IsBitPermOptimal)
+      return nullptr;
 
     // If we've not yet selected a 'starting' instruction, and we have no zeros
     // to fill in, select the (Value, RLAmt) with the highest priority (largest
     // number of groups), and start with this rotated value.
     if ((!NeedMask || LateMask) && !Res) {
       // If we have both Repl32 groups and non-Repl32 groups, the non-Repl32
       // groups will come first, and so the VRI representing the largest number
       // of groups might not be first (it might be the first Repl32 groups).

 
   void eraseMatchingBitGroups(function_ref<bool(const BitGroup &)> F) {
     erase_if(BitGroups, F);
   }
 
   SmallVector<ValueBit, 64> Bits;
 
   bool NeedMask = false;
+  bool IsBitPermOptimal = true;
+  SDValue LHSofSingleAnd;
   SmallVector<unsigned, 64> RLAmt;
 
   SmallVector<BitGroup, 16> BitGroups;
 
   DenseMap<std::pair<SDValue, unsigned>, ValueRotInfo> ValueRots;
   SmallVector<ValueRotInfo, 16> ValueRotsVec;
 
   SelectionDAG *CurDAG = nullptr;
static bool mayUseP9Setb(SDNode *N, const ISD::CondCode &CC, SelectionDAG *DAG,
   }
 
   LLVM_DEBUG(dbgs() << "Found a node that can be lowered to a SETB: ");
   LLVM_DEBUG(N->dump());
 
   return true;
 }
 
-bool PPCDAGToDAGISel::tryAsSingleRLWINM(SDNode *N) {
-  assert(N->getOpcode() == ISD::AND && "ISD::AND SDNode expected");
-  unsigned Imm;
-  if (!isInt32Immediate(N->getOperand(1), Imm))
-    return false;
-
-  SDLoc dl(N);
-  SDValue Val = N->getOperand(0);
-  unsigned SH, MB, ME;
-  // If this is an and of a value rotated between 0 and 31 bits and then and'd
-  // with a mask, emit rlwinm
-  if (isRotateAndMask(Val.getNode(), Imm, false, SH, MB, ME)) {
-    Val = Val.getOperand(0);
-    SDValue Ops[] = {Val, getI32Imm(SH, dl), getI32Imm(MB, dl),
-                     getI32Imm(ME, dl)};
-    CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
-    return true;
-  }
-
-  // If this is just a masked value where the input is not handled, and
-  // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
-  if (isRunOfOnes(Imm, MB, ME) && Val.getOpcode() != ISD::ROTL) {
-    SDValue Ops[] = {Val, getI32Imm(0, dl), getI32Imm(MB, dl),
-                     getI32Imm(ME, dl)};
-    CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
-    return true;
-  }
-
-  // AND X, 0 -> 0, not "rlwinm 32".
-  if (Imm == 0) {
-    ReplaceUses(SDValue(N, 0), N->getOperand(1));
-    return true;
-  }
-
-  return false;
-}
-
-bool PPCDAGToDAGISel::tryAsSingleRLWINM8(SDNode *N) {
-  assert(N->getOpcode() == ISD::AND && "ISD::AND SDNode expected");
-  uint64_t Imm64;
-  if (!isInt64Immediate(N->getOperand(1).getNode(), Imm64))
-    return false;
-
-  unsigned MB, ME;
-  if (isRunOfOnes64(Imm64, MB, ME) && MB >= 32 && MB <= ME) {
-    //                MB  ME
-    // +----------------------+
-    // |xxxxxxxxxxx00011111000|
-    // +----------------------+
-    //  0         32         64
-    // We can only do it if the MB is larger than 32 and MB <= ME
-    // as RLWINM will replace the contents of [0 - 32) with [32 - 64) even
-    // we didn't rotate it.
-    SDLoc dl(N);
-    SDValue Ops[] = {N->getOperand(0), getI64Imm(0, dl), getI64Imm(MB - 32, dl),
-                     getI64Imm(ME - 32, dl)};
-    CurDAG->SelectNodeTo(N, PPC::RLWINM8, MVT::i64, Ops);
-    return true;
-  }
-
-  return false;
-}
-
-bool PPCDAGToDAGISel::tryAsPairOfRLDICL(SDNode *N) {
-  assert(N->getOpcode() == ISD::AND && "ISD::AND SDNode expected");
-  uint64_t Imm64;
-  if (!isInt64Immediate(N->getOperand(1).getNode(), Imm64))
-    return false;
-
-  // Do nothing if it is 16-bit imm as the pattern in the .td file handle
-  // it well with "andi.".
-  if (isUInt<16>(Imm64))
-    return false;
-
-  SDLoc Loc(N);
-  SDValue Val = N->getOperand(0);
-
-  // Optimized with two rldicl's as follows:
-  // Add missing bits on left to the mask and check that the mask is a
-  // wrapped run of ones, i.e.
-  // Change pattern |0001111100000011111111|
-  //             to |1111111100000011111111|.
-  unsigned NumOfLeadingZeros = countLeadingZeros(Imm64);
-  if (NumOfLeadingZeros != 0)
-    Imm64 |= maskLeadingOnes<uint64_t>(NumOfLeadingZeros);
-
-  unsigned MB, ME;
-  if (!isRunOfOnes64(Imm64, MB, ME))
-    return false;
-
-  //         ME     MB                   MB-ME+63
-  // +----------------------+     +----------------------+
-  // |1111111100000011111111| ->  |0000001111111111111111|
-  // +----------------------+     +----------------------+
-  //  0                    63      0                    63
-  // There are ME + 1 ones on the left and (MB - ME + 63) & 63 zeros in between.
-  unsigned OnesOnLeft = ME + 1;
-  unsigned ZerosInBetween = (MB - ME + 63) & 63;
-  // Rotate left by OnesOnLeft (so leading ones are now trailing ones) and clear
-  // on the left the bits that are already zeros in the mask.
-  Val = SDValue(CurDAG->getMachineNode(PPC::RLDICL, Loc, MVT::i64, Val,
-                                       getI64Imm(OnesOnLeft, Loc),
-                                       getI64Imm(ZerosInBetween, Loc)),
-                0);
-  //        MB-ME+63                      ME     MB
-  // +----------------------+     +----------------------+
-  // |0000001111111111111111| ->  |0001111100000011111111|
-  // +----------------------+     +----------------------+
-  //  0                    63      0                    63
-  // Rotate back by 64 - OnesOnLeft to undo previous rotate. Then clear on the
-  // left the number of ones we previously added.
-  SDValue Ops[] = {Val, getI64Imm(64 - OnesOnLeft, Loc),
-                   getI64Imm(NumOfLeadingZeros, Loc)};
-  CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops);
-  return true;
-}
-
-bool PPCDAGToDAGISel::tryAsSingleRLWIMI(SDNode *N) {
-  assert(N->getOpcode() == ISD::AND && "ISD::AND SDNode expected");
-  unsigned Imm;
-  if (!isInt32Immediate(N->getOperand(1), Imm))
-    return false;
-
-  SDValue Val = N->getOperand(0);
-  unsigned Imm2;
-  // ISD::OR doesn't get all the bitfield insertion fun.
-  // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) might be a
-  // bitfield insert.
-  if (Val.getOpcode() != ISD::OR || !isInt32Immediate(Val.getOperand(1), Imm2))
-    return false;
-
-  // The idea here is to check whether this is equivalent to:
-  //   (c1 & m) | (x & ~m)
-  // where m is a run-of-ones mask. The logic here is that, for each bit in
-  // c1 and c2:
-  //  - if both are 1, then the output will be 1.
-  //  - if both are 0, then the output will be 0.
-  //  - if the bit in c1 is 0, and the bit in c2 is 1, then the output will
-  //    come from x.
-  //  - if the bit in c1 is 1, and the bit in c2 is 0, then the output will
-  //    be 0.
-  //  If that last condition is never the case, then we can form m from the
-  //  bits that are the same between c1 and c2.
-  unsigned MB, ME;
-  if (isRunOfOnes(~(Imm ^ Imm2), MB, ME) && !(~Imm & Imm2)) {
-    SDLoc dl(N);
-    SDValue Ops[] = {Val.getOperand(0), Val.getOperand(1), getI32Imm(0, dl),
-                     getI32Imm(MB, dl), getI32Imm(ME, dl)};
-    ReplaceNode(N, CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops));
-    return true;
-  }
-
-  return false;
-}
-
 bool PPCDAGToDAGISel::tryAsSingleRLDICL(SDNode *N) {
   assert(N->getOpcode() == ISD::AND && "ISD::AND SDNode expected");
   uint64_t Imm64;
   if (!isInt64Immediate(N->getOperand(1).getNode(), Imm64) || !isMask_64(Imm64))
     return false;
 
+  SDValue Val = N->getOperand(0);
+  if (N->getOperand(0).getOpcode() == ISD::ANY_EXTEND) {
     // If this is a 64-bit zero-extension mask, emit rldicl.
     unsigned MB = 64 - countTrailingOnes(Imm64);
-  unsigned SH = 0;
     unsigned Imm;
-  SDValue Val = N->getOperand(0);
-  SDLoc dl(N);
-
-  if (Val.getOpcode() == ISD::ANY_EXTEND) {
     auto Op0 = Val.getOperand(0);
+    SDLoc dl(N);
     if (Op0.getOpcode() == ISD::SRL &&
         isInt32Immediate(Op0.getOperand(1).getNode(), Imm) && Imm <= MB) {
 
       auto ResultType = Val.getNode()->getValueType(0);
       auto ImDef = CurDAG->getMachineNode(PPC::IMPLICIT_DEF, dl, ResultType);
       SDValue IDVal(ImDef, 0);
 
       Val = SDValue(CurDAG->getMachineNode(PPC::INSERT_SUBREG, dl, ResultType,
                                            IDVal, Op0.getOperand(0),
                                            getI32Imm(1, dl)),
                     0);
-      SH = 64 - Imm;
-    }
-  }
-
-  // If the operand is a logical right shift, we can fold it into this
-  // instruction: rldicl(rldicl(x, 64-n, n), 0, mb) -> rldicl(x, 64-n, mb)
-  // for n <= mb. The right shift is really a left rotate followed by a
-  // mask, and this mask is a more-restrictive sub-mask of the mask implied
-  // by the shift.
-  if (Val.getOpcode() == ISD::SRL &&
-      isInt32Immediate(Val.getOperand(1).getNode(), Imm) && Imm <= MB) {
-    assert(Imm < 64 && "Illegal shift amount");
-    Val = Val.getOperand(0);
-    SH = 64 - Imm;
-  }
-
+      unsigned SH = 64 - Imm;
       SDValue Ops[] = {Val, getI32Imm(SH, dl), getI32Imm(MB, dl)};
       CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops);
       return true;
     }
-
-bool PPCDAGToDAGISel::tryAsSingleRLDICR(SDNode *N) {
-  assert(N->getOpcode() == ISD::AND && "ISD::AND SDNode expected");
-  uint64_t Imm64;
-  if (!isInt64Immediate(N->getOperand(1).getNode(), Imm64) ||
-      !isMask_64(~Imm64))
-    return false;
-
-  // If this is a negated 64-bit zero-extension mask,
-  // i.e. the immediate is a sequence of ones from most significant side
-  // and all zero for reminder, we should use rldicr.
-  unsigned MB = 63 - countTrailingOnes(~Imm64);
-  unsigned SH = 0;
-  SDLoc dl(N);
-  SDValue Ops[] = {N->getOperand(0), getI32Imm(SH, dl), getI32Imm(MB, dl)};
-  CurDAG->SelectNodeTo(N, PPC::RLDICR, MVT::i64, Ops);
-  return true;
+  }
 }
 
 bool PPCDAGToDAGISel::tryAsSingleRLDIMI(SDNode *N) {
   assert(N->getOpcode() == ISD::OR && "ISD::OR SDNode expected");
   uint64_t Imm64;
   unsigned MB, ME;
   SDValue N0 = N->getOperand(0);
 
if (Offset.getOpcode() == ISD::TargetConstant ||
           PPCLowering->getPointerTy(CurDAG->getDataLayout()), MVT::Other, Ops);
       transferMemOperands(N, MN);
       ReplaceNode(N, MN);
       return;
     }
   }
 
   case ISD::AND:
-    // If this is an 'and' with a mask, try to emit rlwinm/rldicl/rldicr
-    if (tryAsSingleRLWINM(N) || tryAsSingleRLWIMI(N) || tryAsSingleRLDICL(N) ||
-        tryAsSingleRLDICR(N) || tryAsSingleRLWINM8(N) || tryAsPairOfRLDICL(N))
+    // Try to do this transformation: and(any_extend(srl), C1) -> rldicl
+    if (tryAsSingleRLDICL(N))
       return;
 
     // Other cases are autogenerated.
     break;
   case ISD::OR: {
     if (N->getValueType(0) == MVT::i32)
       if (tryBitfieldInsert(N))
         return;

llvm/test/CodeGen/PowerPC/2016-04-17-combine.ll

 ; RUN: llc -verify-machineinstrs <%s | FileCheck %s
 target datalayout = "e-m:e-i64:64-n32:64"
 target triple = "powerpc64le-unknown-linux-gnu"
 
 ; PR27390 crasher
 
 %typ = type { i32, i32 }
 
 ; On release builds, it doesn't crash, spewing nonsense instead.
-; To make sure it works, check that rldicl is still alive.
-; CHECK: rldicl
+; To make sure it works, check that rldic is still alive.
+; CHECK: rldic
 ; Also, in release, it emits a COPY from a 32-bit register to
 ; a 64-bit register, which happens to be emitted as cror [!]
 ; by the confused CodeGen.  Just to be sure, check there isn't one.
 ; CHECK-NOT: cror
 ; Function Attrs: uwtable
 define signext i32 @_Z8access_pP1Tc(%typ* %p, i8 zeroext %type) {
   %b = getelementptr inbounds %typ, %typ* %p, i64 0, i32 1
   %1 = load i32, i32* %b, align 4
   %2 = ptrtoint i32* %b to i64
   %3 = and i64 %2, -35184372088833
   %4 = inttoptr i64 %3 to i32*
   %_msld = load i32, i32* %4, align 4
   %zzz = add i32 %1,  %_msld
   ret i32 %zzz
 }

llvm/test/CodeGen/PowerPC/Frames-dyn-alloca.ll

 ; PPC32-LINUX-NEXT: blr
 
 ; PPC64-LINUX-LABEL: f1
 ; PPC64-LINUX:      std 31, -8(1)
 ; PPC64-LINUX-NEXT: stdu 1, -64(1)
 ; PPC64-LINUX-NEXT: rldic 3, 3, 2, 30
 ; PPC64-LINUX-NEXT: mr 31, 1
 ; PPC64-LINUX-NEXT: addi 3, 3, 15
-; PPC64-LINUX-NEXT: rldicl 3, 3, 60, 4
+; PPC64-LINUX-NEXT: rotldi 3, 3, 60
 ; PPC64-LINUX-NEXT: addi 4, 31, 64
-; PPC64-LINUX-NEXT: rldicl 3, 3, 4, 29
+; PPC64-LINUX-NEXT: rldic 3, 3, 4, 29
 ; PPC64-LINUX-NEXT: neg 3, 3
 ; PPC64-LINUX-NEXT: stdux 4, 1, 3
 
 ; The linkage area is always put on the top of the stack.
 ; PPC64-LINUX-NEXT: addi 3, 1, 48
 
 ; PPC64-LINUX-NEXT: ld 1, 0(1)
 ; PPC64-LINUX-NEXT: ld 31, -8(1)

 
 ; PPC64-AIX-LABEL: f1
 ; PPC64-AIX:      std 31, -8(1)
 ; PPC64-AIX-NEXT: stdu 1, -64(1)
 ; PPC64-AIX-NEXT: rldic 3, 3, 2, 30
 ; PPC64-AIX-NEXT: mr 31, 1
 ; PPC64-AIX-NEXT: addi 3, 3, 15
 ; PPC64-AIX-NEXT: addi 4, 31, 64
-; PPC64-AIX-NEXT: rldicl 3, 3, 60, 4 
-; PPC64-AIX-NEXT: rldicl 3, 3, 4, 29
+; PPC64-AIX-NEXT: rotldi 3, 3, 60
+; PPC64-AIX-NEXT: rldic 3, 3, 4, 29
 ; PPC64-AIX-NEXT: neg 3, 3
 ; PPC64-AIX-NEXT: stdux 4, 1, 3
 
 ; The linkage area is always put on the top of the stack.
 ; PPC64-AIX-NEXT: addi 3, 1, 48
 
 ; PPC64-AIX-NEXT: ld 1, 0(1)
 ; PPC64-AIX-NEXT: ld 31, -8(1)
 ; PPC64-AIX-NEXT: blr

llvm/test/CodeGen/PowerPC/and-mask.ll

; CHECK-NEXT:    blr
   %and = and i32 %a, -2
   ret i32 %and
 }
 
 ; mask 0xFFFFFFFFFFFFFFF9
 define i64 @test2(i64 %a) {
 ; CHECK-LABEL: test2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rldicl 3, 3, 61, 2
-; CHECK-NEXT:    rotldi 3, 3, 3
+; CHECK-NEXT:    li 4, -7
+; CHECK-NEXT:    and 3, 3, 4
 ; CHECK-NEXT:    blr
   %and = and i64 %a, -7
   ret i64 %and
 }
 
 ; mask: 0xFFFFFFC00000
 define i64 @test3(i64 %a) {
 ; CHECK-LABEL: test3:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rldicl 3, 3, 42, 22
-; CHECK-NEXT:    rldicl 3, 3, 22, 16
+; CHECK-NEXT:    rotldi 3, 3, 42
+; CHECK-NEXT:    rldic 3, 3, 22, 16
 ; CHECK-NEXT:    blr
   %and = and i64 %a, 281474972516352
   ret i64 %and
 }
 
 ; mask: 0xC000000FF
 define i64 @test4(i64 %a) {
 ; CHECK-LABEL: test4:
; CHECK-NEXT:    blr
   %and = and i64 %a, 4290838527
   ret i64 %and
 }
 
 ; mask: 0x3FC0FFE0
 define i64 @test6(i64 %a) {
 ; CHECK-LABEL: test6:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lis 4, 16320
-; CHECK-NEXT:    ori 4, 4, 65504
-; CHECK-NEXT:    and 3, 3, 4
+; CHECK-NEXT:    rlwinm 3, 3, 0, 16, 9
+; CHECK-NEXT:    rlwinm 3, 3, 0, 2, 26
 ; CHECK-NEXT:    blr
   %and = and i64 %a, 1069613024
   ret i64 %and
 }
 
 ; mask: 0x3FC000001FFFF
 define i64 @test7(i64 %a) {
 ; CHECK-LABEL: test7:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    rldicl 3, 3, 22, 25
 ; CHECK-NEXT:    rldicl 3, 3, 42, 14
 ; CHECK-NEXT:    blr
   %and = and i64 %a, 1121501860462591
   ret i64 %and
 }
 
 ; mask: 0xFFC0000000007800
 define i64 @test8(i64 %a) {
 ; CHECK-LABEL: test8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lis 4, 480
-; CHECK-NEXT:    ori 4, 4, 1023
-; CHECK-NEXT:    rotldi 4, 4, 54
-; CHECK-NEXT:    and 3, 3, 4
+; CHECK-NEXT:    rldicl 3, 3, 10, 39
+; CHECK-NEXT:    rldicr 3, 3, 54, 52
 ; CHECK-NEXT:    blr
   %and = and i64 %a, 18428729675200100352
   ret i64 %and
 }
 
 ; mask: 0x1ffe0007e000
 define i64 @test9(i64 %a) {
 ; CHECK-LABEL: test9:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lis 4, -16
-; CHECK-NEXT:    ori 4, 4, 63
-; CHECK-NEXT:    rldic 4, 4, 13, 19
-; CHECK-NEXT:    and 3, 3, 4
+; CHECK-NEXT:    rotldi 4, 3, 31
+; CHECK-NEXT:    rlwinm 3, 3, 0, 13, 18
+; CHECK-NEXT:    rldimi 3, 4, 33, 19
 ; CHECK-NEXT:    blr
   %and = and i64 %a, 35175782670336
   ret i64 %and
 }
 
 ; mask: 0xfc1fffe007e000
 define i64 @test10(i64 %a) {
 ; CHECK-LABEL: test10:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lis 4, 252
-; CHECK-NEXT:    ori 4, 4, 8191
-; CHECK-NEXT:    rldic 4, 4, 32, 8
-; CHECK-NEXT:    oris 4, 4, 57351
-; CHECK-NEXT:    ori 4, 4, 57344
-; CHECK-NEXT:    and 3, 3, 4
+; CHECK-NEXT:    rotldi 5, 3, 35
+; CHECK-NEXT:    rlwinm 4, 3, 0, 13, 18
+; CHECK-NEXT:    rldimi 4, 5, 29, 19
+; CHECK-NEXT:    rotldi 3, 3, 14
+; CHECK-NEXT:    rldimi 4, 3, 50, 8
+; CHECK-NEXT:    mr 3, 4
 ; CHECK-NEXT:    blr
   %and = and i64 %a, 70966877966819328
   ret i64 %and
 }

llvm/test/CodeGen/PowerPC/andc.ll

; CHECK-NEXT:    blr
   %and = and i32 %x, %y
   %cmp = icmp eq i32 %and, %y
   ret i1 %cmp
 }
 
 define i1 @and_cmp_const(i32 %x) {
 ; CHECK-LABEL: and_cmp_const:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    li 4, 43
-; CHECK-NEXT:    andc 3, 4, 3
+; CHECK-NEXT:    not 3, 3
+; CHECK-NEXT:    andi. 3, 3, 43
 ; CHECK-NEXT:    cntlzw 3, 3
 ; CHECK-NEXT:    rlwinm 3, 3, 27, 31, 31
 ; CHECK-NEXT:    blr
   %and = and i32 %x, 43
   %cmp = icmp eq i32 %and, 43
   ret i1 %cmp
 }
 

llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll

 ; PPC64-NEXT:    addi 6, 6, 1
 ; PPC64-NEXT:    clrldi 7, 5, 53
 ; PPC64-NEXT:    cmpldi 1, 6, 1
 ; PPC64-NEXT:    clrldi 6, 3, 53
 ; PPC64-NEXT:    addi 7, 7, 2047
 ; PPC64-NEXT:    addi 6, 6, 2047
 ; PPC64-NEXT:    or 4, 7, 4
 ; PPC64-NEXT:    or 6, 6, 3
-; PPC64-NEXT:    rldicl 4, 4, 53, 11
+; PPC64-NEXT:    rotldi 4, 4, 53
 ; PPC64-NEXT:    rldicr 6, 6, 0, 52
 ; PPC64-NEXT:    bc 12, 1, .LBB2_4
 ; PPC64-NEXT:  # %bb.3: # %entry
 ; PPC64-NEXT:    ori 6, 3, 0
 ; PPC64-NEXT:    b .LBB2_4
 ; PPC64-NEXT:  .LBB2_4: # %entry
-; PPC64-NEXT:    rldicl 4, 4, 11, 1
+; PPC64-NEXT:    rldic 4, 4, 11, 1
 ; PPC64-NEXT:    cmpdi 3, 0
 ; PPC64-NEXT:    std 6, -32(1)
 ; PPC64-NEXT:    bc 12, 5, .LBB2_6
 ; PPC64-NEXT:  # %bb.5: # %entry
 ; PPC64-NEXT:    ori 4, 5, 0
 ; PPC64-NEXT:    b .LBB2_6
 ; PPC64-NEXT:  .LBB2_6: # %entry
 ; PPC64-NEXT:    std 4, -24(1)

llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll

 ; RUN: llc -verify-machineinstrs -print-before=peephole-opt -print-after=peephole-opt -mtriple=powerpc64-unknown-linux-gnu -o /dev/null 2>&1 < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -print-before=peephole-opt -print-after=peephole-opt -mtriple=powerpc64le-unknown-linux-gnu -o /dev/null 2>&1 < %s | FileCheck %s
 
 ; CHECK-LABEL: fn1
 define signext i32 @fn1(i32 %baz) {
   %1 = mul nsw i32 %baz, 208
   %2 = zext i32 %1 to i64
   %3 = shl i64 %2, 48
   %4 = ashr exact i64 %3, 48
-; CHECK: RLWINM8 killed {{[^,]+}}, 0, 16, 27
+; CHECK: RLWINM8 {{[^,]+}}, 0, 16, 27
 ; CHECK: CMPLDI
 ; CHECK: BCC
 
 ; CHECK: ANDI8_rec {{[^,]+}}, 65520, implicit-def $cr0
 ; CHECK: COPY killed $cr0
 ; CHECK: BCC
   %5 = icmp eq i64 %4, 0
   br i1 %5, label %foo, label %bar

llvm/test/CodeGen/PowerPC/popcnt-zext.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -mattr=+popcntd < %s      | FileCheck %s --check-prefixes=ANY,FAST
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -mattr=+slow-popcntd < %s | FileCheck %s --check-prefixes=ANY,SLOW
 
 define i16 @zpop_i8_i16(i8 %x) {
 ; FAST-LABEL: zpop_i8_i16:
 ; FAST:       # %bb.0:
 ; FAST-NEXT:    clrldi 3, 3, 56
 ; FAST-NEXT:    popcntd 3, 3
 ; FAST-NEXT:    blr
 ;
 ; SLOW-LABEL: zpop_i8_i16:
 ; SLOW:       # %bb.0:
 ; SLOW-NEXT:    clrlwi 5, 3, 24
 ; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 85
-; SLOW-NEXT:    lis 4, 13107
 ; SLOW-NEXT:    sub 3, 5, 3
-; SLOW-NEXT:    ori 4, 4, 13107
-; SLOW-NEXT:    rotlwi 5, 3, 30
-; SLOW-NEXT:    and 3, 3, 4
-; SLOW-NEXT:    andis. 4, 5, 13107
-; SLOW-NEXT:    andi. 5, 5, 13107
-; SLOW-NEXT:    or 4, 5, 4
-; SLOW-NEXT:    add 3, 3, 4
-; SLOW-NEXT:    lis 5, 3855
-; SLOW-NEXT:    srwi 4, 3, 4
-; SLOW-NEXT:    add 3, 3, 4
+; SLOW-NEXT:    andis. 5, 3, 13107
+; SLOW-NEXT:    andi. 6, 3, 13107
+; SLOW-NEXT:    rotlwi 3, 3, 30
+; SLOW-NEXT:    or 5, 6, 5
+; SLOW-NEXT:    andis. 6, 3, 13107
+; SLOW-NEXT:    andi. 3, 3, 13107
+; SLOW-NEXT:    or 3, 3, 6
+; SLOW-NEXT:    add 3, 5, 3
+; SLOW-NEXT:    srwi 5, 3, 4
+; SLOW-NEXT:    add 3, 3, 5
 ; SLOW-NEXT:    lis 4, 257
-; SLOW-NEXT:    ori 5, 5, 3855
-; SLOW-NEXT:    and 3, 3, 5
+; SLOW-NEXT:    andis. 5, 3, 3855
+; SLOW-NEXT:    andi. 3, 3, 3855
+; SLOW-NEXT:    or 3, 3, 5
 ; SLOW-NEXT:    ori 4, 4, 257
 ; SLOW-NEXT:    mullw 3, 3, 4
 ; SLOW-NEXT:    srwi 3, 3, 24
 ; SLOW-NEXT:    blr
   %z = zext i8 %x to i16
   %pop = tail call i16 @llvm.ctpop.i16(i16 %z)
   ret i16 %pop
 }
 
 define i16 @popz_i8_i16(i8 %x) {
 ; FAST-LABEL: popz_i8_i16:
 ; FAST:       # %bb.0:
 ; FAST-NEXT:    clrldi 3, 3, 56
 ; FAST-NEXT:    popcntd 3, 3
 ; FAST-NEXT:    blr
 ;
 ; SLOW-LABEL: popz_i8_i16:
 ; SLOW:       # %bb.0:
 ; SLOW-NEXT:    clrlwi 5, 3, 24
 ; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 85
-; SLOW-NEXT:    lis 4, 13107
 ; SLOW-NEXT:    sub 3, 5, 3
-; SLOW-NEXT:    ori 4, 4, 13107
-; SLOW-NEXT:    rotlwi 5, 3, 30
-; SLOW-NEXT:    and 3, 3, 4
-; SLOW-NEXT:    andis. 4, 5, 13107
-; SLOW-NEXT:    andi. 5, 5, 13107
-; SLOW-NEXT:    or 4, 5, 4
-; SLOW-NEXT:    add 3, 3, 4
-; SLOW-NEXT:    lis 5, 3855
-; SLOW-NEXT:    srwi 4, 3, 4
-; SLOW-NEXT:    add 3, 3, 4
+; SLOW-NEXT:    andis. 5, 3, 13107
+; SLOW-NEXT:    andi. 6, 3, 13107
+; SLOW-NEXT:    rotlwi 3, 3, 30
+; SLOW-NEXT:    or 5, 6, 5
+; SLOW-NEXT:    andis. 6, 3, 13107
+; SLOW-NEXT:    andi. 3, 3, 13107
+; SLOW-NEXT:    or 3, 3, 6
+; SLOW-NEXT:    add 3, 5, 3
+; SLOW-NEXT:    srwi 5, 3, 4
+; SLOW-NEXT:    add 3, 3, 5
 ; SLOW-NEXT:    lis 4, 257
-; SLOW-NEXT:    ori 5, 5, 3855
-; SLOW-NEXT:    and 3, 3, 5
+; SLOW-NEXT:    andis. 5, 3, 3855
+; SLOW-NEXT:    andi. 3, 3, 3855
+; SLOW-NEXT:    or 3, 3, 5
 ; SLOW-NEXT:    ori 4, 4, 257
 ; SLOW-NEXT:    mullw 3, 3, 4
 ; SLOW-NEXT:    rlwinm 3, 3, 8, 24, 31
 ; SLOW-NEXT:    blr
   %pop = tail call i8 @llvm.ctpop.i8(i8 %x)
   %z = zext i8 %pop to i16
   ret i16 %z
 }
 
 define i32 @zpop_i8_i32(i8 %x) {
 ; FAST-LABEL: zpop_i8_i32:
 ; FAST:       # %bb.0:
 ; FAST-NEXT:    clrlwi 3, 3, 24
 ; FAST-NEXT:    popcntw 3, 3
 ; FAST-NEXT:    blr
 ;
 ; SLOW-LABEL: zpop_i8_i32:
 ; SLOW:       # %bb.0:
 ; SLOW-NEXT:    clrlwi 5, 3, 24
 ; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 85
-; SLOW-NEXT:    lis 4, 13107
 ; SLOW-NEXT:    sub 3, 5, 3
-; SLOW-NEXT:    ori 4, 4, 13107
-; SLOW-NEXT:    rotlwi 5, 3, 30
-; SLOW-NEXT:    and 3, 3, 4
-; SLOW-NEXT:    andis. 4, 5, 13107
-; SLOW-NEXT:    andi. 5, 5, 13107
-; SLOW-NEXT:    or 4, 5, 4
-; SLOW-NEXT:    add 3, 3, 4
-; SLOW-NEXT:    lis 5, 3855
-; SLOW-NEXT:    srwi 4, 3, 4
-; SLOW-NEXT:    add 3, 3, 4
+; SLOW-NEXT:    andis. 5, 3, 13107
+; SLOW-NEXT:    andi. 6, 3, 13107
+; SLOW-NEXT:    rotlwi 3, 3, 30
+; SLOW-NEXT:    or 5, 6, 5
+; SLOW-NEXT:    andis. 6, 3, 13107
+; SLOW-NEXT:    andi. 3, 3, 13107
+; SLOW-NEXT:    or 3, 3, 6
+; SLOW-NEXT:    add 3, 5, 3
+; SLOW-NEXT:    srwi 5, 3, 4
+; SLOW-NEXT:    add 3, 3, 5
 ; SLOW-NEXT:    lis 4, 257
-; SLOW-NEXT:    ori 5, 5, 3855
-; SLOW-NEXT:    and 3, 3, 5
+; SLOW-NEXT:    andis. 5, 3, 3855
+; SLOW-NEXT:    andi. 3, 3, 3855
+; SLOW-NEXT:    or 3, 3, 5
 ; SLOW-NEXT:    ori 4, 4, 257
 ; SLOW-NEXT:    mullw 3, 3, 4
 ; SLOW-NEXT:    srwi 3, 3, 24
 ; SLOW-NEXT:    blr
   %z = zext i8 %x to i32
   %pop = tail call i32 @llvm.ctpop.i32(i32 %z)
   ret i32 %pop
 }
 
 define i32 @popz_i8_32(i8 %x) {
 ; FAST-LABEL: popz_i8_32:
 ; FAST:       # %bb.0:
 ; FAST-NEXT:    clrldi 3, 3, 56
 ; FAST-NEXT:    popcntd 3, 3
 ; FAST-NEXT:    blr
 ;
 ; SLOW-LABEL: popz_i8_32:
 ; SLOW:       # %bb.0:
 ; SLOW-NEXT:    clrlwi 5, 3, 24
 ; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 85
-; SLOW-NEXT:    lis 4, 13107
 ; SLOW-NEXT:    sub 3, 5, 3
-; SLOW-NEXT:    ori 4, 4, 13107
-; SLOW-NEXT:    rotlwi 5, 3, 30
-; SLOW-NEXT:    and 3, 3, 4
-; SLOW-NEXT:    andis. 4, 5, 13107
-; SLOW-NEXT:    andi. 5, 5, 13107
-; SLOW-NEXT:    or 4, 5, 4
-; SLOW-NEXT:    add 3, 3, 4
-; SLOW-NEXT:    lis 5, 3855
-; SLOW-NEXT:    srwi 4, 3, 4
-; SLOW-NEXT:    add 3, 3, 4
+; SLOW-NEXT:    andis. 5, 3, 13107
+; SLOW-NEXT:    andi. 6, 3, 13107
+; SLOW-NEXT:    rotlwi 3, 3, 30
+; SLOW-NEXT:    or 5, 6, 5
+; SLOW-NEXT:    andis. 6, 3, 13107
+; SLOW-NEXT:    andi. 3, 3, 13107
+; SLOW-NEXT:    or 3, 3, 6
+; SLOW-NEXT:    add 3, 5, 3
+; SLOW-NEXT:    srwi 5, 3, 4
+; SLOW-NEXT:    add 3, 3, 5
 ; SLOW-NEXT:    lis 4, 257
-; SLOW-NEXT:    ori 5, 5, 3855
-; SLOW-NEXT:    and 3, 3, 5
+; SLOW-NEXT:    andis. 5, 3, 3855
+; SLOW-NEXT:    andi. 3, 3, 3855
+; SLOW-NEXT:    or 3, 3, 5
 ; SLOW-NEXT:    ori 4, 4, 257
 ; SLOW-NEXT:    mullw 3, 3, 4
 ; SLOW-NEXT:    rlwinm 3, 3, 8, 24, 31
 ; SLOW-NEXT:    blr
   %pop = tail call i8 @llvm.ctpop.i8(i8 %x)
   %z = zext i8 %pop to i32
   ret i32 %z
 }
 
 define i32 @zpop_i16_i32(i16 %x) {
 ; FAST-LABEL: zpop_i16_i32:
 ; FAST:       # %bb.0:
 ; FAST-NEXT:    clrlwi 3, 3, 16
 ; FAST-NEXT:    popcntw 3, 3
 ; FAST-NEXT:    blr
 ;
 ; SLOW-LABEL: zpop_i16_i32:
 ; SLOW:       # %bb.0:
 ; SLOW-NEXT:    clrlwi 5, 3, 16
 ; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 21845
-; SLOW-NEXT:    lis 4, 13107
 ; SLOW-NEXT:    sub 3, 5, 3
-; SLOW-NEXT:    ori 4, 4, 13107
-; SLOW-NEXT:    rotlwi 5, 3, 30
-; SLOW-NEXT:    and 3, 3, 4
-; SLOW-NEXT:    andis. 4, 5, 13107
-; SLOW-NEXT:    andi. 5, 5, 13107
-; SLOW-NEXT:    or 4, 5, 4
-; SLOW-NEXT:    add 3, 3, 4
-; SLOW-NEXT:    lis 5, 3855
-; SLOW-NEXT:    srwi 4, 3, 4
-; SLOW-NEXT:    add 3, 3, 4
+; SLOW-NEXT:    andis. 5, 3, 13107
+; SLOW-NEXT:    andi. 6, 3, 13107
+; SLOW-NEXT:    rotlwi 3, 3, 30
+; SLOW-NEXT:    or 5, 6, 5
+; SLOW-NEXT:    andis. 6, 3, 13107
+; SLOW-NEXT:    andi. 3, 3, 13107
+; SLOW-NEXT:    or 3, 3, 6
+; SLOW-NEXT:    add 3, 5, 3
+; SLOW-NEXT:    srwi 5, 3, 4
+; SLOW-NEXT:    add 3, 3, 5
 ; SLOW-NEXT:    lis 4, 257
-; SLOW-NEXT:    ori 5, 5, 3855
-; SLOW-NEXT:    and 3, 3, 5
+; SLOW-NEXT:    andis. 5, 3, 3855
+; SLOW-NEXT:    andi. 3, 3, 3855
+; SLOW-NEXT:    or 3, 3, 5
 ; SLOW-NEXT:    ori 4, 4, 257
 ; SLOW-NEXT:    mullw 3, 3, 4
 ; SLOW-NEXT:    srwi 3, 3, 24
 ; SLOW-NEXT:    blr
   %z = zext i16 %x to i32
   %pop = tail call i32 @llvm.ctpop.i32(i32 %z)
   ret i32 %pop
 }
 
 define i32 @popz_i16_32(i16 %x) {
 ; FAST-LABEL: popz_i16_32:
 ; FAST:       # %bb.0:
 ; FAST-NEXT:    clrldi 3, 3, 48
 ; FAST-NEXT:    popcntd 3, 3
 ; FAST-NEXT:    blr
 ;
 ; SLOW-LABEL: popz_i16_32:
 ; SLOW:       # %bb.0:
 ; SLOW-NEXT:    clrlwi 5, 3, 16
 ; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 21845
-; SLOW-NEXT:    lis 4, 13107
 ; SLOW-NEXT:    sub 3, 5, 3
-; SLOW-NEXT:    ori 4, 4, 13107
-; SLOW-NEXT:    rotlwi 5, 3, 30
-; SLOW-NEXT:    and 3, 3, 4
-; SLOW-NEXT:    andis. 4, 5, 13107
-; SLOW-NEXT:    andi. 5, 5, 13107
-; SLOW-NEXT:    or 4, 5, 4
-; SLOW-NEXT:    add 3, 3, 4
-; SLOW-NEXT:    lis 5, 3855
-; SLOW-NEXT:    srwi 4, 3, 4
-; SLOW-NEXT:    add 3, 3, 4
+; SLOW-NEXT:    andis. 5, 3, 13107
+; SLOW-NEXT:    andi. 6, 3, 13107
+; SLOW-NEXT:    rotlwi 3, 3, 30
+; SLOW-NEXT:    or 5, 6, 5
+; SLOW-NEXT:    andis. 6, 3, 13107
+; SLOW-NEXT:    andi. 3, 3, 13107
+; SLOW-NEXT:    or 3, 3, 6
+; SLOW-NEXT:    add 3, 5, 3
+; SLOW-NEXT:    srwi 5, 3, 4
+; SLOW-NEXT:    add 3, 3, 5
 ; SLOW-NEXT:    lis 4, 257
-; SLOW-NEXT:    ori 5, 5, 3855
-; SLOW-NEXT:    and 3, 3, 5
+; SLOW-NEXT:    andis. 5, 3, 3855
+; SLOW-NEXT:    andi. 3, 3, 3855
+; SLOW-NEXT:    or 3, 3, 5
 ; SLOW-NEXT:    ori 4, 4, 257
 ; SLOW-NEXT:    mullw 3, 3, 4
 ; SLOW-NEXT:    rlwinm 3, 3, 8, 24, 31
 ; SLOW-NEXT:    blr
   %pop = tail call i16 @llvm.ctpop.i16(i16 %x)
   %z = zext i16 %pop to i32
   ret i32 %z
 }

 ; FAST-NEXT:    blr
 ;
 ; SLOW-LABEL: popz_i32_i64:
 ; SLOW:       # %bb.0:
 ; SLOW-NEXT:    rotlwi 5, 3, 31
 ; SLOW-NEXT:    andis. 6, 5, 21845
 ; SLOW-NEXT:    andi. 5, 5, 21845
 ; SLOW-NEXT:    or 5, 5, 6
-; SLOW-NEXT:    lis 4, 13107
 ; SLOW-NEXT:    sub 3, 3, 5
-; SLOW-NEXT:    ori 4, 4, 13107
-; SLOW-NEXT:    rotlwi 5, 3, 30
-; SLOW-NEXT:    and 3, 3, 4
-; SLOW-NEXT:    andis. 4, 5, 13107
-; SLOW-NEXT:    andi. 5, 5, 13107
-; SLOW-NEXT:    or 4, 5, 4
-; SLOW-NEXT:    add 3, 3, 4
-; SLOW-NEXT:    lis 5, 3855
-; SLOW-NEXT:    srwi 4, 3, 4
-; SLOW-NEXT:    add 3, 3, 4
+; SLOW-NEXT:    andis. 5, 3, 13107
+; SLOW-NEXT:    andi. 6, 3, 13107
+; SLOW-NEXT:    rotlwi 3, 3, 30
+; SLOW-NEXT:    or 5, 6, 5
+; SLOW-NEXT:    andis. 6, 3, 13107
+; SLOW-NEXT:    andi. 3, 3, 13107
+; SLOW-NEXT:    or 3, 3, 6
+; SLOW-NEXT:    add 3, 5, 3
+; SLOW-NEXT:    srwi 5, 3, 4
+; SLOW-NEXT:    add 3, 3, 5
 ; SLOW-NEXT:    lis 4, 257
-; SLOW-NEXT:    ori 5, 5, 3855
-; SLOW-NEXT:    and 3, 3, 5
+; SLOW-NEXT:    andis. 5, 3, 3855
+; SLOW-NEXT:    andi. 3, 3, 3855
+; SLOW-NEXT:    or 3, 3, 5
 ; SLOW-NEXT:    ori 4, 4, 257
 ; SLOW-NEXT:    mullw 3, 3, 4
 ; SLOW-NEXT:    rlwinm 3, 3, 8, 24, 31
 ; SLOW-NEXT:    blr
   %pop = tail call i32 @llvm.ctpop.i32(i32 %x)
   %z = zext i32 %pop to i64
   ret i64 %z
 }
 
 define i64 @popa_i16_i64(i16 %x) {
 ; FAST-LABEL: popa_i16_i64:
 ; FAST:       # %bb.0:
 ; FAST-NEXT:    clrldi 3, 3, 48
 ; FAST-NEXT:    popcntd 3, 3
 ; FAST-NEXT:    rlwinm 3, 3, 0, 27, 27
 ; FAST-NEXT:    blr
 ;
 ; SLOW-LABEL: popa_i16_i64:
 ; SLOW:       # %bb.0:
 ; SLOW-NEXT:    clrlwi 5, 3, 16
 ; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 21845
-; SLOW-NEXT:    lis 4, 13107
 ; SLOW-NEXT:    sub 3, 5, 3
-; SLOW-NEXT:    ori 4, 4, 13107
-; SLOW-NEXT:    rotlwi 5, 3, 30
-; SLOW-NEXT:    and 3, 3, 4
-; SLOW-NEXT:    andis. 4, 5, 13107
-; SLOW-NEXT:    andi. 5, 5, 13107
-; SLOW-NEXT:    or 4, 5, 4
-; SLOW-NEXT:    add 3, 3, 4
-; SLOW-NEXT:    lis 5, 3855
-; SLOW-NEXT:    srwi 4, 3, 4
-; SLOW-NEXT:    add 3, 3, 4
+; SLOW-NEXT:    andis. 5, 3, 13107
+; SLOW-NEXT:    andi. 6, 3, 13107
+; SLOW-NEXT:    rotlwi 3, 3, 30
+; SLOW-NEXT:    or 5, 6, 5
+; SLOW-NEXT:    andis. 6, 3, 13107
+; SLOW-NEXT:    andi. 3, 3, 13107
+; SLOW-NEXT:    or 3, 3, 6
+; SLOW-NEXT:    add 3, 5, 3
+; SLOW-NEXT:    srwi 5, 3, 4
+; SLOW-NEXT:    add 3, 3, 5
 ; SLOW-NEXT:    lis 4, 257
-; SLOW-NEXT:    ori 5, 5, 3855
-; SLOW-NEXT:    and 3, 3, 5
+; SLOW-NEXT:    andis. 5, 3, 3855
+; SLOW-NEXT:    andi. 3, 3, 3855
+; SLOW-NEXT:    or 3, 3, 5
 ; SLOW-NEXT:    ori 4, 4, 257
 ; SLOW-NEXT:    mullw 3, 3, 4
 ; SLOW-NEXT:    srwi 3, 3, 24
-; SLOW-NEXT:    rlwinm 3, 3, 0, 27, 27
+; SLOW-NEXT:    andi. 3, 3, 16
 ; SLOW-NEXT:    blr
   %pop = call i16 @llvm.ctpop.i16(i16 %x)
   %z = zext i16 %pop to i64 ; SimplifyDemandedBits may turn zext (or sext) into aext
   %a = and i64 %z, 16
   ret i64 %a
 }
 
 declare i8 @llvm.ctpop.i8(i8) nounwind readnone
 declare i16 @llvm.ctpop.i16(i16) nounwind readnone
 declare i32 @llvm.ctpop.i32(i32) nounwind readnone
 declare i64 @llvm.ctpop.i64(i64) nounwind readnone

llvm/test/CodeGen/PowerPC/pr46759.ll

 ; CHECK-LE-NEXT:    .cfi_def_cfa_register r1
 ; CHECK-LE-NEXT:    .cfi_def_cfa_register r30
 ; CHECK-LE-NEXT:    .cfi_offset r31, -8
 ; CHECK-LE-NEXT:    .cfi_offset r30, -16
 ; CHECK-LE-NEXT:    clrldi r3, r3, 32
 ; CHECK-LE-NEXT:    li r5, -2048
 ; CHECK-LE-NEXT:    mr r31, r1
 ; CHECK-LE-NEXT:    addi r3, r3, 15
-; CHECK-LE-NEXT:    rldicl r3, r3, 60, 4
-; CHECK-LE-NEXT:    rldicl r3, r3, 4, 31
+; CHECK-LE-NEXT:    rotldi r3, r3, 60
+; CHECK-LE-NEXT:    rldic r3, r3, 4, 31
 ; CHECK-LE-NEXT:    neg r4, r3
 ; CHECK-LE-NEXT:    ld r3, 0(r1)
 ; CHECK-LE-NEXT:    and r5, r4, r5
 ; CHECK-LE-NEXT:    mr r4, r5
 ; CHECK-LE-NEXT:    li r5, -4096
 ; CHECK-LE-NEXT:    divd r6, r4, r5
 ; CHECK-LE-NEXT:    mulld r5, r6, r5
 ; CHECK-LE-NEXT:    sub r5, r4, r5

llvm/test/CodeGen/PowerPC/pr47373.ll

 ; CHECK-NEXT:    add r7, r3, r6
 ; CHECK-NEXT:    cmpld r29, r7
 ; CHECK-NEXT:    add r6, r29, r6
 ; CHECK-NEXT:    bc 4, lt, .LBB0_4
 ; CHECK-NEXT:  # %bb.3: # %vector.memcheck
 ; CHECK-NEXT:    cmpld r3, r6
 ; CHECK-NEXT:    bc 12, lt, .LBB0_7
 ; CHECK-NEXT:  .LBB0_4: # %vector.ph
-; CHECK-NEXT:    rlwinm r5, r4, 0, 0, 29
+; CHECK-NEXT:    rldicr r5, r4, 0, 61
 ; CHECK-NEXT:    li r7, 15
 ; CHECK-NEXT:    addi r6, r5, -4
 ; CHECK-NEXT:    addi r8, r1, 144
 ; CHECK-NEXT:    rldicl r6, r6, 62, 2
 ; CHECK-NEXT:    addi r9, r1, 128
 ; CHECK-NEXT:    addi r6, r6, 1
 ; CHECK-NEXT:    addi r10, r1, 160
 ; CHECK-NEXT:    mtctr r6

llvm/test/CodeGen/PowerPC/setcc-logic.ll

; CHECK-NEXT:    blr
   %cmp2 = icmp eq <4 x i32> %c, %d
   %and = and <4 x i1> %cmp1, %cmp2
   ret <4 x i1> %and
 }
 
 define i1 @or_icmps_const_1bit_diff(i64 %x) {
 ; CHECK-LABEL: or_icmps_const_1bit_diff:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    li 4, -5
 ; CHECK-NEXT:    addi 3, 3, -13
-; CHECK-NEXT:    rldicl 3, 3, 61, 1
-; CHECK-NEXT:    rotldi 3, 3, 3
+; CHECK-NEXT:    and 3, 3, 4
 ; CHECK-NEXT:    cntlzd 3, 3
 ; CHECK-NEXT:    rldicl 3, 3, 58, 63
 ; CHECK-NEXT:    blr
   %a = icmp eq i64 %x, 17
   %b = icmp eq i64 %x, 13
   %r = or i1 %a, %b
   ret i1 %r
 }

llvm/test/CodeGen/PowerPC/stack-clash-dynamic-alloca.ll

 ; CHECK-LE-LABEL: foo:
 ; CHECK-LE:       # %bb.0:
 ; CHECK-LE-NEXT:    std r31, -8(r1)
 ; CHECK-LE-NEXT:    stdu r1, -48(r1)
 ; CHECK-LE-NEXT:    rldic r3, r3, 2, 30
 ; CHECK-LE-NEXT:    li r5, -32768
 ; CHECK-LE-NEXT:    mr r31, r1
 ; CHECK-LE-NEXT:    addi r3, r3, 15
-; CHECK-LE-NEXT:    rldicl r3, r3, 60, 4
-; CHECK-LE-NEXT:    rldicl r3, r3, 4, 29
+; CHECK-LE-NEXT:    rotldi r3, r3, 60
+; CHECK-LE-NEXT:    rldic r3, r3, 4, 29
 ; CHECK-LE-NEXT:    neg r4, r3
 ; CHECK-LE-NEXT:    addi r3, r31, 48
 ; CHECK-LE-NEXT:    divd r6, r4, r5
 ; CHECK-LE-NEXT:    mulld r5, r6, r5
 ; CHECK-LE-NEXT:    sub r5, r4, r5
 ; CHECK-LE-NEXT:    add r4, r1, r4
 ; CHECK-LE-NEXT:    stdux r3, r1, r5
 ; CHECK-LE-NEXT:    cmpd r1, r4

 ; CHECK-P9-LE-LABEL: foo:
 ; CHECK-P9-LE:       # %bb.0:
 ; CHECK-P9-LE-NEXT:    std r31, -8(r1)
 ; CHECK-P9-LE-NEXT:    stdu r1, -48(r1)
 ; CHECK-P9-LE-NEXT:    rldic r3, r3, 2, 30
 ; CHECK-P9-LE-NEXT:    addi r3, r3, 15
 ; CHECK-P9-LE-NEXT:    li r6, -32768
 ; CHECK-P9-LE-NEXT:    mr r31, r1
-; CHECK-P9-LE-NEXT:    rldicl r3, r3, 60, 4
-; CHECK-P9-LE-NEXT:    rldicl r3, r3, 4, 29
+; CHECK-P9-LE-NEXT:    rotldi r3, r3, 60
+; CHECK-P9-LE-NEXT:    rldic r3, r3, 4, 29
 ; CHECK-P9-LE-NEXT:    neg r5, r3
 ; CHECK-P9-LE-NEXT:    addi r3, r31, 48
 ; CHECK-P9-LE-NEXT:    divd r7, r5, r6
 ; CHECK-P9-LE-NEXT:    add r4, r1, r5
 ; CHECK-P9-LE-NEXT:    mulld r6, r7, r6
 ; CHECK-P9-LE-NEXT:    sub r5, r5, r6
 ; CHECK-P9-LE-NEXT:    stdux r3, r1, r5
 ; CHECK-P9-LE-NEXT:    cmpd r1, r4

 ;
 ; CHECK-BE-LABEL: foo:
 ; CHECK-BE:       # %bb.0:
 ; CHECK-BE-NEXT:    std r31, -8(r1)
 ; CHECK-BE-NEXT:    stdu r1, -64(r1)
 ; CHECK-BE-NEXT:    rldic r3, r3, 2, 30
 ; CHECK-BE-NEXT:    li r5, -32768
 ; CHECK-BE-NEXT:    addi r3, r3, 15
-; CHECK-BE-NEXT:    rldicl r3, r3, 60, 4
+; CHECK-BE-NEXT:    rotldi r3, r3, 60
 ; CHECK-BE-NEXT:    mr r31, r1
-; CHECK-BE-NEXT:    rldicl r3, r3, 4, 29
+; CHECK-BE-NEXT:    rldic r3, r3, 4, 29
 ; CHECK-BE-NEXT:    neg r4, r3
 ; CHECK-BE-NEXT:    divd r6, r4, r5
 ; CHECK-BE-NEXT:    addi r3, r31, 64
 ; CHECK-BE-NEXT:    mulld r5, r6, r5
 ; CHECK-BE-NEXT:    sub r5, r4, r5
 ; CHECK-BE-NEXT:    add r4, r1, r4
 ; CHECK-BE-NEXT:    stdux r3, r1, r5
 ; CHECK-BE-NEXT:    cmpd r1, r4

 ; CHECK-LE-LABEL: bar:
 ; CHECK-LE:       # %bb.0:
 ; CHECK-LE-NEXT:    std r31, -8(r1)
 ; CHECK-LE-NEXT:    stdu r1, -48(r1)
 ; CHECK-LE-NEXT:    rldic r4, r3, 2, 30
 ; CHECK-LE-NEXT:    li r6, -4096
 ; CHECK-LE-NEXT:    mr r31, r1
 ; CHECK-LE-NEXT:    addi r4, r4, 15
-; CHECK-LE-NEXT:    rldicl r4, r4, 60, 4
-; CHECK-LE-NEXT:    rldicl r4, r4, 4, 29
+; CHECK-LE-NEXT:    rotldi r4, r4, 60
+; CHECK-LE-NEXT:    rldic r4, r4, 4, 29
 ; CHECK-LE-NEXT:    neg r5, r4
 ; CHECK-LE-NEXT:    addi r4, r31, 48
 ; CHECK-LE-NEXT:    divd r7, r5, r6
 ; CHECK-LE-NEXT:    mulld r6, r7, r6
 ; CHECK-LE-NEXT:    sub r6, r5, r6
 ; CHECK-LE-NEXT:    add r5, r1, r5
 ; CHECK-LE-NEXT:    stdux r4, r1, r6
 ; CHECK-LE-NEXT:    cmpd r1, r5

 ; CHECK-P9-LE-LABEL: bar:
 ; CHECK-P9-LE:       # %bb.0:
 ; CHECK-P9-LE-NEXT:    std r31, -8(r1)
 ; CHECK-P9-LE-NEXT:    stdu r1, -48(r1)
 ; CHECK-P9-LE-NEXT:    rldic r4, r3, 2, 30
 ; CHECK-P9-LE-NEXT:    addi r4, r4, 15
 ; CHECK-P9-LE-NEXT:    li r7, -4096
 ; CHECK-P9-LE-NEXT:    mr r31, r1
-; CHECK-P9-LE-NEXT:    rldicl r4, r4, 60, 4
-; CHECK-P9-LE-NEXT:    rldicl r4, r4, 4, 29
+; CHECK-P9-LE-NEXT:    rotldi r4, r4, 60
+; CHECK-P9-LE-NEXT:    rldic r4, r4, 4, 29
 ; CHECK-P9-LE-NEXT:    neg r6, r4
 ; CHECK-P9-LE-NEXT:    addi r4, r31, 48
 ; CHECK-P9-LE-NEXT:    divd r8, r6, r7
 ; CHECK-P9-LE-NEXT:    add r5, r1, r6
 ; CHECK-P9-LE-NEXT:    mulld r7, r8, r7
 ; CHECK-P9-LE-NEXT:    sub r6, r6, r7
 ; CHECK-P9-LE-NEXT:    stdux r4, r1, r6
 ; CHECK-P9-LE-NEXT:    cmpd r1, r5

 ;
 ; CHECK-BE-LABEL: bar:
 ; CHECK-BE:       # %bb.0:
 ; CHECK-BE-NEXT:    std r31, -8(r1)
 ; CHECK-BE-NEXT:    stdu r1, -64(r1)
 ; CHECK-BE-NEXT:    rldic r4, r3, 2, 30
 ; CHECK-BE-NEXT:    li r6, -4096
 ; CHECK-BE-NEXT:    addi r4, r4, 15
-; CHECK-BE-NEXT:    rldicl r4, r4, 60, 4
+; CHECK-BE-NEXT:    rotldi r4, r4, 60
 ; CHECK-BE-NEXT:    mr r31, r1
-; CHECK-BE-NEXT:    rldicl r4, r4, 4, 29
+; CHECK-BE-NEXT:    rldic r4, r4, 4, 29
 ; CHECK-BE-NEXT:    neg r5, r4
 ; CHECK-BE-NEXT:    divd r7, r5, r6
 ; CHECK-BE-NEXT:    addi r4, r31, 64
 ; CHECK-BE-NEXT:    mulld r6, r7, r6
 ; CHECK-BE-NEXT:    sub r6, r5, r6
 ; CHECK-BE-NEXT:    add r5, r1, r5
 ; CHECK-BE-NEXT:    stdux r4, r1, r6
 ; CHECK-BE-NEXT:    cmpd r1, r5

 ; CHECK-LE:       # %bb.0:
 ; CHECK-LE-NEXT:    std r31, -8(r1)
 ; CHECK-LE-NEXT:    stdu r1, -48(r1)
 ; CHECK-LE-NEXT:    rldic r3, r3, 2, 30
 ; CHECK-LE-NEXT:    lis r4, -1
 ; CHECK-LE-NEXT:    mr r31, r1
 ; CHECK-LE-NEXT:    addi r3, r3, 15
 ; CHECK-LE-NEXT:    ori r4, r4, 0
-; CHECK-LE-NEXT:    rldicl r3, r3, 60, 4
-; CHECK-LE-NEXT:    rldicl r3, r3, 4, 29
+; CHECK-LE-NEXT:    rotldi r3, r3, 60
+; CHECK-LE-NEXT:    rldic r3, r3, 4, 29
 ; CHECK-LE-NEXT:    neg r5, r3
 ; CHECK-LE-NEXT:    addi r3, r31, 48
 ; CHECK-LE-NEXT:    divd r6, r5, r4
 ; CHECK-LE-NEXT:    mulld r6, r6, r4
 ; CHECK-LE-NEXT:    sub r6, r5, r6
 ; CHECK-LE-NEXT:    add r5, r1, r5
 ; CHECK-LE-NEXT:    stdux r3, r1, r6
 ; CHECK-LE-NEXT:    cmpd r1, r5

 ; CHECK-P9-LE:       # %bb.0:
 ; CHECK-P9-LE-NEXT:    std r31, -8(r1)
 ; CHECK-P9-LE-NEXT:    stdu r1, -48(r1)
 ; CHECK-P9-LE-NEXT:    rldic r3, r3, 2, 30
 ; CHECK-P9-LE-NEXT:    addi r3, r3, 15
 ; CHECK-P9-LE-NEXT:    lis r5, -1
 ; CHECK-P9-LE-NEXT:    ori r5, r5, 0
 ; CHECK-P9-LE-NEXT:    mr r31, r1
-; CHECK-P9-LE-NEXT:    rldicl r3, r3, 60, 4
-; CHECK-P9-LE-NEXT:    rldicl r3, r3, 4, 29
+; CHECK-P9-LE-NEXT:    rotldi r3, r3, 60
+; CHECK-P9-LE-NEXT:    rldic r3, r3, 4, 29
 ; CHECK-P9-LE-NEXT:    neg r6, r3
 ; CHECK-P9-LE-NEXT:    addi r3, r31, 48
 ; CHECK-P9-LE-NEXT:    divd r7, r6, r5
 ; CHECK-P9-LE-NEXT:    add r4, r1, r6
 ; CHECK-P9-LE-NEXT:    mulld r7, r7, r5
 ; CHECK-P9-LE-NEXT:    sub r6, r6, r7
 ; CHECK-P9-LE-NEXT:    stdux r3, r1, r6
 ; CHECK-P9-LE-NEXT:    cmpd r1, r4

 ;
 ; CHECK-BE-LABEL: f:
 ; CHECK-BE:       # %bb.0:
 ; CHECK-BE-NEXT:    std r31, -8(r1)
 ; CHECK-BE-NEXT:    stdu r1, -64(r1)
 ; CHECK-BE-NEXT:    rldic r3, r3, 2, 30
 ; CHECK-BE-NEXT:    lis r4, -1
 ; CHECK-BE-NEXT:    addi r3, r3, 15
-; CHECK-BE-NEXT:    rldicl r3, r3, 60, 4
+; CHECK-BE-NEXT:    rotldi r3, r3, 60
 ; CHECK-BE-NEXT:    ori r4, r4, 0
-; CHECK-BE-NEXT:    rldicl r3, r3, 4, 29
+; CHECK-BE-NEXT:    rldic r3, r3, 4, 29
 ; CHECK-BE-NEXT:    mr r31, r1
 ; CHECK-BE-NEXT:    neg r5, r3
 ; CHECK-BE-NEXT:    divd r6, r5, r4
 ; CHECK-BE-NEXT:    addi r3, r31, 64
 ; CHECK-BE-NEXT:    mulld r6, r6, r4
 ; CHECK-BE-NEXT:    sub r6, r5, r6
 ; CHECK-BE-NEXT:    add r5, r1, r5
 ; CHECK-BE-NEXT:    stdux r3, r1, r6

llvm/test/CodeGen/PowerPC/stack-clash-prologue.ll

 ; CHECK-LE-NEXT:    .cfi_offset r31, -8
 ; CHECK-LE-NEXT:    .cfi_offset r30, -16
 ; CHECK-LE-NEXT:    clrldi r3, r3, 32
 ; CHECK-LE-NEXT:    lis r5, 1
 ; CHECK-LE-NEXT:    mr r31, r1
 ; CHECK-LE-NEXT:    li r6, 1
 ; CHECK-LE-NEXT:    addi r3, r3, 15
 ; CHECK-LE-NEXT:    ori r5, r5, 0
-; CHECK-LE-NEXT:    rldicl r3, r3, 60, 4
+; CHECK-LE-NEXT:    rotldi r3, r3, 60
 ; CHECK-LE-NEXT:    sldi r4, r4, 2
 ; CHECK-LE-NEXT:    add r5, r31, r5
-; CHECK-LE-NEXT:    rldicl r3, r3, 4, 31
+; CHECK-LE-NEXT:    rldic r3, r3, 4, 31
 ; CHECK-LE-NEXT:    stwx r6, r5, r4
 ; CHECK-LE-NEXT:    li r4, -32768
 ; CHECK-LE-NEXT:    neg r7, r3
 ; CHECK-LE-NEXT:    ld r3, 0(r1)
 ; CHECK-LE-NEXT:    and r4, r7, r4
 ; CHECK-LE-NEXT:    mr r7, r4
 ; CHECK-LE-NEXT:    li r4, -4096
 ; CHECK-LE-NEXT:    divd r5, r7, r4

 ; CHECK-BE-NEXT:    .cfi_def_cfa_register r30
 ; CHECK-BE-NEXT:    .cfi_offset r31, -8
 ; CHECK-BE-NEXT:    .cfi_offset r30, -16
 ; CHECK-BE-NEXT:    clrldi r3, r3, 32
 ; CHECK-BE-NEXT:    lis r5, 1
 ; CHECK-BE-NEXT:    addi r3, r3, 15
 ; CHECK-BE-NEXT:    mr r31, r1
 ; CHECK-BE-NEXT:    ori r5, r5, 0
-; CHECK-BE-NEXT:    rldicl r3, r3, 60, 4
+; CHECK-BE-NEXT:    rotldi r3, r3, 60
 ; CHECK-BE-NEXT:    add r5, r31, r5
 ; CHECK-BE-NEXT:    sldi r4, r4, 2
 ; CHECK-BE-NEXT:    li r6, 1
-; CHECK-BE-NEXT:    rldicl r3, r3, 4, 31
+; CHECK-BE-NEXT:    rldic r3, r3, 4, 31
 ; CHECK-BE-NEXT:    stwx r6, r5, r4
 ; CHECK-BE-NEXT:    neg r7, r3
 ; CHECK-BE-NEXT:    li r4, -32768
 ; CHECK-BE-NEXT:    and r4, r7, r4
 ; CHECK-BE-NEXT:    ld r3, 0(r1)
 ; CHECK-BE-NEXT:    mr r7, r4
 ; CHECK-BE-NEXT:    li r4, -4096
 ; CHECK-BE-NEXT:    divd r5, r7, r4