diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -355,11 +355,6 @@
 private:
     bool trySETCC(SDNode *N);
     bool tryAsSingleRLDICL(SDNode *N);
-    bool tryAsSingleRLDICR(SDNode *N);
-    bool tryAsSingleRLWINM(SDNode *N);
-    bool tryAsSingleRLWINM8(SDNode *N);
-    bool tryAsSingleRLWIMI(SDNode *N);
-    bool tryAsPairOfRLDICL(SDNode *N);
     bool tryAsSingleRLDIMI(SDNode *N);
 
     void PeepholePPC64();
@@ -1255,10 +1250,6 @@
         uint64_t Mask = V.getConstantOperandVal(1);
 
         const SmallVector<ValueBit, 64> *LHSBits;
-        // Mark this as interesting, only if the LHS was also interesting. This
-        // prevents the overall procedure from matching a single immediate 'and'
-        // (which is non-optimal because such an and might be folded with other
-        // things if we don't select it here).
         std::tie(Interesting, LHSBits) = getValueBits(V.getOperand(0), NumBits);
 
         for (unsigned i = 0; i < NumBits; ++i)
@@ -1272,8 +1263,12 @@
             else
               Bits[i] = ValueBit(ValueBit::ConstZero);
           }
-
-        return std::make_pair(Interesting, &Bits);
+        // If the LHS isn't interesting, we should take care whether it's
+        // optimal to handle such a single immediate `and` here. Record the 
+        // LHS of the `AND` instruction for later analyzing.
+        if (!Interesting)
+          LHSofSingleAnd = V.getOperand(0);
+        return std::make_pair(Interesting = true, &Bits);
       }
       break;
     case ISD::OR: {
@@ -1701,6 +1696,39 @@
     return ~Mask;
   }
 
+  // This method checks if it's optimal to select the single `and` with
+  // bit-permutation-based stratege. Considering the cases where `and` can be
+  // folded with its LHS, determine which stratege use less instruction. Return
+  // true if bit-permutation-based stratege is optimal.
+  bool isBitPermOptimal(unsigned AndImm, unsigned NumSelectInsts,
+                        unsigned NumBitPermInsts) {
+    if (!LHSofSingleAnd)
+      return true;
+    switch (LHSofSingleAnd.getOpcode()) {
+    case ISD::XOR:
+      // Consider the transformation, and(not, AndImm) -> andc.
+      if (isa<ConstantSDNode>(LHSofSingleAnd.getOperand(1)) &&
+          cast<ConstantSDNode>(LHSofSingleAnd.getOperand(1))->getSExtValue() ==
+              -1)
+        // Compare which kind of conversion is better.
+        if ((NumBitPermInsts + /* xor */ 1) > (NumSelectInsts + /* andc */ 1))
+          return false;
+      break;
+    case ISD::ANY_EXTEND:
+      // and(any_extend(srl), AndImm) -> rldicl
+      if (isMask_64(AndImm) &&
+          LHSofSingleAnd.getOperand(0).getOpcode() == ISD::SRL)
+        return false;
+      break;
+    case ISD::ROTL:
+      // and(rotl, AndImm) -> rlwnm
+      if (isShiftedMask_32(AndImm) || isShiftedMask_32(~AndImm))
+        return false;
+      break;
+    }
+    return true;
+  }
+
   // This method extends an input value to 64 bit if input is 32-bit integer.
   // While selecting instructions in BitPermutationSelector in 64-bit mode,
   // an input value can be a 32-bit integer if a ZERO_EXTEND node is included.
@@ -1773,6 +1801,16 @@
                              (unsigned) (ANDIMask != 0 && ANDISMask != 0) +
                              (unsigned) (bool) Res;
 
+      unsigned NumSelectInsts = 0;
+      selectI64Imm(CurDAG, dl, Mask, &NumSelectInsts);
+      if (!isBitPermOptimal(Mask, NumSelectInsts,
+                            NumAndInsts < VRI.NumGroups ? NumAndInsts
+                                                        : VRI.NumGroups)) {
+        IsBitPermOptimal = false;
+        LLVM_DEBUG(dbgs() << "\t\t\t\tDon't use bit-permutation-based ISel.\n");
+        return;
+      }
+
       LLVM_DEBUG(dbgs() << "\t\trotation groups for " << VRI.V.getNode()
                         << " RL: " << VRI.RLAmt << ":"
                         << "\n\t\t\tisel using masking: " << NumAndInsts
@@ -1839,6 +1877,10 @@
 
     // Take care of cases that should use andi/andis first.
     SelectAndParts32(dl, Res, InstCnt);
+    // Check if it's optimal to handle the input instructions with
+    // bit-permutation-based ISel.
+    if (!IsBitPermOptimal)
+      return nullptr;
 
     // If we've not yet selected a 'starting' instruction, and we have no zeros
     // to fill in, select the (Value, RLAmt) with the highest priority (largest
@@ -1927,7 +1969,8 @@
       return 1;
 
     if ((!IsIns && (InstMaskEnd == 63 || InstMaskStart == 0)) ||
-        InstMaskEnd == 63 - RLAmt)
+        InstMaskEnd == 63 - RLAmt ||
+        (InstMaskStart >= 32 && InstMaskStart <= InstMaskEnd))
       return 1;
 
     return 2;
@@ -1979,6 +2022,14 @@
       return SDValue(CurDAG->getMachineNode(PPC::RLDIC, dl, MVT::i64, Ops), 0);
     }
 
+    if (InstMaskStart >= 32 && InstMaskStart <= InstMaskEnd) {
+      SDValue Ops[] = {ExtendToInt64(V, dl), getI32Imm(RLAmt, dl),
+                       getI32Imm(InstMaskStart - 32, dl),
+                       getI32Imm(InstMaskEnd - 32, dl)};
+      return SDValue(CurDAG->getMachineNode(PPC::RLWINM8, dl, MVT::i64, Ops),
+                     0);
+    }
+
     // We cannot do this with a single instruction, so we'll use two. The
     // problem is that we're not free to choose both a rotation amount and mask
     // start and end independently. We can choose an arbitrary mask start and
@@ -2047,6 +2098,51 @@
     return SelectRotMaskIns64(Base, V, dl, RLAmt2, false, MaskStart, MaskEnd);
   }
 
+  SDValue tryAsPairRot(BitGroup BG1, BitGroup BG2, const SDLoc &dl) {
+    if (BG1.RLAmt || BG2.RLAmt || BG1.StartIdx >= BG1.EndIdx ||
+        BG2.StartIdx >= BG2.EndIdx || BG1.EndIdx >= BG2.StartIdx)
+      return SDValue();
+    SDValue RotVal;
+    // RLDICL + RLDICL
+    if (BG1.StartIdx == 0) {
+      SDValue Ops1[] = {ExtendToInt64(BG1.V, dl),
+                        getI32Imm(64 - BG2.StartIdx, dl),
+                        getI32Imm(BG2.StartIdx - BG1.EndIdx - 1, dl)};
+      RotVal =
+          SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Ops1), 0);
+      SDValue Ops2[] = {ExtendToInt64(RotVal, dl), getI32Imm(BG2.StartIdx, dl),
+                        getI32Imm(63 - BG2.EndIdx, dl)};
+      return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Ops2),
+                     0);
+    }
+    // RLDICL + RLDICR
+    else if (BG2.EndIdx == 63) {
+      SDValue Ops1[] = {ExtendToInt64(BG1.V, dl),
+                        getI32Imm(64 - BG2.StartIdx, dl),
+                        getI32Imm(BG2.StartIdx - BG1.EndIdx - 1, dl)};
+      RotVal =
+          SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Ops1), 0);
+      SDValue Ops2[] = {ExtendToInt64(RotVal, dl), getI32Imm(BG2.StartIdx, dl),
+                        getI32Imm(63 - BG1.StartIdx, dl)};
+      return SDValue(CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, Ops2),
+                     0);
+    }
+    // RLWINM + RLWINM
+    else if (BG2.EndIdx < 32) {
+      SDValue Ops1[] = {ExtendToInt64(BG1.V, dl), getI32Imm(0, dl),
+                        getI32Imm(31 - BG1.EndIdx, dl),
+                        getI32Imm(31 - BG2.StartIdx, dl)};
+      RotVal =
+          SDValue(CurDAG->getMachineNode(PPC::RLWINM8, dl, MVT::i64, Ops1), 0);
+      SDValue Ops2[] = {ExtendToInt64(RotVal, dl), getI32Imm(0, dl),
+                        getI32Imm(31 - BG2.EndIdx, dl),
+                        getI32Imm(31 - BG1.StartIdx, dl)};
+      return SDValue(CurDAG->getMachineNode(PPC::RLWINM8, dl, MVT::i64, Ops2),
+                     0);
+    }
+    return SDValue();
+  }
+
   void SelectAndParts64(const SDLoc &dl, SDValue &Res, unsigned *InstCnt) {
     if (BPermRewriterNoMasking)
       return;
@@ -2062,6 +2158,7 @@
 
     for (ValueRotInfo &VRI : ValueRotsVec) {
       uint64_t Mask = 0;
+      SmallVector<BitGroup, 16> MatchingBitGroups;
 
       // We need to add to the mask all bits from the associated bit groups.
       // If Repl32 is false, we need to add bits from bit groups that have
@@ -2092,6 +2189,7 @@
         if (!MatchingBG(BG))
           continue;
 
+        MatchingBitGroups.push_back(BG);
         if (BG.StartIdx <= BG.EndIdx) {
           for (unsigned i = BG.StartIdx; i <= BG.EndIdx; ++i)
             Mask |= (UINT64_C(1) << i);
@@ -2138,6 +2236,36 @@
         FirstBG = false;
       }
 
+      // Take care of cases that should select a pair of bit groups directly
+      // with 2 instructions.
+      if (MatchingBitGroups.size() == 2 && NumAndInsts > 2) {
+        BitGroup BG1 = MatchingBitGroups[0], BG2 = MatchingBitGroups[1];
+        SDValue PairRotVal = tryAsPairRot(BG1, BG2, dl);
+        if (PairRotVal) {
+          if (InstCnt)
+            *InstCnt += 2;
+          if (!Res)
+            Res = PairRotVal;
+          else
+            Res =
+                SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
+                                               ExtendToInt64(Res, dl), PairRotVal),
+                        0);
+          // Now, remove all groups with this underlying value and rotation
+          // factor.
+          eraseMatchingBitGroups(MatchingBG);
+          continue;
+        }
+      }
+
+      if (!isBitPermOptimal(Mask, NumOfSelectInsts,
+                            NumAndInsts < NumRLInsts ? NumAndInsts
+                                                     : NumRLInsts)) {
+        IsBitPermOptimal = false;
+        LLVM_DEBUG(dbgs() << "\t\t\t\tDon't use bit-permutation-based ISel.\n");
+        return;
+      }
+
       LLVM_DEBUG(dbgs() << "\t\trotation groups for " << VRI.V.getNode()
                         << " RL: " << VRI.RLAmt << (VRI.Repl32 ? " (32):" : ":")
                         << "\n\t\t\tisel using masking: " << NumAndInsts
@@ -2225,6 +2353,10 @@
 
     // Take care of cases that should use andi/andis first.
     SelectAndParts64(dl, Res, InstCnt);
+    // Check if it's optimal to handle the input instructions with
+    // bit-permutation-based ISel.
+    if (!IsBitPermOptimal)
+      return nullptr;
 
     // If we've not yet selected a 'starting' instruction, and we have no zeros
     // to fill in, select the (Value, RLAmt) with the highest priority (largest
@@ -2390,6 +2522,8 @@
   SmallVector<ValueBit, 64> Bits;
 
   bool NeedMask = false;
+  bool IsBitPermOptimal = true;
+  SDValue LHSofSingleAnd;
   SmallVector<unsigned, 64> RLAmt;
 
   SmallVector<BitGroup, 16> BitGroups;
@@ -4380,176 +4514,19 @@
   return true;
 }
 
-bool PPCDAGToDAGISel::tryAsSingleRLWINM(SDNode *N) {
-  assert(N->getOpcode() == ISD::AND && "ISD::AND SDNode expected");
-  unsigned Imm;
-  if (!isInt32Immediate(N->getOperand(1), Imm))
-    return false;
-
-  SDLoc dl(N);
-  SDValue Val = N->getOperand(0);
-  unsigned SH, MB, ME;
-  // If this is an and of a value rotated between 0 and 31 bits and then and'd
-  // with a mask, emit rlwinm
-  if (isRotateAndMask(Val.getNode(), Imm, false, SH, MB, ME)) {
-    Val = Val.getOperand(0);
-    SDValue Ops[] = {Val, getI32Imm(SH, dl), getI32Imm(MB, dl),
-                     getI32Imm(ME, dl)};
-    CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
-    return true;
-  }
-
-  // If this is just a masked value where the input is not handled, and
-  // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
-  if (isRunOfOnes(Imm, MB, ME) && Val.getOpcode() != ISD::ROTL) {
-    SDValue Ops[] = {Val, getI32Imm(0, dl), getI32Imm(MB, dl),
-                     getI32Imm(ME, dl)};
-    CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
-    return true;
-  }
-
-  // AND X, 0 -> 0, not "rlwinm 32".
-  if (Imm == 0) {
-    ReplaceUses(SDValue(N, 0), N->getOperand(1));
-    return true;
-  }
-
-  return false;
-}
-
-bool PPCDAGToDAGISel::tryAsSingleRLWINM8(SDNode *N) {
-  assert(N->getOpcode() == ISD::AND && "ISD::AND SDNode expected");
-  uint64_t Imm64;
-  if (!isInt64Immediate(N->getOperand(1).getNode(), Imm64))
-    return false;
-
-  unsigned MB, ME;
-  if (isRunOfOnes64(Imm64, MB, ME) && MB >= 32 && MB <= ME) {
-    //                MB  ME
-    // +----------------------+
-    // |xxxxxxxxxxx00011111000|
-    // +----------------------+
-    //  0         32         64
-    // We can only do it if the MB is larger than 32 and MB <= ME
-    // as RLWINM will replace the contents of [0 - 32) with [32 - 64) even
-    // we didn't rotate it.
-    SDLoc dl(N);
-    SDValue Ops[] = {N->getOperand(0), getI64Imm(0, dl), getI64Imm(MB - 32, dl),
-                     getI64Imm(ME - 32, dl)};
-    CurDAG->SelectNodeTo(N, PPC::RLWINM8, MVT::i64, Ops);
-    return true;
-  }
-
-  return false;
-}
-
-bool PPCDAGToDAGISel::tryAsPairOfRLDICL(SDNode *N) {
-  assert(N->getOpcode() == ISD::AND && "ISD::AND SDNode expected");
-  uint64_t Imm64;
-  if (!isInt64Immediate(N->getOperand(1).getNode(), Imm64))
-    return false;
-
-  // Do nothing if it is 16-bit imm as the pattern in the .td file handle
-  // it well with "andi.".
-  if (isUInt<16>(Imm64))
-    return false;
-
-  SDLoc Loc(N);
-  SDValue Val = N->getOperand(0);
-
-  // Optimized with two rldicl's as follows:
-  // Add missing bits on left to the mask and check that the mask is a
-  // wrapped run of ones, i.e.
-  // Change pattern |0001111100000011111111|
-  //             to |1111111100000011111111|.
-  unsigned NumOfLeadingZeros = countLeadingZeros(Imm64);
-  if (NumOfLeadingZeros != 0)
-    Imm64 |= maskLeadingOnes<uint64_t>(NumOfLeadingZeros);
-
-  unsigned MB, ME;
-  if (!isRunOfOnes64(Imm64, MB, ME))
-    return false;
-
-  //         ME     MB                   MB-ME+63
-  // +----------------------+     +----------------------+
-  // |1111111100000011111111| ->  |0000001111111111111111|
-  // +----------------------+     +----------------------+
-  //  0                    63      0                    63
-  // There are ME + 1 ones on the left and (MB - ME + 63) & 63 zeros in between.
-  unsigned OnesOnLeft = ME + 1;
-  unsigned ZerosInBetween = (MB - ME + 63) & 63;
-  // Rotate left by OnesOnLeft (so leading ones are now trailing ones) and clear
-  // on the left the bits that are already zeros in the mask.
-  Val = SDValue(CurDAG->getMachineNode(PPC::RLDICL, Loc, MVT::i64, Val,
-                                       getI64Imm(OnesOnLeft, Loc),
-                                       getI64Imm(ZerosInBetween, Loc)),
-                0);
-  //        MB-ME+63                      ME     MB
-  // +----------------------+     +----------------------+
-  // |0000001111111111111111| ->  |0001111100000011111111|
-  // +----------------------+     +----------------------+
-  //  0                    63      0                    63
-  // Rotate back by 64 - OnesOnLeft to undo previous rotate. Then clear on the
-  // left the number of ones we previously added.
-  SDValue Ops[] = {Val, getI64Imm(64 - OnesOnLeft, Loc),
-                   getI64Imm(NumOfLeadingZeros, Loc)};
-  CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops);
-  return true;
-}
-
-bool PPCDAGToDAGISel::tryAsSingleRLWIMI(SDNode *N) {
-  assert(N->getOpcode() == ISD::AND && "ISD::AND SDNode expected");
-  unsigned Imm;
-  if (!isInt32Immediate(N->getOperand(1), Imm))
-    return false;
-
-  SDValue Val = N->getOperand(0);
-  unsigned Imm2;
-  // ISD::OR doesn't get all the bitfield insertion fun.
-  // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) might be a
-  // bitfield insert.
-  if (Val.getOpcode() != ISD::OR || !isInt32Immediate(Val.getOperand(1), Imm2))
-    return false;
-
-  // The idea here is to check whether this is equivalent to:
-  //   (c1 & m) | (x & ~m)
-  // where m is a run-of-ones mask. The logic here is that, for each bit in
-  // c1 and c2:
-  //  - if both are 1, then the output will be 1.
-  //  - if both are 0, then the output will be 0.
-  //  - if the bit in c1 is 0, and the bit in c2 is 1, then the output will
-  //    come from x.
-  //  - if the bit in c1 is 1, and the bit in c2 is 0, then the output will
-  //    be 0.
-  //  If that last condition is never the case, then we can form m from the
-  //  bits that are the same between c1 and c2.
-  unsigned MB, ME;
-  if (isRunOfOnes(~(Imm ^ Imm2), MB, ME) && !(~Imm & Imm2)) {
-    SDLoc dl(N);
-    SDValue Ops[] = {Val.getOperand(0), Val.getOperand(1), getI32Imm(0, dl),
-                     getI32Imm(MB, dl), getI32Imm(ME, dl)};
-    ReplaceNode(N, CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops));
-    return true;
-  }
-
-  return false;
-}
-
 bool PPCDAGToDAGISel::tryAsSingleRLDICL(SDNode *N) {
   assert(N->getOpcode() == ISD::AND && "ISD::AND SDNode expected");
   uint64_t Imm64;
   if (!isInt64Immediate(N->getOperand(1).getNode(), Imm64) || !isMask_64(Imm64))
     return false;
 
-  // If this is a 64-bit zero-extension mask, emit rldicl.
-  unsigned MB = 64 - countTrailingOnes(Imm64);
-  unsigned SH = 0;
-  unsigned Imm;
   SDValue Val = N->getOperand(0);
-  SDLoc dl(N);
-
-  if (Val.getOpcode() == ISD::ANY_EXTEND) {
+  if (N->getOperand(0).getOpcode() == ISD::ANY_EXTEND) {
+    // If this is a 64-bit zero-extension mask, emit rldicl.
+    unsigned MB = 64 - countTrailingOnes(Imm64);
+    unsigned Imm;
     auto Op0 = Val.getOperand(0);
+    SDLoc dl(N);
     if (Op0.getOpcode() == ISD::SRL &&
         isInt32Immediate(Op0.getOperand(1).getNode(), Imm) && Imm <= MB) {
 
@@ -4561,43 +4538,13 @@
                                            IDVal, Op0.getOperand(0),
                                            getI32Imm(1, dl)),
                     0);
-      SH = 64 - Imm;
+      unsigned SH = 64 - Imm;
+      SDValue Ops[] = {Val, getI32Imm(SH, dl), getI32Imm(MB, dl)};
+      CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops);
+      return true;
     }
   }
-
-  // If the operand is a logical right shift, we can fold it into this
-  // instruction: rldicl(rldicl(x, 64-n, n), 0, mb) -> rldicl(x, 64-n, mb)
-  // for n <= mb. The right shift is really a left rotate followed by a
-  // mask, and this mask is a more-restrictive sub-mask of the mask implied
-  // by the shift.
-  if (Val.getOpcode() == ISD::SRL &&
-      isInt32Immediate(Val.getOperand(1).getNode(), Imm) && Imm <= MB) {
-    assert(Imm < 64 && "Illegal shift amount");
-    Val = Val.getOperand(0);
-    SH = 64 - Imm;
-  }
-
-  SDValue Ops[] = {Val, getI32Imm(SH, dl), getI32Imm(MB, dl)};
-  CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops);
-  return true;
-}
-
-bool PPCDAGToDAGISel::tryAsSingleRLDICR(SDNode *N) {
-  assert(N->getOpcode() == ISD::AND && "ISD::AND SDNode expected");
-  uint64_t Imm64;
-  if (!isInt64Immediate(N->getOperand(1).getNode(), Imm64) ||
-      !isMask_64(~Imm64))
-    return false;
-
-  // If this is a negated 64-bit zero-extension mask,
-  // i.e. the immediate is a sequence of ones from most significant side
-  // and all zero for reminder, we should use rldicr.
-  unsigned MB = 63 - countTrailingOnes(~Imm64);
-  unsigned SH = 0;
-  SDLoc dl(N);
-  SDValue Ops[] = {N->getOperand(0), getI32Imm(SH, dl), getI32Imm(MB, dl)};
-  CurDAG->SelectNodeTo(N, PPC::RLDICR, MVT::i64, Ops);
-  return true;
+  return false;
 }
 
 bool PPCDAGToDAGISel::tryAsSingleRLDIMI(SDNode *N) {
@@ -4886,9 +4833,8 @@
   }
 
   case ISD::AND:
-    // If this is an 'and' with a mask, try to emit rlwinm/rldicl/rldicr
-    if (tryAsSingleRLWINM(N) || tryAsSingleRLWIMI(N) || tryAsSingleRLDICL(N) ||
-        tryAsSingleRLDICR(N) || tryAsSingleRLWINM8(N) || tryAsPairOfRLDICL(N))
+    // Try to do this transformation: and(any_extend(srl), C1) -> rldicl
+    if (tryAsSingleRLDICL(N))
       return;
 
     // Other cases are autogenerated.
diff --git a/llvm/test/CodeGen/PowerPC/2016-04-17-combine.ll b/llvm/test/CodeGen/PowerPC/2016-04-17-combine.ll
--- a/llvm/test/CodeGen/PowerPC/2016-04-17-combine.ll
+++ b/llvm/test/CodeGen/PowerPC/2016-04-17-combine.ll
@@ -7,8 +7,8 @@
 %typ = type { i32, i32 }
 
 ; On release builds, it doesn't crash, spewing nonsense instead.
-; To make sure it works, check that rldicl is still alive.
-; CHECK: rldicl
+; To make sure it works, check that rldic is still alive.
+; CHECK: rldic
 ; Also, in release, it emits a COPY from a 32-bit register to
 ; a 64-bit register, which happens to be emitted as cror [!]
 ; by the confused CodeGen.  Just to be sure, check there isn't one.
diff --git a/llvm/test/CodeGen/PowerPC/Frames-dyn-alloca.ll b/llvm/test/CodeGen/PowerPC/Frames-dyn-alloca.ll
--- a/llvm/test/CodeGen/PowerPC/Frames-dyn-alloca.ll
+++ b/llvm/test/CodeGen/PowerPC/Frames-dyn-alloca.ll
@@ -46,9 +46,9 @@
 ; PPC64-LINUX-NEXT: rldic 3, 3, 2, 30
 ; PPC64-LINUX-NEXT: mr 31, 1
 ; PPC64-LINUX-NEXT: addi 3, 3, 15
-; PPC64-LINUX-NEXT: rldicl 3, 3, 60, 4
+; PPC64-LINUX-NEXT: rotldi 3, 3, 60
 ; PPC64-LINUX-NEXT: addi 4, 31, 64
-; PPC64-LINUX-NEXT: rldicl 3, 3, 4, 29
+; PPC64-LINUX-NEXT: rldic 3, 3, 4, 29
 ; PPC64-LINUX-NEXT: neg 3, 3
 ; PPC64-LINUX-NEXT: stdux 4, 1, 3
 
@@ -84,8 +84,8 @@
 ; PPC64-AIX-NEXT: mr 31, 1
 ; PPC64-AIX-NEXT: addi 3, 3, 15
 ; PPC64-AIX-NEXT: addi 4, 31, 64
-; PPC64-AIX-NEXT: rldicl 3, 3, 60, 4 
-; PPC64-AIX-NEXT: rldicl 3, 3, 4, 29
+; PPC64-AIX-NEXT: rotldi 3, 3, 60
+; PPC64-AIX-NEXT: rldic 3, 3, 4, 29
 ; PPC64-AIX-NEXT: neg 3, 3
 ; PPC64-AIX-NEXT: stdux 4, 1, 3
 
diff --git a/llvm/test/CodeGen/PowerPC/and-mask.ll b/llvm/test/CodeGen/PowerPC/and-mask.ll
--- a/llvm/test/CodeGen/PowerPC/and-mask.ll
+++ b/llvm/test/CodeGen/PowerPC/and-mask.ll
@@ -15,8 +15,8 @@
 define i64 @test2(i64 %a) {
 ; CHECK-LABEL: test2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rldicl 3, 3, 61, 2
-; CHECK-NEXT:    rotldi 3, 3, 3
+; CHECK-NEXT:    li 4, -7
+; CHECK-NEXT:    and 3, 3, 4
 ; CHECK-NEXT:    blr
   %and = and i64 %a, -7
   ret i64 %and
@@ -26,8 +26,8 @@
 define i64 @test3(i64 %a) {
 ; CHECK-LABEL: test3:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    rldicl 3, 3, 42, 22
-; CHECK-NEXT:    rldicl 3, 3, 22, 16
+; CHECK-NEXT:    rotldi 3, 3, 42
+; CHECK-NEXT:    rldic 3, 3, 22, 16
 ; CHECK-NEXT:    blr
   %and = and i64 %a, 281474972516352
   ret i64 %and
@@ -59,9 +59,8 @@
 define i64 @test6(i64 %a) {
 ; CHECK-LABEL: test6:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lis 4, 16320
-; CHECK-NEXT:    ori 4, 4, 65504
-; CHECK-NEXT:    and 3, 3, 4
+; CHECK-NEXT:    rlwinm 3, 3, 0, 16, 9
+; CHECK-NEXT:    rlwinm 3, 3, 0, 2, 26
 ; CHECK-NEXT:    blr
   %and = and i64 %a, 1069613024
   ret i64 %and
@@ -82,10 +81,8 @@
 define i64 @test8(i64 %a) {
 ; CHECK-LABEL: test8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lis 4, 480
-; CHECK-NEXT:    ori 4, 4, 1023
-; CHECK-NEXT:    rotldi 4, 4, 54
-; CHECK-NEXT:    and 3, 3, 4
+; CHECK-NEXT:    rldicl 3, 3, 10, 39
+; CHECK-NEXT:    rldicr 3, 3, 54, 52
 ; CHECK-NEXT:    blr
   %and = and i64 %a, 18428729675200100352
   ret i64 %and
@@ -95,10 +92,9 @@
 define i64 @test9(i64 %a) {
 ; CHECK-LABEL: test9:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lis 4, -16
-; CHECK-NEXT:    ori 4, 4, 63
-; CHECK-NEXT:    rldic 4, 4, 13, 19
-; CHECK-NEXT:    and 3, 3, 4
+; CHECK-NEXT:    rotldi 4, 3, 31
+; CHECK-NEXT:    rlwinm 3, 3, 0, 13, 18
+; CHECK-NEXT:    rldimi 3, 4, 33, 19
 ; CHECK-NEXT:    blr
   %and = and i64 %a, 35175782670336
   ret i64 %and
@@ -108,12 +104,12 @@
 define i64 @test10(i64 %a) {
 ; CHECK-LABEL: test10:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    lis 4, 252
-; CHECK-NEXT:    ori 4, 4, 8191
-; CHECK-NEXT:    rldic 4, 4, 32, 8
-; CHECK-NEXT:    oris 4, 4, 57351
-; CHECK-NEXT:    ori 4, 4, 57344
-; CHECK-NEXT:    and 3, 3, 4
+; CHECK-NEXT:    rotldi 5, 3, 35
+; CHECK-NEXT:    rlwinm 4, 3, 0, 13, 18
+; CHECK-NEXT:    rldimi 4, 5, 29, 19
+; CHECK-NEXT:    rotldi 3, 3, 14
+; CHECK-NEXT:    rldimi 4, 3, 50, 8
+; CHECK-NEXT:    mr 3, 4
 ; CHECK-NEXT:    blr
   %and = and i64 %a, 70966877966819328
   ret i64 %and
diff --git a/llvm/test/CodeGen/PowerPC/andc.ll b/llvm/test/CodeGen/PowerPC/andc.ll
--- a/llvm/test/CodeGen/PowerPC/andc.ll
+++ b/llvm/test/CodeGen/PowerPC/andc.ll
@@ -16,8 +16,8 @@
 define i1 @and_cmp_const(i32 %x) {
 ; CHECK-LABEL: and_cmp_const:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    li 4, 43
-; CHECK-NEXT:    andc 3, 4, 3
+; CHECK-NEXT:    not 3, 3
+; CHECK-NEXT:    andi. 3, 3, 43
 ; CHECK-NEXT:    cntlzw 3, 3
 ; CHECK-NEXT:    rlwinm 3, 3, 27, 31, 31
 ; CHECK-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll b/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll
--- a/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-to-int-to-fp.ll
@@ -98,14 +98,14 @@
 ; PPC64-NEXT:    addi 6, 6, 2047
 ; PPC64-NEXT:    or 4, 7, 4
 ; PPC64-NEXT:    or 6, 6, 3
-; PPC64-NEXT:    rldicl 4, 4, 53, 11
+; PPC64-NEXT:    rotldi 4, 4, 53
 ; PPC64-NEXT:    rldicr 6, 6, 0, 52
 ; PPC64-NEXT:    bc 12, 1, .LBB2_4
 ; PPC64-NEXT:  # %bb.3: # %entry
 ; PPC64-NEXT:    ori 6, 3, 0
 ; PPC64-NEXT:    b .LBB2_4
 ; PPC64-NEXT:  .LBB2_4: # %entry
-; PPC64-NEXT:    rldicl 4, 4, 11, 1
+; PPC64-NEXT:    rldic 4, 4, 11, 1
 ; PPC64-NEXT:    cmpdi 3, 0
 ; PPC64-NEXT:    std 6, -32(1)
 ; PPC64-NEXT:    bc 12, 5, .LBB2_6
diff --git a/llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll b/llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
--- a/llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
+++ b/llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
@@ -7,7 +7,7 @@
   %2 = zext i32 %1 to i64
   %3 = shl i64 %2, 48
   %4 = ashr exact i64 %3, 48
-; CHECK: RLWINM8 killed {{[^,]+}}, 0, 16, 27
+; CHECK: RLWINM8 {{[^,]+}}, 0, 16, 27
 ; CHECK: CMPLDI
 ; CHECK: BCC
 
diff --git a/llvm/test/CodeGen/PowerPC/popcnt-zext.ll b/llvm/test/CodeGen/PowerPC/popcnt-zext.ll
--- a/llvm/test/CodeGen/PowerPC/popcnt-zext.ll
+++ b/llvm/test/CodeGen/PowerPC/popcnt-zext.ll
@@ -14,21 +14,21 @@
 ; SLOW-NEXT:    clrlwi 5, 3, 24
 ; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 85
-; SLOW-NEXT:    lis 4, 13107
 ; SLOW-NEXT:    sub 3, 5, 3
-; SLOW-NEXT:    ori 4, 4, 13107
-; SLOW-NEXT:    rotlwi 5, 3, 30
-; SLOW-NEXT:    and 3, 3, 4
-; SLOW-NEXT:    andis. 4, 5, 13107
-; SLOW-NEXT:    andi. 5, 5, 13107
-; SLOW-NEXT:    or 4, 5, 4
-; SLOW-NEXT:    add 3, 3, 4
-; SLOW-NEXT:    lis 5, 3855
-; SLOW-NEXT:    srwi 4, 3, 4
-; SLOW-NEXT:    add 3, 3, 4
+; SLOW-NEXT:    andis. 5, 3, 13107
+; SLOW-NEXT:    andi. 6, 3, 13107
+; SLOW-NEXT:    rotlwi 3, 3, 30
+; SLOW-NEXT:    or 5, 6, 5
+; SLOW-NEXT:    andis. 6, 3, 13107
+; SLOW-NEXT:    andi. 3, 3, 13107
+; SLOW-NEXT:    or 3, 3, 6
+; SLOW-NEXT:    add 3, 5, 3
+; SLOW-NEXT:    srwi 5, 3, 4
+; SLOW-NEXT:    add 3, 3, 5
 ; SLOW-NEXT:    lis 4, 257
-; SLOW-NEXT:    ori 5, 5, 3855
-; SLOW-NEXT:    and 3, 3, 5
+; SLOW-NEXT:    andis. 5, 3, 3855
+; SLOW-NEXT:    andi. 3, 3, 3855
+; SLOW-NEXT:    or 3, 3, 5
 ; SLOW-NEXT:    ori 4, 4, 257
 ; SLOW-NEXT:    mullw 3, 3, 4
 ; SLOW-NEXT:    srwi 3, 3, 24
@@ -50,21 +50,21 @@
 ; SLOW-NEXT:    clrlwi 5, 3, 24
 ; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 85
-; SLOW-NEXT:    lis 4, 13107
 ; SLOW-NEXT:    sub 3, 5, 3
-; SLOW-NEXT:    ori 4, 4, 13107
-; SLOW-NEXT:    rotlwi 5, 3, 30
-; SLOW-NEXT:    and 3, 3, 4
-; SLOW-NEXT:    andis. 4, 5, 13107
-; SLOW-NEXT:    andi. 5, 5, 13107
-; SLOW-NEXT:    or 4, 5, 4
-; SLOW-NEXT:    add 3, 3, 4
-; SLOW-NEXT:    lis 5, 3855
-; SLOW-NEXT:    srwi 4, 3, 4
-; SLOW-NEXT:    add 3, 3, 4
+; SLOW-NEXT:    andis. 5, 3, 13107
+; SLOW-NEXT:    andi. 6, 3, 13107
+; SLOW-NEXT:    rotlwi 3, 3, 30
+; SLOW-NEXT:    or 5, 6, 5
+; SLOW-NEXT:    andis. 6, 3, 13107
+; SLOW-NEXT:    andi. 3, 3, 13107
+; SLOW-NEXT:    or 3, 3, 6
+; SLOW-NEXT:    add 3, 5, 3
+; SLOW-NEXT:    srwi 5, 3, 4
+; SLOW-NEXT:    add 3, 3, 5
 ; SLOW-NEXT:    lis 4, 257
-; SLOW-NEXT:    ori 5, 5, 3855
-; SLOW-NEXT:    and 3, 3, 5
+; SLOW-NEXT:    andis. 5, 3, 3855
+; SLOW-NEXT:    andi. 3, 3, 3855
+; SLOW-NEXT:    or 3, 3, 5
 ; SLOW-NEXT:    ori 4, 4, 257
 ; SLOW-NEXT:    mullw 3, 3, 4
 ; SLOW-NEXT:    rlwinm 3, 3, 8, 24, 31
@@ -86,21 +86,21 @@
 ; SLOW-NEXT:    clrlwi 5, 3, 24
 ; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 85
-; SLOW-NEXT:    lis 4, 13107
 ; SLOW-NEXT:    sub 3, 5, 3
-; SLOW-NEXT:    ori 4, 4, 13107
-; SLOW-NEXT:    rotlwi 5, 3, 30
-; SLOW-NEXT:    and 3, 3, 4
-; SLOW-NEXT:    andis. 4, 5, 13107
-; SLOW-NEXT:    andi. 5, 5, 13107
-; SLOW-NEXT:    or 4, 5, 4
-; SLOW-NEXT:    add 3, 3, 4
-; SLOW-NEXT:    lis 5, 3855
-; SLOW-NEXT:    srwi 4, 3, 4
-; SLOW-NEXT:    add 3, 3, 4
+; SLOW-NEXT:    andis. 5, 3, 13107
+; SLOW-NEXT:    andi. 6, 3, 13107
+; SLOW-NEXT:    rotlwi 3, 3, 30
+; SLOW-NEXT:    or 5, 6, 5
+; SLOW-NEXT:    andis. 6, 3, 13107
+; SLOW-NEXT:    andi. 3, 3, 13107
+; SLOW-NEXT:    or 3, 3, 6
+; SLOW-NEXT:    add 3, 5, 3
+; SLOW-NEXT:    srwi 5, 3, 4
+; SLOW-NEXT:    add 3, 3, 5
 ; SLOW-NEXT:    lis 4, 257
-; SLOW-NEXT:    ori 5, 5, 3855
-; SLOW-NEXT:    and 3, 3, 5
+; SLOW-NEXT:    andis. 5, 3, 3855
+; SLOW-NEXT:    andi. 3, 3, 3855
+; SLOW-NEXT:    or 3, 3, 5
 ; SLOW-NEXT:    ori 4, 4, 257
 ; SLOW-NEXT:    mullw 3, 3, 4
 ; SLOW-NEXT:    srwi 3, 3, 24
@@ -122,21 +122,21 @@
 ; SLOW-NEXT:    clrlwi 5, 3, 24
 ; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 85
-; SLOW-NEXT:    lis 4, 13107
 ; SLOW-NEXT:    sub 3, 5, 3
-; SLOW-NEXT:    ori 4, 4, 13107
-; SLOW-NEXT:    rotlwi 5, 3, 30
-; SLOW-NEXT:    and 3, 3, 4
-; SLOW-NEXT:    andis. 4, 5, 13107
-; SLOW-NEXT:    andi. 5, 5, 13107
-; SLOW-NEXT:    or 4, 5, 4
-; SLOW-NEXT:    add 3, 3, 4
-; SLOW-NEXT:    lis 5, 3855
-; SLOW-NEXT:    srwi 4, 3, 4
-; SLOW-NEXT:    add 3, 3, 4
+; SLOW-NEXT:    andis. 5, 3, 13107
+; SLOW-NEXT:    andi. 6, 3, 13107
+; SLOW-NEXT:    rotlwi 3, 3, 30
+; SLOW-NEXT:    or 5, 6, 5
+; SLOW-NEXT:    andis. 6, 3, 13107
+; SLOW-NEXT:    andi. 3, 3, 13107
+; SLOW-NEXT:    or 3, 3, 6
+; SLOW-NEXT:    add 3, 5, 3
+; SLOW-NEXT:    srwi 5, 3, 4
+; SLOW-NEXT:    add 3, 3, 5
 ; SLOW-NEXT:    lis 4, 257
-; SLOW-NEXT:    ori 5, 5, 3855
-; SLOW-NEXT:    and 3, 3, 5
+; SLOW-NEXT:    andis. 5, 3, 3855
+; SLOW-NEXT:    andi. 3, 3, 3855
+; SLOW-NEXT:    or 3, 3, 5
 ; SLOW-NEXT:    ori 4, 4, 257
 ; SLOW-NEXT:    mullw 3, 3, 4
 ; SLOW-NEXT:    rlwinm 3, 3, 8, 24, 31
@@ -158,21 +158,21 @@
 ; SLOW-NEXT:    clrlwi 5, 3, 16
 ; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 21845
-; SLOW-NEXT:    lis 4, 13107
 ; SLOW-NEXT:    sub 3, 5, 3
-; SLOW-NEXT:    ori 4, 4, 13107
-; SLOW-NEXT:    rotlwi 5, 3, 30
-; SLOW-NEXT:    and 3, 3, 4
-; SLOW-NEXT:    andis. 4, 5, 13107
-; SLOW-NEXT:    andi. 5, 5, 13107
-; SLOW-NEXT:    or 4, 5, 4
-; SLOW-NEXT:    add 3, 3, 4
-; SLOW-NEXT:    lis 5, 3855
-; SLOW-NEXT:    srwi 4, 3, 4
-; SLOW-NEXT:    add 3, 3, 4
+; SLOW-NEXT:    andis. 5, 3, 13107
+; SLOW-NEXT:    andi. 6, 3, 13107
+; SLOW-NEXT:    rotlwi 3, 3, 30
+; SLOW-NEXT:    or 5, 6, 5
+; SLOW-NEXT:    andis. 6, 3, 13107
+; SLOW-NEXT:    andi. 3, 3, 13107
+; SLOW-NEXT:    or 3, 3, 6
+; SLOW-NEXT:    add 3, 5, 3
+; SLOW-NEXT:    srwi 5, 3, 4
+; SLOW-NEXT:    add 3, 3, 5
 ; SLOW-NEXT:    lis 4, 257
-; SLOW-NEXT:    ori 5, 5, 3855
-; SLOW-NEXT:    and 3, 3, 5
+; SLOW-NEXT:    andis. 5, 3, 3855
+; SLOW-NEXT:    andi. 3, 3, 3855
+; SLOW-NEXT:    or 3, 3, 5
 ; SLOW-NEXT:    ori 4, 4, 257
 ; SLOW-NEXT:    mullw 3, 3, 4
 ; SLOW-NEXT:    srwi 3, 3, 24
@@ -194,21 +194,21 @@
 ; SLOW-NEXT:    clrlwi 5, 3, 16
 ; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 21845
-; SLOW-NEXT:    lis 4, 13107
 ; SLOW-NEXT:    sub 3, 5, 3
-; SLOW-NEXT:    ori 4, 4, 13107
-; SLOW-NEXT:    rotlwi 5, 3, 30
-; SLOW-NEXT:    and 3, 3, 4
-; SLOW-NEXT:    andis. 4, 5, 13107
-; SLOW-NEXT:    andi. 5, 5, 13107
-; SLOW-NEXT:    or 4, 5, 4
-; SLOW-NEXT:    add 3, 3, 4
-; SLOW-NEXT:    lis 5, 3855
-; SLOW-NEXT:    srwi 4, 3, 4
-; SLOW-NEXT:    add 3, 3, 4
+; SLOW-NEXT:    andis. 5, 3, 13107
+; SLOW-NEXT:    andi. 6, 3, 13107
+; SLOW-NEXT:    rotlwi 3, 3, 30
+; SLOW-NEXT:    or 5, 6, 5
+; SLOW-NEXT:    andis. 6, 3, 13107
+; SLOW-NEXT:    andi. 3, 3, 13107
+; SLOW-NEXT:    or 3, 3, 6
+; SLOW-NEXT:    add 3, 5, 3
+; SLOW-NEXT:    srwi 5, 3, 4
+; SLOW-NEXT:    add 3, 3, 5
 ; SLOW-NEXT:    lis 4, 257
-; SLOW-NEXT:    ori 5, 5, 3855
-; SLOW-NEXT:    and 3, 3, 5
+; SLOW-NEXT:    andis. 5, 3, 3855
+; SLOW-NEXT:    andi. 3, 3, 3855
+; SLOW-NEXT:    or 3, 3, 5
 ; SLOW-NEXT:    ori 4, 4, 257
 ; SLOW-NEXT:    mullw 3, 3, 4
 ; SLOW-NEXT:    rlwinm 3, 3, 8, 24, 31
@@ -270,21 +270,21 @@
 ; SLOW-NEXT:    andis. 6, 5, 21845
 ; SLOW-NEXT:    andi. 5, 5, 21845
 ; SLOW-NEXT:    or 5, 5, 6
-; SLOW-NEXT:    lis 4, 13107
 ; SLOW-NEXT:    sub 3, 3, 5
-; SLOW-NEXT:    ori 4, 4, 13107
-; SLOW-NEXT:    rotlwi 5, 3, 30
-; SLOW-NEXT:    and 3, 3, 4
-; SLOW-NEXT:    andis. 4, 5, 13107
-; SLOW-NEXT:    andi. 5, 5, 13107
-; SLOW-NEXT:    or 4, 5, 4
-; SLOW-NEXT:    add 3, 3, 4
-; SLOW-NEXT:    lis 5, 3855
-; SLOW-NEXT:    srwi 4, 3, 4
-; SLOW-NEXT:    add 3, 3, 4
+; SLOW-NEXT:    andis. 5, 3, 13107
+; SLOW-NEXT:    andi. 6, 3, 13107
+; SLOW-NEXT:    rotlwi 3, 3, 30
+; SLOW-NEXT:    or 5, 6, 5
+; SLOW-NEXT:    andis. 6, 3, 13107
+; SLOW-NEXT:    andi. 3, 3, 13107
+; SLOW-NEXT:    or 3, 3, 6
+; SLOW-NEXT:    add 3, 5, 3
+; SLOW-NEXT:    srwi 5, 3, 4
+; SLOW-NEXT:    add 3, 3, 5
 ; SLOW-NEXT:    lis 4, 257
-; SLOW-NEXT:    ori 5, 5, 3855
-; SLOW-NEXT:    and 3, 3, 5
+; SLOW-NEXT:    andis. 5, 3, 3855
+; SLOW-NEXT:    andi. 3, 3, 3855
+; SLOW-NEXT:    or 3, 3, 5
 ; SLOW-NEXT:    ori 4, 4, 257
 ; SLOW-NEXT:    mullw 3, 3, 4
 ; SLOW-NEXT:    rlwinm 3, 3, 8, 24, 31
@@ -307,25 +307,25 @@
 ; SLOW-NEXT:    clrlwi 5, 3, 16
 ; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 21845
-; SLOW-NEXT:    lis 4, 13107
 ; SLOW-NEXT:    sub 3, 5, 3
-; SLOW-NEXT:    ori 4, 4, 13107
-; SLOW-NEXT:    rotlwi 5, 3, 30
-; SLOW-NEXT:    and 3, 3, 4
-; SLOW-NEXT:    andis. 4, 5, 13107
-; SLOW-NEXT:    andi. 5, 5, 13107
-; SLOW-NEXT:    or 4, 5, 4
-; SLOW-NEXT:    add 3, 3, 4
-; SLOW-NEXT:    lis 5, 3855
-; SLOW-NEXT:    srwi 4, 3, 4
-; SLOW-NEXT:    add 3, 3, 4
+; SLOW-NEXT:    andis. 5, 3, 13107
+; SLOW-NEXT:    andi. 6, 3, 13107
+; SLOW-NEXT:    rotlwi 3, 3, 30
+; SLOW-NEXT:    or 5, 6, 5
+; SLOW-NEXT:    andis. 6, 3, 13107
+; SLOW-NEXT:    andi. 3, 3, 13107
+; SLOW-NEXT:    or 3, 3, 6
+; SLOW-NEXT:    add 3, 5, 3
+; SLOW-NEXT:    srwi 5, 3, 4
+; SLOW-NEXT:    add 3, 3, 5
 ; SLOW-NEXT:    lis 4, 257
-; SLOW-NEXT:    ori 5, 5, 3855
-; SLOW-NEXT:    and 3, 3, 5
+; SLOW-NEXT:    andis. 5, 3, 3855
+; SLOW-NEXT:    andi. 3, 3, 3855
+; SLOW-NEXT:    or 3, 3, 5
 ; SLOW-NEXT:    ori 4, 4, 257
 ; SLOW-NEXT:    mullw 3, 3, 4
 ; SLOW-NEXT:    srwi 3, 3, 24
-; SLOW-NEXT:    rlwinm 3, 3, 0, 27, 27
+; SLOW-NEXT:    andi. 3, 3, 16
 ; SLOW-NEXT:    blr
   %pop = call i16 @llvm.ctpop.i16(i16 %x)
   %z = zext i16 %pop to i64 ; SimplifyDemandedBits may turn zext (or sext) into aext
diff --git a/llvm/test/CodeGen/PowerPC/pr46759.ll b/llvm/test/CodeGen/PowerPC/pr46759.ll
--- a/llvm/test/CodeGen/PowerPC/pr46759.ll
+++ b/llvm/test/CodeGen/PowerPC/pr46759.ll
@@ -39,8 +39,8 @@
 ; CHECK-LE-NEXT:    li r5, -2048
 ; CHECK-LE-NEXT:    mr r31, r1
 ; CHECK-LE-NEXT:    addi r3, r3, 15
-; CHECK-LE-NEXT:    rldicl r3, r3, 60, 4
-; CHECK-LE-NEXT:    rldicl r3, r3, 4, 31
+; CHECK-LE-NEXT:    rotldi r3, r3, 60
+; CHECK-LE-NEXT:    rldic r3, r3, 4, 31
 ; CHECK-LE-NEXT:    neg r4, r3
 ; CHECK-LE-NEXT:    ld r3, 0(r1)
 ; CHECK-LE-NEXT:    and r5, r4, r5
diff --git a/llvm/test/CodeGen/PowerPC/pr47373.ll b/llvm/test/CodeGen/PowerPC/pr47373.ll
--- a/llvm/test/CodeGen/PowerPC/pr47373.ll
+++ b/llvm/test/CodeGen/PowerPC/pr47373.ll
@@ -37,7 +37,7 @@
 ; CHECK-NEXT:    cmpld r3, r6
 ; CHECK-NEXT:    bc 12, lt, .LBB0_7
 ; CHECK-NEXT:  .LBB0_4: # %vector.ph
-; CHECK-NEXT:    rlwinm r5, r4, 0, 0, 29
+; CHECK-NEXT:    rldicr r5, r4, 0, 61
 ; CHECK-NEXT:    li r7, 15
 ; CHECK-NEXT:    addi r6, r5, -4
 ; CHECK-NEXT:    addi r8, r1, 144
diff --git a/llvm/test/CodeGen/PowerPC/setcc-logic.ll b/llvm/test/CodeGen/PowerPC/setcc-logic.ll
--- a/llvm/test/CodeGen/PowerPC/setcc-logic.ll
+++ b/llvm/test/CodeGen/PowerPC/setcc-logic.ll
@@ -481,9 +481,9 @@
 define i1 @or_icmps_const_1bit_diff(i64 %x) {
 ; CHECK-LABEL: or_icmps_const_1bit_diff:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    li 4, -5
 ; CHECK-NEXT:    addi 3, 3, -13
-; CHECK-NEXT:    rldicl 3, 3, 61, 1
-; CHECK-NEXT:    rotldi 3, 3, 3
+; CHECK-NEXT:    and 3, 3, 4
 ; CHECK-NEXT:    cntlzd 3, 3
 ; CHECK-NEXT:    rldicl 3, 3, 58, 63
 ; CHECK-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/stack-clash-dynamic-alloca.ll b/llvm/test/CodeGen/PowerPC/stack-clash-dynamic-alloca.ll
--- a/llvm/test/CodeGen/PowerPC/stack-clash-dynamic-alloca.ll
+++ b/llvm/test/CodeGen/PowerPC/stack-clash-dynamic-alloca.ll
@@ -21,8 +21,8 @@
 ; CHECK-LE-NEXT:    li r5, -32768
 ; CHECK-LE-NEXT:    mr r31, r1
 ; CHECK-LE-NEXT:    addi r3, r3, 15
-; CHECK-LE-NEXT:    rldicl r3, r3, 60, 4
-; CHECK-LE-NEXT:    rldicl r3, r3, 4, 29
+; CHECK-LE-NEXT:    rotldi r3, r3, 60
+; CHECK-LE-NEXT:    rldic r3, r3, 4, 29
 ; CHECK-LE-NEXT:    neg r4, r3
 ; CHECK-LE-NEXT:    addi r3, r31, 48
 ; CHECK-LE-NEXT:    divd r6, r4, r5
@@ -53,8 +53,8 @@
 ; CHECK-P9-LE-NEXT:    addi r3, r3, 15
 ; CHECK-P9-LE-NEXT:    li r6, -32768
 ; CHECK-P9-LE-NEXT:    mr r31, r1
-; CHECK-P9-LE-NEXT:    rldicl r3, r3, 60, 4
-; CHECK-P9-LE-NEXT:    rldicl r3, r3, 4, 29
+; CHECK-P9-LE-NEXT:    rotldi r3, r3, 60
+; CHECK-P9-LE-NEXT:    rldic r3, r3, 4, 29
 ; CHECK-P9-LE-NEXT:    neg r5, r3
 ; CHECK-P9-LE-NEXT:    addi r3, r31, 48
 ; CHECK-P9-LE-NEXT:    divd r7, r5, r6
@@ -84,9 +84,9 @@
 ; CHECK-BE-NEXT:    rldic r3, r3, 2, 30
 ; CHECK-BE-NEXT:    li r5, -32768
 ; CHECK-BE-NEXT:    addi r3, r3, 15
-; CHECK-BE-NEXT:    rldicl r3, r3, 60, 4
+; CHECK-BE-NEXT:    rotldi r3, r3, 60
 ; CHECK-BE-NEXT:    mr r31, r1
-; CHECK-BE-NEXT:    rldicl r3, r3, 4, 29
+; CHECK-BE-NEXT:    rldic r3, r3, 4, 29
 ; CHECK-BE-NEXT:    neg r4, r3
 ; CHECK-BE-NEXT:    divd r6, r4, r5
 ; CHECK-BE-NEXT:    addi r3, r31, 64
@@ -157,8 +157,8 @@
 ; CHECK-LE-NEXT:    li r6, -4096
 ; CHECK-LE-NEXT:    mr r31, r1
 ; CHECK-LE-NEXT:    addi r4, r4, 15
-; CHECK-LE-NEXT:    rldicl r4, r4, 60, 4
-; CHECK-LE-NEXT:    rldicl r4, r4, 4, 29
+; CHECK-LE-NEXT:    rotldi r4, r4, 60
+; CHECK-LE-NEXT:    rldic r4, r4, 4, 29
 ; CHECK-LE-NEXT:    neg r5, r4
 ; CHECK-LE-NEXT:    addi r4, r31, 48
 ; CHECK-LE-NEXT:    divd r7, r5, r6
@@ -192,8 +192,8 @@
 ; CHECK-P9-LE-NEXT:    addi r4, r4, 15
 ; CHECK-P9-LE-NEXT:    li r7, -4096
 ; CHECK-P9-LE-NEXT:    mr r31, r1
-; CHECK-P9-LE-NEXT:    rldicl r4, r4, 60, 4
-; CHECK-P9-LE-NEXT:    rldicl r4, r4, 4, 29
+; CHECK-P9-LE-NEXT:    rotldi r4, r4, 60
+; CHECK-P9-LE-NEXT:    rldic r4, r4, 4, 29
 ; CHECK-P9-LE-NEXT:    neg r6, r4
 ; CHECK-P9-LE-NEXT:    addi r4, r31, 48
 ; CHECK-P9-LE-NEXT:    divd r8, r6, r7
@@ -225,9 +225,9 @@
 ; CHECK-BE-NEXT:    rldic r4, r3, 2, 30
 ; CHECK-BE-NEXT:    li r6, -4096
 ; CHECK-BE-NEXT:    addi r4, r4, 15
-; CHECK-BE-NEXT:    rldicl r4, r4, 60, 4
+; CHECK-BE-NEXT:    rotldi r4, r4, 60
 ; CHECK-BE-NEXT:    mr r31, r1
-; CHECK-BE-NEXT:    rldicl r4, r4, 4, 29
+; CHECK-BE-NEXT:    rldic r4, r4, 4, 29
 ; CHECK-BE-NEXT:    neg r5, r4
 ; CHECK-BE-NEXT:    divd r7, r5, r6
 ; CHECK-BE-NEXT:    addi r4, r31, 64
@@ -304,8 +304,8 @@
 ; CHECK-LE-NEXT:    mr r31, r1
 ; CHECK-LE-NEXT:    addi r3, r3, 15
 ; CHECK-LE-NEXT:    ori r4, r4, 0
-; CHECK-LE-NEXT:    rldicl r3, r3, 60, 4
-; CHECK-LE-NEXT:    rldicl r3, r3, 4, 29
+; CHECK-LE-NEXT:    rotldi r3, r3, 60
+; CHECK-LE-NEXT:    rldic r3, r3, 4, 29
 ; CHECK-LE-NEXT:    neg r5, r3
 ; CHECK-LE-NEXT:    addi r3, r31, 48
 ; CHECK-LE-NEXT:    divd r6, r5, r4
@@ -337,8 +337,8 @@
 ; CHECK-P9-LE-NEXT:    lis r5, -1
 ; CHECK-P9-LE-NEXT:    ori r5, r5, 0
 ; CHECK-P9-LE-NEXT:    mr r31, r1
-; CHECK-P9-LE-NEXT:    rldicl r3, r3, 60, 4
-; CHECK-P9-LE-NEXT:    rldicl r3, r3, 4, 29
+; CHECK-P9-LE-NEXT:    rotldi r3, r3, 60
+; CHECK-P9-LE-NEXT:    rldic r3, r3, 4, 29
 ; CHECK-P9-LE-NEXT:    neg r6, r3
 ; CHECK-P9-LE-NEXT:    addi r3, r31, 48
 ; CHECK-P9-LE-NEXT:    divd r7, r6, r5
@@ -368,9 +368,9 @@
 ; CHECK-BE-NEXT:    rldic r3, r3, 2, 30
 ; CHECK-BE-NEXT:    lis r4, -1
 ; CHECK-BE-NEXT:    addi r3, r3, 15
-; CHECK-BE-NEXT:    rldicl r3, r3, 60, 4
+; CHECK-BE-NEXT:    rotldi r3, r3, 60
 ; CHECK-BE-NEXT:    ori r4, r4, 0
-; CHECK-BE-NEXT:    rldicl r3, r3, 4, 29
+; CHECK-BE-NEXT:    rldic r3, r3, 4, 29
 ; CHECK-BE-NEXT:    mr r31, r1
 ; CHECK-BE-NEXT:    neg r5, r3
 ; CHECK-BE-NEXT:    divd r6, r5, r4
diff --git a/llvm/test/CodeGen/PowerPC/stack-clash-prologue.ll b/llvm/test/CodeGen/PowerPC/stack-clash-prologue.ll
--- a/llvm/test/CodeGen/PowerPC/stack-clash-prologue.ll
+++ b/llvm/test/CodeGen/PowerPC/stack-clash-prologue.ll
@@ -859,10 +859,10 @@
 ; CHECK-LE-NEXT:    li r6, 1
 ; CHECK-LE-NEXT:    addi r3, r3, 15
 ; CHECK-LE-NEXT:    ori r5, r5, 0
-; CHECK-LE-NEXT:    rldicl r3, r3, 60, 4
+; CHECK-LE-NEXT:    rotldi r3, r3, 60
 ; CHECK-LE-NEXT:    sldi r4, r4, 2
 ; CHECK-LE-NEXT:    add r5, r31, r5
-; CHECK-LE-NEXT:    rldicl r3, r3, 4, 31
+; CHECK-LE-NEXT:    rldic r3, r3, 4, 31
 ; CHECK-LE-NEXT:    stwx r6, r5, r4
 ; CHECK-LE-NEXT:    li r4, -32768
 ; CHECK-LE-NEXT:    neg r7, r3
@@ -928,11 +928,11 @@
 ; CHECK-BE-NEXT:    addi r3, r3, 15
 ; CHECK-BE-NEXT:    mr r31, r1
 ; CHECK-BE-NEXT:    ori r5, r5, 0
-; CHECK-BE-NEXT:    rldicl r3, r3, 60, 4
+; CHECK-BE-NEXT:    rotldi r3, r3, 60
 ; CHECK-BE-NEXT:    add r5, r31, r5
 ; CHECK-BE-NEXT:    sldi r4, r4, 2
 ; CHECK-BE-NEXT:    li r6, 1
-; CHECK-BE-NEXT:    rldicl r3, r3, 4, 31
+; CHECK-BE-NEXT:    rldic r3, r3, 4, 31
 ; CHECK-BE-NEXT:    stwx r6, r5, r4
 ; CHECK-BE-NEXT:    neg r7, r3
 ; CHECK-BE-NEXT:    li r4, -32768