[CSKY 4/n] Add basic CSKYAsmParser and CSKYInstPrinter

[zixuan-wu]

Summary

This basic parser will handle basic instructions with register or immediate operands.
With the addition of CSKYInstPrinter, we can now make use of lit tests.

[zixuan-wu]

Gentle pin..

[MaskRay]

I think the M68k has a lot which can be learned by other experimental targets. The author posted the patch series all together (1) so reviewers can review each individual patch separately and suggest code motion among patches. (2) The author shared updates on llvm-dev.

For example, if this patch were in part of a patch series, the back-and-forth style change def : ProcessorModel<"generic-csky", NoSchedModel, []>; (generic-csky->generic) could be caught earlier.

[zixuan-wu]

In D93798#2472909, @MaskRay wrote:

I think the M68k has a lot which can be learned by other experimental targets. The author posted the patch series all together (1) so reviewers can review each individual patch separately and suggest code motion among patches. (2) The author shared updates on llvm-dev.

For example, if this patch were in part of a patch series, the back-and-forth style change def : ProcessorModel<"generic-csky", NoSchedModel, []>; (generic-csky->generic) could be caught earlier.

The whole picture can be referred here https://reviews.llvm.org/D86269.
I don't think too many patches on the fly is good to upstream because they influence each other and need change on the way of review.
Yes, it's good to sync the process of development in llvm-dev maillist phase by phase

[rengolin]

In D93798#2473365, @zixuan-wu wrote:

I don't think too many patches on the fly is good to upstream because they influence each other and need change on the way of review.

@MaskRay is right. Even though they do affect each other and you have to do a bit more work in refactoring them, it's a lot easier to see he effect of the early decisions on your patches on the later stages.

So far in CSKY, I have been looking at stubs and they don't look "wrong" but they also don't tell me anything about the future decisions.

You could probably compare the amount of work you do initially on a multi-patch approach with a similar amount with post-merge fixes and local refactoring.

The m64k is a good example on the benefits of having such approach, as we have already avoided some mistakes from happening in the first place.

[zixuan-wu]

In D93798#2473722, @rengolin wrote:

In D93798#2473365, @zixuan-wu wrote:

I don't think too many patches on the fly is good to upstream because they influence each other and need change on the way of review.

@MaskRay is right. Even though they do affect each other and you have to do a bit more work in refactoring them, it's a lot easier to see he effect of the early decisions on your patches on the later stages.

So far in CSKY, I have been looking at stubs and they don't look "wrong" but they also don't tell me anything about the future decisions.

You could probably compare the amount of work you do initially on a multi-patch approach with a similar amount with post-merge fixes and local refactoring.

The m64k is a good example on the benefits of having such approach, as we have already avoided some mistakes from happening in the first place.

I think it's early-refactoring issue. We should assume the current patch is good in current codebase context, or we will re-review many times.
We can proposal a rough whole picture patch as reference at first to make sure the direction is right, but every small patch is changing during the review process and only suitable for newest codebase at the moment of upstream.

For example, the development process is A->B->C. We can/should not make the structure of B is good to C as we lookup ahead the future patch(C), because B is in codebase of A.
What's more, if we have D following C (C->D), the early review of D is meaningless as B is changing and the change of C is much more. It's much more burden to consider every context (A,B,C,D) for both author and reviewer.

[rengolin]

In D93798#2474617, @zixuan-wu wrote:

I think it's early-refactoring issue. We should assume the current patch is good in current codebase context, or we will re-review many times.

You are right, it is an early refactoring issue. But @MaskRay is also right, that not doing it leads to late refactoring issues.

Because LLVM is an upstream project with lost of downstream projects depending on it, late refactoring hurts more than early refactoring.

This is not a right vs. wrong point. It's a "which is less painful" and the LLVM community has consistently chosen early refactoring over late refactoring.

The reasons are varied and extensive, but a summary would be three major points:

1. When we land the target, we want to make sure that the direction it's going is agreeable with the rest of the project.

2. Later breakages in buildbots and developer builds will increase the pressure for you to potentially have to revert your patches.

3. Early refactoring puts the pain to prove correctness on the community that proposes the patch, while late refactoring puts the pressure on everyone else, which is unfair.

Take the other back-ends that have been merged to LLVM in the past and you'll see all of them followed the same recipe. This is not an isolated opinion, it's the "status quo".

You could start a new RFC on the list to change the status quo, but that would mean your back-end effort will pause and the code will get stale.

Because it's not a right vs. wrong discussion, I predict it would lead to no consensus and no change in the status quo, so I'd advise against. But it's up to you if you want to follow that course.

We can proposal a rough whole picture patch as reference at first to make sure the direction is right, but every small patch is changing during the review process and only suitable for newest codebase at the moment of upstream.

There are examples of this being done by major contributors and not helping at all (even if it's not meant to merge, just informational). For example ARM's SVE target and PGI's Flang front-end.

While it's good to see the overall picture, it's really hard for any one person to review the whole thing as is and take any meaningful context from it.

It's much more burden to consider every context (A,B,C,D) for both author and reviewer.

That is true, but both author and reviewer are a very small subset of the community. We have hundreds of committers, thousands working downstream and who knows how many tests are being run.

If other changes in the project are added half-baked (assuming it will be correct in the end), it could affect your own change right now and create bugs that we can't predict and may make your life much worse.

There are a number of concurrent in-flight changes, big and small, being done to LLVM every day. If all of them land half-way, we may create a situation that we can't get out of.

True, a new back-end is a lot less dangerous than say a refactoring of the table-gen description or the pass manager, but it's still not negligible.

[zixuan-wu]

Yes, I agree with it's not a right vs wrong problem.

I want to say every patch when it's upstreamed is not half-baked or land half-way. It's good enough for current codebase with test cases so that it's workable for downstream.
There is just no perfect infra which is needed and introduced by the later patch/feature.

I think it's not worthwhile to spend too much time to discuss this open topic. Let's come back to review this and following patches, please. Thank you! I can make few diff files based on this one.

[rengolin]

In D93798#2475498, @zixuan-wu wrote:

I think it's not worthwhile to spend too much time to discuss this open topic. Let's come back to review this and following patches, please. Thank you! I can make few diff files based on this one.

Awesome! Thank you!

[zixuan-wu]

could anybody review this patch and https://reviews.llvm.org/D94007? Gentle ping..

[zixuan-wu]

ping..

[rengolin]

Hi Zixuan,

I'm still worried about the n in 4/n and 5/n. I know these are not the final patches of the back-end, but we need a minimal structure of the first batch, just like we have for m68k at the moment.

Can you isolate a first batch of patches that'd make the CSKY back-end generate ASM code for some basic code generation example (like foo(a, b) { return a+b })?

Those would be a first import, and will give reviewers the chance to understand your whole approach, not only one step into the future.

I think this is what's keeping people from reviewing your patches...

cheers,
--renato

[zixuan-wu]

In D93798#2506428, @rengolin wrote:

Hi Zixuan,

I'm still worried about the n in 4/n and 5/n. I know these are not the final patches of the back-end, but we need a minimal structure of the first batch, just like we have for m68k at the moment.

Can you isolate a first batch of patches that'd make the CSKY back-end generate ASM code for some basic code generation example (like foo(a, b) { return a+b })?

Those would be a first import, and will give reviewers the chance to understand your whole approach, not only one step into the future.

I think this is what's keeping people from reviewing your patches...

cheers,
--renato

Yes, a first batch of patches to reach the point that it can generate first ALU asm codegen. In all, I propose following patches to construct the first batch.

https://reviews.llvm.org/D93798
https://reviews.llvm.org/D94007
https://reviews.llvm.org/D95029
https://reviews.llvm.org/D95030

[rengolin]

In D93798#2509226, @zixuan-wu wrote:

Yes, a first batch of patches to reach the point that it can generate first ALU asm codegen. In all, I propose following patches to construct the first batch.

https://reviews.llvm.org/D93798
https://reviews.llvm.org/D94007
https://reviews.llvm.org/D95029
https://reviews.llvm.org/D95030

Sounds great, thanks @zixuan-wu!

@MaskRay should be better now to have another look, thanks!

[MaskRay]

llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp

79

Delete CSKYOperand -
https://llvm.org/docs/CodingStandards.html#doxygen-use-in-documentation-comments
"Don’t duplicate the documentation comment in the header file ..."

82

Delete the blank line

169

"Don’t duplicate the documentation comment in the header file ..."

171

"Don’t duplicate the documentation comment in the header file ..."

195

can use one OS

238

Complete sentences end with periods.

This applies to many other places.

290

May use D94649

435

Period.

llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.cpp

102

No newline at end of file

llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.cpp

72

clang-format prefers /*TuneCPU=*/

llvm/test/MC/CSKY/csky-invalid.s

1 ↗

(On Diff #317494)

Instead of a separate error test, consider merging into the positive test and use .ifdef ERR (you can find several examples in test/MC added by me)

4 ↗

(On Diff #317494)

[[@LINE]] is deprecated lit syntax. Use [[#@LINE]]

llvm/test/MC/CSKY/csky-valid.s

1 ↗

(On Diff #317494)

Instead of csky-valid.s, you may pick basic.s. every file in this directory is C-SKY related so the name csky.s does not convey additional information. -valid can be omitted because most tests are positive tests.

[MaskRay]

llvm/test/MC/CSKY/csky-valid.s

2 ↗

(On Diff #317494)

CHECK-ASM,CHECK-ASM-AND-OBJ was probably copied somewhere else. MCAsmStreamer and MCObjectStreamer are different enough that sometimes you want to test both llvm-mc and llvm-mc -filetype=obj ... | llvm-objdump -d

If the disassembly part hasn't been implemented, don't add CHECK-ASM-AND-OBJ

[zixuan-wu]

Address comments.

[zixuan-wu]

anymore comments or LGTM?

[rengolin]

In D93798#2518757, @zixuan-wu wrote:

anymore comments or LGTM?

@zixuan-wu, like other multi reviews, wait until all pending patches are approved to commit all of them in one go.

This allows discussion in other patches to happen and maybe change existing approvals if issues are found.

I'll let @MaskRay approve this one.

[MaskRay]

llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp

125

Is isMem unimplemented? If yes, deferring to a subsequent patch is better.

284

The convention is to have a space after :

llvm/test/MC/CSKY/basic.s

2

The joined line is sufficiently short, no need for wrapping.

99

If you use ## for non-RUN non-CHECK comment markers, please stick with the rule consistently for subsequent comments.

[zixuan-wu]

llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp

125

It's implement of pure virtual function, I am afraid it can not ignore.

[zixuan-wu]

ping..

[rengolin]

Hi @zixuan-wu,

There are still some comments on the remaining patches in this set that need addressing before all of them can be committed as a whole.

Addressing all the reviews on the set increases the chances of people checking back (otherwise, it looks to us that you're still working on them).

Thanks!
--renato

[zixuan-wu]

D93798, D94007 and D95029 are the first set of patches to review and commit together. Please have a review together, thanks.

[rengolin]

And this one, too: https://reviews.llvm.org/D95030

[zixuan-wu]

In D93798#2688279, @rengolin wrote:

And this one, too: https://reviews.llvm.org/D95030

Yep, but I was gonna make D95030 as next set of patches to handle dag codegen.

[rengolin]

In D93798#2690364, @zixuan-wu wrote:

Yep, but I was gonna make D95030 as next set of patches to handle dag codegen.

Fair enough, though that patch is probably good to go, too, with a few nits sorted.

[zixuan-wu]

In D93798#2690896, @rengolin wrote:

In D93798#2690364, @zixuan-wu wrote:

Yep, but I was gonna make D95030 as next set of patches to handle dag codegen.

Fair enough, though that patch is probably good to go, too, with a few nits sorted.

Could you please also accept this revision and D95029?

[rengolin]

In D93798#2693768, @zixuan-wu wrote:

Could you please also accept this revision and D95029?

Hadn't noticed you had updated, sorry. Approved now.

[zixuan-wu]

In D93798#2694367, @rengolin wrote:

In D93798#2693768, @zixuan-wu wrote:

Could you please also accept this revision and D95029?

Hadn't noticed you had updated, sorry. Approved now.

Sorry for the confuse. Thank you for your review.
How about this patch ?

[rengolin]

Hi, it seems you have addressed all review comments, so this looks good to me. Thanks for all the work, and sorry it took so long.

[zixuan-wu]

In D93798#2697831, @rengolin wrote:

Hi, it seems you have addressed all review comments, so this looks good to me. Thanks for all the work, and sorry it took so long.

As our internal codebase is changing and not stable, I delayed the process of upstreaming to community about CSKY backend. So it lasts too long, and the process will be restarting and going further now.
Thank for your support.

llvm/lib/Target/CSKY/AsmParser/CMakeLists.txt

+add_llvm_component_library(LLVMCSKYAsmParser
+  CSKYAsmParser.cpp
+
+  LINK_COMPONENTS
+  CSKYDesc
+  CSKYInfo
+  MC
+  MCParser
+  Support
+
+  ADD_TO_COMPONENT
+  CSKY
+  )

llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp

+//===-- CSKYAsmParser.cpp - Parse CSKY assembly to MCInst instructions --===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "MCTargetDesc/CSKYMCTargetDesc.h"
+#include "TargetInfo/CSKYTargetInfo.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/StringSwitch.h"
+#include "llvm/CodeGen/Register.h"
+#include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCExpr.h"
+#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCParser/MCAsmLexer.h"
+#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
+#include "llvm/MC/MCParser/MCTargetAsmParser.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCStreamer.h"
+#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/Support/Casting.h"
+#include "llvm/Support/TargetRegistry.h"
+
+using namespace llvm;
+
+namespace {
+struct CSKYOperand;
+
+class CSKYAsmParser : public MCTargetAsmParser {
+
+  bool generateImmOutOfRangeError(OperandVector &Operands, uint64_t ErrorInfo,
+                                  int64_t Lower, int64_t Upper, Twine Msg);
+
+  SMLoc getLoc() const { return getParser().getTok().getLoc(); }
+
+  bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+                               OperandVector &Operands, MCStreamer &Out,
+                               uint64_t &ErrorInfo,
+                               bool MatchingInlineAsm) override;
+
+  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
+
+  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+                        SMLoc NameLoc, OperandVector &Operands) override;
+
+  bool ParseDirective(AsmToken DirectiveID) override;
+
+  OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+                                        SMLoc &EndLoc) override;
+
+// Auto-generated instruction matching functions
+#define GET_ASSEMBLER_HEADER
+#include "CSKYGenAsmMatcher.inc"
+
+  OperandMatchResultTy parseImmediate(OperandVector &Operands);
+  OperandMatchResultTy parseRegister(OperandVector &Operands);
+
+  bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
+
+public:
+  enum CSKYMatchResultTy {
+    Match_Dummy = FIRST_TARGET_MATCH_RESULT_TY,
+#define GET_OPERAND_DIAGNOSTIC_TYPES
+#include "CSKYGenAsmMatcher.inc"
+#undef GET_OPERAND_DIAGNOSTIC_TYPES
+  };
+
+  CSKYAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
+                const MCInstrInfo &MII, const MCTargetOptions &Options)
+      : MCTargetAsmParser(Options, STI, MII) {
+    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
+  }
+};
+
+/// Instances of this class represent a parsed machine instruction.
+struct CSKYOperand : public MCParsedAsmOperand {
+  enum KindTy {
+    Token,
+    Register,
+    Immediate,
+  } Kind;
+
+  struct RegOp {
+    unsigned RegNum;
+  };
+
+  struct ImmOp {
+    const MCExpr *Val;
+  };
+
+  SMLoc StartLoc, EndLoc;
+  union {
+    StringRef Tok;
+    RegOp Reg;
+    ImmOp Imm;
+  };
+
+  CSKYOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
+
+public:
+  CSKYOperand(const CSKYOperand &o) : MCParsedAsmOperand() {
+    Kind = o.Kind;
+    StartLoc = o.StartLoc;
+    EndLoc = o.EndLoc;
+    switch (Kind) {
+    case Register:
+      Reg = o.Reg;
+      break;
+    case Immediate:
+      Imm = o.Imm;
+      break;
+    case Token:
+      Tok = o.Tok;
+      break;
+    }
+  }
+
+  bool isToken() const override { return Kind == Token; }
+  bool isReg() const override { return Kind == Register; }
+  bool isImm() const override { return Kind == Immediate; }
+  bool isMem() const override { return false; }
+
+  static bool evaluateConstantImm(const MCExpr *Expr, int64_t &Imm) {
+    if (auto CE = dyn_cast<MCConstantExpr>(Expr)) {
+      Imm = CE->getValue();
+      return true;
+    }
+
+    return false;
+  }
+
+  template <unsigned num> bool isUImm() const {
+    if (!isImm())
+      return false;
+
+    int64_t Imm;
+    bool IsConstantImm = evaluateConstantImm(getImm(), Imm);
+    return IsConstantImm && isUInt<num>(Imm);
+  }
+
+  template <unsigned num> bool isOImm() const {
+    if (!isImm())
+      return false;
+
+    int64_t Imm;
+    bool IsConstantImm = evaluateConstantImm(getImm(), Imm);
+    return IsConstantImm && isUInt<num>(Imm - 1);
+  }
+
+  template <unsigned num> bool isSImm() const {
+    if (!isImm())
+      return false;
+
+    int64_t Imm;
+    bool IsConstantImm = evaluateConstantImm(getImm(), Imm);
+    return IsConstantImm && isInt<num>(Imm);
+  }
+
+  bool isUImm5() const { return isUImm<5>(); }
+  bool isUImm12() const { return isUImm<12>(); }
+  bool isOImm12() const { return isOImm<12>(); }
+
+  /// Gets location of the first token of this operand.
+  SMLoc getStartLoc() const override { return StartLoc; }
+  /// Gets location of the last token of this operand.
+  SMLoc getEndLoc() const override { return EndLoc; }
+
+  unsigned getReg() const override {
+    assert(Kind == Register && "Invalid type access!");
+    return Reg.RegNum;
+  }
+
+  const MCExpr *getImm() const {
+    assert(Kind == Immediate && "Invalid type access!");
+    return Imm.Val;
+  }
+
+  StringRef getToken() const {
+    assert(Kind == Token && "Invalid type access!");
+    return Tok;
+  }
+
+  void print(raw_ostream &OS) const override {
+    switch (Kind) {
+    case Immediate:
+      OS << *getImm();
+      break;
+    case Register:
+      OS << "<register x" << getReg() << ">";
+      break;
+    case Token:
+      OS << "'" << getToken() << "'";
+      break;
+    }
+  }
+
+  static std::unique_ptr<CSKYOperand> createToken(StringRef Str, SMLoc S) {
+    auto Op = std::make_unique<CSKYOperand>(Token);
+    Op->Tok = Str;
+    Op->StartLoc = S;
+    Op->EndLoc = S;
+    return Op;
+  }
+
+  static std::unique_ptr<CSKYOperand> createReg(unsigned RegNo, SMLoc S,
+                                                SMLoc E) {
+    auto Op = std::make_unique<CSKYOperand>(Register);
+    Op->Reg.RegNum = RegNo;
+    Op->StartLoc = S;
+    Op->EndLoc = E;
+    return Op;
+  }
+
+  static std::unique_ptr<CSKYOperand> createImm(const MCExpr *Val, SMLoc S,
+                                                SMLoc E) {
+    auto Op = std::make_unique<CSKYOperand>(Immediate);
+    Op->Imm.Val = Val;
+    Op->StartLoc = S;
+    Op->EndLoc = E;
+    return Op;
+  }
+
+  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
+    assert(Expr && "Expr shouldn't be null!");
+    if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
+      Inst.addOperand(MCOperand::createImm(CE->getValue()));
+    else
+      Inst.addOperand(MCOperand::createExpr(Expr));
+  }
+
+  // Used by the TableGen Code.
+  void addRegOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    Inst.addOperand(MCOperand::createReg(getReg()));
+  }
+
+  void addImmOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    addExpr(Inst, getImm());
+  }
+};
+} // end anonymous namespace.
+
+#define GET_REGISTER_MATCHER
+#define GET_SUBTARGET_FEATURE_NAME
+#define GET_MATCHER_IMPLEMENTATION
+#define GET_MNEMONIC_SPELL_CHECKER
+#include "CSKYGenAsmMatcher.inc"
+
+static std::string CSKYMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS,
+                                          unsigned VariantID = 0);
+
+bool CSKYAsmParser::generateImmOutOfRangeError(
+    OperandVector &Operands, uint64_t ErrorInfo, int64_t Lower, int64_t Upper,
+    Twine Msg = "immediate must be an integer in the range") {
+  SMLoc ErrorLoc = ((CSKYOperand &)*Operands[ErrorInfo]).getStartLoc();
+  return Error(ErrorLoc, Msg + " [" + Twine(Lower) + ", " + Twine(Upper) + "]");
+}
+
+bool CSKYAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
+                                            OperandVector &Operands,
+                                            MCStreamer &Out,
+                                            uint64_t &ErrorInfo,
+                                            bool MatchingInlineAsm) {
+  MCInst Inst;
+  FeatureBitset MissingFeatures;
+
+  auto Result = MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,
+                                     MatchingInlineAsm);
+  switch (Result) {
+  default:
+    break;
+  case Match_Success:
+    Inst.setLoc(IDLoc);
+    Out.emitInstruction(Inst, getSTI());
+    return false;
+  case Match_MissingFeature: {
+    assert(MissingFeatures.any() && "Unknown missing features!");
+    ListSeparator LS;
+    std::string Msg = "instruction requires the following: ";
+    for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) {
+      if (MissingFeatures[i]) {
+        Msg += LS;
+        Msg += getSubtargetFeatureName(i);
+      }
+    }
+    return Error(IDLoc, Msg);
+  }
+  case Match_MnemonicFail: {
+    FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
+    std::string Suggestion =
+        CSKYMnemonicSpellCheck(((CSKYOperand &)*Operands[0]).getToken(), FBS);
+    return Error(IDLoc, "unrecognized instruction mnemonic" + Suggestion);
+  }
+  case Match_InvalidOperand: {
+    SMLoc ErrorLoc = IDLoc;
+    if (ErrorInfo != ~0U) {
+      if (ErrorInfo >= Operands.size())
+        return Error(ErrorLoc, "too few operands for instruction");
+
+      ErrorLoc = ((CSKYOperand &)*Operands[ErrorInfo]).getStartLoc();
+      if (ErrorLoc == SMLoc())
+        ErrorLoc = IDLoc;
+    }
+    return Error(ErrorLoc, "invalid operand for instruction");
+  }
+  }
+
+  // Handle the case when the error message is of specific type
+  // other than the generic Match_InvalidOperand, and the
+  // corresponding operand is missing.
+  if (Result > FIRST_TARGET_MATCH_RESULT_TY) {
+    SMLoc ErrorLoc = IDLoc;
+    if (ErrorInfo != ~0U && ErrorInfo >= Operands.size())
+      return Error(ErrorLoc, "too few operands for instruction");
+  }
+
+  switch (Result) {
+  default:
+    break;
+  case Match_InvalidOImm12:
+    return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 12));
+  case Match_InvalidUImm12:
+    return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 12) - 1);
+  case Match_InvalidUImm5:
+    return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1);
+  }
+
+  llvm_unreachable("Unknown match type detected!");
+}
+
+// Attempts to match Name as a register (either using the default name or
+// alternative ABI names), setting RegNo to the matching register. Upon
+// failure, returns true and sets RegNo to 0.
+static bool matchRegisterNameHelper(MCRegister &RegNo, StringRef Name) {
+  RegNo = MatchRegisterName(Name);
+
+  if (RegNo == CSKY::NoRegister)
+    RegNo = MatchRegisterAltName(Name);
+
+  return RegNo == CSKY::NoRegister;
+}
+
+bool CSKYAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
+                                  SMLoc &EndLoc) {
+  const AsmToken &Tok = getParser().getTok();
+  StartLoc = Tok.getLoc();
+  EndLoc = Tok.getEndLoc();
+  StringRef Name = getLexer().getTok().getIdentifier();
+
+  if (!matchRegisterNameHelper((MCRegister &)RegNo, Name)) {
+    getParser().Lex(); // Eat identifier token.
+    return false;
+  }
+
+  return Error(StartLoc, "invalid register name");
+}
+
+OperandMatchResultTy CSKYAsmParser::parseRegister(OperandVector &Operands) {
+  SMLoc S = getLoc();
+  SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1);
+
+  switch (getLexer().getKind()) {
+  default:
+    return MatchOperand_NoMatch;
+  case AsmToken::Identifier: {
+    StringRef Name = getLexer().getTok().getIdentifier();
+    MCRegister RegNo;
+
+    if (matchRegisterNameHelper((MCRegister &)RegNo, Name))
+      return MatchOperand_NoMatch;
+
+    getLexer().Lex();
+    Operands.push_back(CSKYOperand::createReg(RegNo, S, E));
+
+    return MatchOperand_Success;
+  }
+  }
+}
+
+OperandMatchResultTy CSKYAsmParser::parseImmediate(OperandVector &Operands) {
+  switch (getLexer().getKind()) {
+  default:
+    return MatchOperand_NoMatch;
+  case AsmToken::LParen:
+  case AsmToken::Minus:
+  case AsmToken::Plus:
+  case AsmToken::Integer:
+  case AsmToken::String:
+    break;
+  }
+
+  const MCExpr *IdVal;
+  SMLoc S = getLoc();
+  if (getParser().parseExpression(IdVal))
+    return MatchOperand_ParseFail;
+
+  SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1);
+  Operands.push_back(CSKYOperand::createImm(IdVal, S, E));
+  return MatchOperand_Success;
+}
+
+/// Looks at a token type and creates the relevant operand from this
+/// information, adding to Operands. If operand was parsed, returns false, else
+/// true.
+bool CSKYAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
+  // Attempt to parse token as register
+  if (parseRegister(Operands) == MatchOperand_Success)
+    return false;
+
+  // Attempt to parse token as a imm.
+  if (parseImmediate(Operands) == MatchOperand_Success)
+    return false;
+
+  // Finally we have exhausted all options and must declare defeat.
+  Error(getLoc(), "unknown operand");
+  return true;
+}
+
+bool CSKYAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
+                                     SMLoc NameLoc, OperandVector &Operands) {
+  // First operand is token for instruction.
+  Operands.push_back(CSKYOperand::createToken(Name, NameLoc));
+
+  // If there are no more operands, then finish.
+  if (getLexer().is(AsmToken::EndOfStatement))
+    return false;
+
+  // Parse first operand.
+  if (parseOperand(Operands, Name))
+    return true;
+
+  // Parse until end of statement, consuming commas between operands.
+  while (getLexer().is(AsmToken::Comma)) {
+    // Consume comma token.
+    getLexer().Lex();
+
+    // Parse next operand.
+    if (parseOperand(Operands, Name))
+      return true;
+  }
+
+  if (getLexer().isNot(AsmToken::EndOfStatement)) {
+    SMLoc Loc = getLexer().getLoc();
+    getParser().eatToEndOfStatement();
+    return Error(Loc, "unexpected token");
+  }
+
+  getParser().Lex(); // Consume the EndOfStatement.
+  return false;
+}
+
+OperandMatchResultTy CSKYAsmParser::tryParseRegister(unsigned &RegNo,
+                                                     SMLoc &StartLoc,
+                                                     SMLoc &EndLoc) {
+  const AsmToken &Tok = getParser().getTok();
+  StartLoc = Tok.getLoc();
+  EndLoc = Tok.getEndLoc();
+
+  StringRef Name = getLexer().getTok().getIdentifier();
+
+  if (matchRegisterNameHelper((MCRegister &)RegNo, Name))
+    return MatchOperand_NoMatch;
+
+  getParser().Lex(); // Eat identifier token.
+  return MatchOperand_Success;
+}
+
+bool CSKYAsmParser::ParseDirective(AsmToken DirectiveID) { return true; }
+
+extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeCSKYAsmParser() {
+  RegisterMCAsmParser<CSKYAsmParser> X(getTheCSKYTarget());
+}

llvm/lib/Target/CSKY/CMakeLists.txt

 add_llvm_component_group(CSKY)
 
 set(LLVM_TARGET_DEFINITIONS CSKY.td)
 
-tablegen(LLVM CSKYGenRegisterInfo.inc -gen-register-info)
+tablegen(LLVM CSKYGenAsmMatcher.inc -gen-asm-matcher)
+tablegen(LLVM CSKYGenAsmWriter.inc -gen-asm-writer)
 tablegen(LLVM CSKYGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM CSKYGenMCCodeEmitter.inc -gen-emitter)
+tablegen(LLVM CSKYGenRegisterInfo.inc -gen-register-info)
+tablegen(LLVM CSKYGenSubtargetInfo.inc -gen-subtarget)
 
 add_public_tablegen_target(CSKYCommonTableGen)
 
 add_llvm_target(CSKYCodeGen
   CSKYTargetMachine.cpp
 
   LINK_COMPONENTS
   Core
   CodeGen
   CSKYInfo
   Support
   Target
 
   ADD_TO_COMPONENT
   CSKY
   )
 
-add_subdirectory(TargetInfo)
+add_subdirectory(AsmParser)
 add_subdirectory(MCTargetDesc)
+add_subdirectory(TargetInfo)

llvm/lib/Target/CSKY/CSKY.td

 
 include "CSKYRegisterInfo.td"
 include "CSKYInstrInfo.td"
 
 //===----------------------------------------------------------------------===//
 // CSKY processors supported.
 //===----------------------------------------------------------------------===//
 
-def : ProcessorModel<"generic-csky", NoSchedModel, []>;
+def : ProcessorModel<"generic", NoSchedModel, []>;
 
 //===----------------------------------------------------------------------===//
 // Define the CSKY target.
 //===----------------------------------------------------------------------===//
 
 def CSKYInstrInfo : InstrInfo;
 
+
+def CSKYAsmParser : AsmParser {
+  let ShouldEmitMatchRegisterAltName = 1;
+  let AllowDuplicateRegisterNames = 1;
+}
+
+def CSKYAsmWriter : AsmWriter {
+  int PassSubtarget = 1;
+}
+
 def CSKY : Target {
   let InstructionSet = CSKYInstrInfo;
+  let AssemblyParsers = [CSKYAsmParser];
+  let AssemblyWriters = [CSKYAsmWriter];
+  let AllowRegisterRenaming = 1;
 }

llvm/lib/Target/CSKY/CSKYInstrInfo.td

 // CSKY specific DAG Nodes.
 //===----------------------------------------------------------------------===//
 
 // TODO: Add CSKY specific DAG Nodes.
 
 //===----------------------------------------------------------------------===//
 // Operand and SDNode transformation definitions.
 //===----------------------------------------------------------------------===//
+class ImmAsmOperand<string prefix, int width, string suffix> : AsmOperandClass {
+  let Name = prefix # "Imm" # width # suffix;
+  let RenderMethod = "addImmOperands";
+  let DiagnosticType = !strconcat("Invalid", Name);
+}
+
+class SImmAsmOperand<int width, string suffix = "">
+    : ImmAsmOperand<"S", width, suffix> {
+}
+
+class UImmAsmOperand<int width, string suffix = "">
+    : ImmAsmOperand<"U", width, suffix> {
+}
+
+class OImmAsmOperand<int width, string suffix = "">
+    : ImmAsmOperand<"O", width, suffix> {
+}
 
 class oimm<int num> : Operand<i32>,
   ImmLeaf<i32, "return isUInt<"#num#">(Imm - 1);"> {
   let EncoderMethod = "getOImmOpValue";
+  let ParserMatchClass = OImmAsmOperand<num>;
 }
 
 class uimm<int num, int shift = 0> : Operand<i32>,
   ImmLeaf<i32, "return isShiftedUInt<"#num#", "#shift#">(Imm);"> {
   let EncoderMethod = "getImmOpValue<"#shift#">";
+  let ParserMatchClass = UImmAsmOperand<num>;
 }
 
 class simm<int num, int shift = 0> : Operand<i32>,
   ImmLeaf<i32, "return isShiftedInt<"#num#", "#shift#">(Imm);"> {
   let EncoderMethod = "getImmOpValue<"#shift#">";
+  let ParserMatchClass = SImmAsmOperand<num>;
 }
 
 def nimm_XFORM : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(~N->getSExtValue(), SDLoc(N), MVT::i32);
 }]>;
 class nimm<int num> : Operand<i32>,
   ImmLeaf<i32, "return isUInt<"#num#">(~Imm);", nimm_XFORM> {
+  let ParserMatchClass = UImmAsmOperand<num>;
 }
 
 
 def oimm12 : oimm<12>;
 
 def nimm12 : nimm<12>;
 
 def uimm5 : uimm<5>;

 def MULT32 : R_YXZ_SP_F1<0x21, 0x1,
   BinOpFrag<(mul node:$LHS, node:$RHS)>, "mult32", 1>;
 def DIVS32 : R_YXZ_SP_F1<0x20, 0x2,
   BinOpFrag<(sdiv node:$LHS, node:$RHS)>, "divs32">;
 def DIVU32 : R_YXZ_SP_F1<0x20, 0x1,
   BinOpFrag<(udiv node:$LHS, node:$RHS)>, "divu32">;
 
 def NOT32 : R_XXZ<0b001001, 0b00100, (outs GPR:$rz), (ins GPR:$rx),
-  "not", [(set GPR:$rz, (not GPR:$rx))]>;
+  "not32", [(set GPR:$rz, (not GPR:$rx))]>;

llvm/lib/Target/CSKY/MCTargetDesc/CMakeLists.txt

 add_llvm_component_library(LLVMCSKYDesc
   CSKYAsmBackend.cpp
   CSKYELFObjectWriter.cpp
+  CSKYInstPrinter.cpp
   CSKYMCAsmInfo.cpp
   CSKYMCTargetDesc.cpp
   CSKYMCCodeEmitter.cpp
 
   LINK_COMPONENTS
-  MC
   CSKYInfo
+  MC
   Support
 
   ADD_TO_COMPONENT
   CSKY
 )

llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.h

+//===-- CSKYInstPrinter.h - Convert CSKY MCInst to asm syntax ---*- C++ -*----//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints a CSKY MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_CSKY_MCTARGETDESC_CSKYINSTPRINTER_H
+#define LLVM_LIB_TARGET_CSKY_MCTARGETDESC_CSKYINSTPRINTER_H
+
+#include "MCTargetDesc/CSKYMCTargetDesc.h"
+#include "llvm/MC/MCInstPrinter.h"
+
+namespace llvm {
+
+class CSKYInstPrinter : public MCInstPrinter {
+public:
+  CSKYInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
+                  const MCRegisterInfo &MRI)
+      : MCInstPrinter(MAI, MII, MRI) {}
+
+  bool applyTargetSpecificCLOption(StringRef Opt) override;
+
+  void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
+                 const MCSubtargetInfo &STI, raw_ostream &O) override;
+  void printRegName(raw_ostream &O, unsigned RegNo) const override;
+
+  void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
+                    raw_ostream &O, const char *Modifier = nullptr);
+
+  // Autogenerated by tblgen.
+  std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
+  void printInstruction(const MCInst *MI, uint64_t Address,
+                        const MCSubtargetInfo &STI, raw_ostream &O);
+  bool printAliasInstr(const MCInst *MI, uint64_t Address,
+                       const MCSubtargetInfo &STI, raw_ostream &O);
+  void printCustomAliasOperand(const MCInst *MI, uint64_t Address,
+                               unsigned OpIdx, unsigned PrintMethodIdx,
+                               const MCSubtargetInfo &STI, raw_ostream &O);
+
+  static const char *getRegisterName(unsigned RegNo);
+  static const char *getRegisterName(unsigned RegNo, unsigned AltIdx);
+};
+
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_CSKY_MCTARGETDESC_CSKYINSTPRINTER_H

llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.cpp

+//===-- CSKYInstPrinter.cpp - Convert CSKY MCInst to asm syntax ---------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an CSKY MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+#include "CSKYInstPrinter.h"
+#include "llvm/MC/MCAsmInfo.h"
+#include "llvm/MC/MCExpr.h"
+#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCSymbol.h"
+#include "llvm/Support/CommandLine.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/FormattedStream.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "csky-asm-printer"
+
+// Include the auto-generated portion of the assembly writer.
+#define PRINT_ALIAS_INSTR
+#include "CSKYGenAsmWriter.inc"
+
+static cl::opt<bool>
+    NoAliases("csky-no-aliases",
+              cl::desc("Disable the emission of assembler pseudo instructions"),
+              cl::init(false), cl::Hidden);
+
+static cl::opt<bool>
+    ArchRegNames("csky-arch-reg-names",
+                 cl::desc("Print architectural register names rather than the "
+                          "ABI names (such as r14 instead of sp)"),
+                 cl::init(false), cl::Hidden);
+
+// The command-line flags above are used by llvm-mc and llc. They can be used by
+// `llvm-objdump`, but we override their values here to handle options passed to
+// `llvm-objdump` with `-M` (which matches GNU objdump). There did not seem to
+// be an easier way to allow these options in all these tools, without doing it
+// this way.
+bool CSKYInstPrinter::applyTargetSpecificCLOption(StringRef Opt) {
+  if (Opt == "no-aliases") {
+    NoAliases = true;
+    return true;
+  }
+  if (Opt == "numeric") {
+    ArchRegNames = true;
+    return true;
+  }
+
+  return false;
+}
+
+void CSKYInstPrinter::printInst(const MCInst *MI, uint64_t Address,
+                                StringRef Annot, const MCSubtargetInfo &STI,
+                                raw_ostream &O) {
+  const MCInst *NewMI = MI;
+
+  if (NoAliases || !printAliasInstr(NewMI, Address, STI, O))
+    printInstruction(NewMI, Address, STI, O);
+  printAnnotation(O, Annot);
+}
+
+void CSKYInstPrinter::printRegName(raw_ostream &O, unsigned RegNo) const {
+  O << getRegisterName(RegNo);
+}
+
+void CSKYInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
+                                   const MCSubtargetInfo &STI, raw_ostream &O,
+                                   const char *Modifier) {
+  assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported");
+  const MCOperand &MO = MI->getOperand(OpNo);
+
+  if (MO.isReg()) {
+    if (MO.getReg() == CSKY::C)
+      O << "";
+    else
+      printRegName(O, MO.getReg());
+    return;
+  }
+
+  if (MO.isImm()) {
+    O << formatImm(MO.getImm());
+    return;
+  }
+
+  assert(MO.isExpr() && "Unknown operand kind in printOperand");
+  MO.getExpr()->print(O, &MAI);
+}
+
+const char *CSKYInstPrinter::getRegisterName(unsigned RegNo) {
+  return getRegisterName(RegNo, ArchRegNames ? CSKY::NoRegAltName
+                                             : CSKY::ABIRegAltName);
+}

llvm/lib/Target/CSKY/MCTargetDesc/CSKYMCTargetDesc.cpp

 //===-- CSKYMCTargetDesc.cpp - CSKY Target Descriptions -------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 ///
 /// This file provides CSKY specific target descriptions.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "CSKYMCTargetDesc.h"
 #include "CSKYAsmBackend.h"
+#include "CSKYInstPrinter.h"
 #include "CSKYMCAsmInfo.h"
 #include "CSKYMCCodeEmitter.h"
 #include "TargetInfo/CSKYTargetInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/TargetRegistry.h"
 
 #define GET_INSTRINFO_MC_DESC
 #include "CSKYGenInstrInfo.inc"
 
 #define GET_REGINFO_MC_DESC
 #include "CSKYGenRegisterInfo.inc"
 
+#define GET_SUBTARGETINFO_MC_DESC
+#include "CSKYGenSubtargetInfo.inc"
+
 using namespace llvm;
 
 static MCAsmInfo *createCSKYMCAsmInfo(const MCRegisterInfo &MRI,
                                       const Triple &TT,
                                       const MCTargetOptions &Options) {
   MCAsmInfo *MAI = new CSKYMCAsmInfo(TT);
 
   // Initial state of the frame pointer is SP.
   unsigned Reg = MRI.getDwarfRegNum(CSKY::R14, true);
   MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa(nullptr, Reg, 0);
   MAI->addInitialFrameState(Inst);
   return MAI;
 }
 
 static MCInstrInfo *createCSKYMCInstrInfo() {
   MCInstrInfo *Info = new MCInstrInfo();
   InitCSKYMCInstrInfo(Info);
   return Info;
 }
 
+static MCInstPrinter *createCSKYMCInstPrinter(const Triple &T,
+                                              unsigned SyntaxVariant,
+                                              const MCAsmInfo &MAI,
+                                              const MCInstrInfo &MII,
+                                              const MCRegisterInfo &MRI) {
+  return new CSKYInstPrinter(MAI, MII, MRI);
+}
+
 static MCRegisterInfo *createCSKYMCRegisterInfo(const Triple &TT) {
   MCRegisterInfo *Info = new MCRegisterInfo();
   InitCSKYMCRegisterInfo(Info, CSKY::R15);
   return Info;
 }
 
+static MCSubtargetInfo *createCSKYMCSubtargetInfo(const Triple &TT,
+                                                  StringRef CPU, StringRef FS) {
+  std::string CPUName = std::string(CPU);
+  if (CPUName.empty())
+    CPUName = "generic";
+  return createCSKYMCSubtargetInfoImpl(TT, CPUName, /*TuneCPU=*/CPUName, FS);
+}
+
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeCSKYTargetMC() {
   auto &CSKYTarget = getTheCSKYTarget();
   TargetRegistry::RegisterMCAsmBackend(CSKYTarget, createCSKYAsmBackend);
   TargetRegistry::RegisterMCAsmInfo(CSKYTarget, createCSKYMCAsmInfo);
   TargetRegistry::RegisterMCInstrInfo(CSKYTarget, createCSKYMCInstrInfo);
   TargetRegistry::RegisterMCRegInfo(CSKYTarget, createCSKYMCRegisterInfo);
   TargetRegistry::RegisterMCCodeEmitter(CSKYTarget, createCSKYMCCodeEmitter);
+  TargetRegistry::RegisterMCInstPrinter(CSKYTarget, createCSKYMCInstPrinter);
+  TargetRegistry::RegisterMCSubtargetInfo(CSKYTarget,
+                                          createCSKYMCSubtargetInfo);
 }

llvm/test/MC/CSKY/basic.s

+# RUN: llvm-mc %s -triple=csky -show-encoding | FileCheck -check-prefixes=CHECK-ASM %s
+
+# CHECK-ASM: addi32 a0, sp, 2
+# CHECK-ASM: encoding: [0x0e,0xe4,0x01,0x00]
+addi32 a0, sp, 2
+
+# CHECK-ASM: subi32 a0, sp, 2
+# CHECK-ASM: encoding: [0x0e,0xe4,0x01,0x10]
+subi32 a0, sp, 2
+
+# CHECK-ASM: andi32 a0, sp, 2
+# CHECK-ASM: encoding: [0x0e,0xe4,0x02,0x20]
+andi32 a0, sp, 2
+
+# CHECK-ASM: andni32 a0, sp, 2
+# CHECK-ASM: encoding: [0x0e,0xe4,0x02,0x30]
+andni32 a0, sp, 2
+
+# CHECK-ASM: xori32 a0, sp, 2
+# CHECK-ASM: encoding: [0x0e,0xe4,0x02,0x40]
+xori32 a0, sp, 2
+
+# CHECK-ASM: lsli32 a0, sp, 2
+# CHECK-ASM: encoding: [0x4e,0xc4,0x20,0x48]
+lsli32 a0, sp, 2
+
+# CHECK-ASM: lsri32 a0, sp, 2
+# CHECK-ASM: encoding: [0x4e,0xc4,0x40,0x48]
+lsri32 a0, sp, 2
+
+# CHECK-ASM: asri32 a0, sp, 2
+# CHECK-ASM: encoding: [0x4e,0xc4,0x80,0x48]
+asri32 a0, sp, 2
+
+
+# CHECK-ASM: addu32 a3, l0, l1
+# CHECK-ASM: encoding: [0xa4,0xc4,0x23,0x00]
+addu32 a3, l0, l1
+
+# CHECK-ASM: subu32 a3, l0, l1
+# CHECK-ASM: encoding: [0xa4,0xc4,0x83,0x00]
+subu32 a3, l0, l1
+
+# CHECK-ASM: and32 a3, l0, l1
+# CHECK-ASM: encoding: [0xa4,0xc4,0x23,0x20]
+and32 a3, l0, l1
+
+# CHECK-ASM: andn32 a3, l0, l1
+# CHECK-ASM: encoding: [0xa4,0xc4,0x43,0x20]
+andn32 a3, l0, l1
+
+# CHECK-ASM: or32 a3, l0, l1
+# CHECK-ASM: encoding: [0xa4,0xc4,0x23,0x24]
+or32 a3, l0, l1
+
+# CHECK-ASM: xor32 a3, l0, l1
+# CHECK-ASM: encoding: [0xa4,0xc4,0x43,0x24]
+xor32 a3, l0, l1
+
+# CHECK-ASM: nor32 a3, l0, l1
+# CHECK-ASM: encoding: [0xa4,0xc4,0x83,0x24]
+nor32 a3, l0, l1
+
+# CHECK-ASM: lsl32 a3, l0, l1
+# CHECK-ASM: encoding: [0xa4,0xc4,0x23,0x40]
+lsl32 a3, l0, l1
+
+# CHECK-ASM: lsr32 a3, l0, l1
+# CHECK-ASM: encoding: [0xa4,0xc4,0x43,0x40]
+lsr32 a3, l0, l1
+
+# CHECK-ASM: asr32 a3, l0, l1
+# CHECK-ASM: encoding: [0xa4,0xc4,0x83,0x40]
+asr32 a3, l0, l1
+
+# CHECK-ASM: mult32 a3, l0, l1
+# CHECK-ASM: encoding: [0xa4,0xc4,0x23,0x84]
+mult32 a3, l0, l1
+
+# CHECK-ASM: divs32 a3, l0, l1
+# CHECK-ASM: encoding: [0xa4,0xc4,0x43,0x80]
+divs32 a3, l0, l1
+
+# CHECK-ASM: divu32 a3, l0, l1
+# CHECK-ASM: encoding: [0xa4,0xc4,0x23,0x80]
+divu32 a3, l0, l1
+
+# CHECK-ASM: not32 a3, l0
+# CHECK-ASM: encoding: [0x84,0xc4,0x83,0x24]
+not32 a3, l0
+
+
+# RUN: not llvm-mc -triple csky --defsym=ERR=1 < %s 2>&1 | FileCheck %s
+
+.ifdef ERR
+
+# uimm12/oimm12/nimm12
+addi32 a0, a0, 0 # CHECK: :[[#@LINE]]:16: error: immediate must be an integer in the range [1, 4096]
+subi32 a0, a0, 4097 # CHECK: :[[#@LINE]]:16: error: immediate must be an integer in the range [1, 4096]
+andi32 a0, a0, 4096 # CHECK: :[[#@LINE]]:16: error: immediate must be an integer in the range [0, 4095]
+andni32 a0, a0, 4096 # CHECK: :[[#@LINE]]:17: error: immediate must be an integer in the range [0, 4095]
+xori32 a0, a0, 4096 # CHECK: :[[#@LINE]]:16: error: immediate must be an integer in the range [0, 4095]
+
+
+# uimm5
+lsli32 a0, a0, 32 # CHECK: :[[#@LINE]]:16: error: immediate must be an integer in the range [0, 31]
+lsri32 a0, a0, 32 # CHECK: :[[#@LINE]]:16: error: immediate must be an integer in the range [0, 31]
+asri32 a0, a0, 32 # CHECK: :[[#@LINE]]:16: error: immediate must be an integer in the range [0, 31]
+
+
+# Invalid mnemonics
+subs t0, t2, t1 # CHECK: :[[#@LINE]]:1: error: unrecognized instruction mnemonic
+nandi t0, t2, 0 # CHECK: :[[#@LINE]]:1: error: unrecognized instruction mnemonic
+
+# Invalid register names
+addi32 foo, sp, 10 # CHECK: :[[#@LINE]]:8: error: unknown operand
+lsli32 a10, a2, 0x20 # CHECK: :[[#@LINE]]:8: error: unknown operand
+asri32 x32, s0, s0 # CHECK: :[[#@LINE]]:8: error: unknown operand
+
+# Invalid operand types
+xori32 sp, 22, 220 # CHECK: :[[#@LINE]]:12: error: invalid operand for instruction
+subu32 t0, t2, 1 # CHECK: :[[#@LINE]]:16: error: invalid operand for instruction
+
+# Too many operands
+subu32 t2, t3, 0x50, 0x60 # CHECK: :[[#@LINE]]:22: error: invalid operand for instruction
+
+# Too few operands
+xori32 a0, a1 # CHECK: :[[#@LINE]]:1: error: too few operands for instruction
+xor32 a0, a2 # CHECK: :[[#@LINE]]:1: error: too few operands for instruction
+
+.endif

llvm/test/MC/CSKY/lit.local.cfg

+if not 'CSKY' in config.root.targets:
+    config.unsupported = True