This is an archive of the discontinued LLVM Phabricator instance.

[RISCV] Define vector single-width reduction intrinsic.
ClosedPublic

Authored by monkchiang on Dec 22 2020, 10:36 PM.

Details

Summary

Define integer reduction:
vredsum/vredmaxu/vredmax/vredminu/vredmin/vredand/vredor/vredxor
Define float reduction:
vfredosum/vfredsum/vfredmax/vfredmin

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>

Diff Detail

Event Timeline

monkchiang created this revision.Dec 22 2020, 10:36 PM
monkchiang requested review of this revision.Dec 22 2020, 10:36 PM
Herald added a project: Restricted Project. · View Herald TranscriptDec 22 2020, 10:36 PM
Herald added a subscriber: MaskRay. · View Herald Transcript
craig.topper added inline comments.Dec 23 2020, 11:53 AM
llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll
6

The description in IntrinsicsRISCV.td says "The LMUL of second source vector must be 1." But this intrinsic has the destination, first, and third sources as LMUL=1 and the second source as LMUL=1/4.

It looks like every test in this file has LMUL=1 destination and the second source vector is the type that varies. So is the comment in IntrinsicsRISCV.td wrong?

Fix comment in IntrinsicsRISCV.td

craig.topper added inline comments.Dec 23 2020, 5:18 PM
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
932

Is earlyclobber needed for these instructions?

Remove redundant constraint in VPseudoReductionV_VS class

This revision is now accepted and ready to land.Dec 24 2020, 12:10 PM
This revision was landed with ongoing or failed builds.Dec 24 2020, 5:56 PM
This revision was automatically updated to reflect the committed changes.