Index: llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
+++ llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
@@ -213,8 +213,12 @@
     if (UseMI == &MI)
       continue;
     if (MO.isDef() || UseMI->getParent() != MI.getParent() ||
-        UseMI->getOpcode() <= TargetOpcode::GENERIC_OP_END ||
-        !TII->isOperandLegal(*UseMI, UseMI->getOperandNo(&MO), &Src))
+        UseMI->getOpcode() <= TargetOpcode::GENERIC_OP_END)
+      return false;
+
+    unsigned OpIdx = UseMI->getOperandNo(&MO);
+    if (OpIdx >= UseMI->getDesc().getNumOperands() ||
+        !TII->isOperandLegal(*UseMI, OpIdx, &Src))
       return false;
   }
   // Change VGPR to SGPR destination.
Index: llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir
+++ llvm/test/CodeGen/AMDGPU/si-fix-sgpr-copies.mir
@@ -72,3 +72,19 @@
     %1:sreg_32_xm0 = COPY %0
     S_ENDPGM 0, implicit %1
 ...
+
+# Make sure there's no assert when looking at the implicit use on S_ENDPGM
+# GCN-LABEL: name: s_to_v_copy_implicit_use
+# GCN: %0:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM undef %1:sreg_64, 0, 0, 0 :: (load 4, addrspace 4)
+# GCN-NEXT: %2:vgpr_32 = COPY %0
+# GCN-NEXT: S_ENDPGM 0, implicit %2
+---
+name: s_to_v_copy_implicit_use
+tracksRegLiveness: true
+body:               |
+  bb.0:
+    %0:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM undef %2:sreg_64, 0, 0, 0 :: (load 4, addrspace 4)
+    %1:vgpr_32 = COPY %0
+    S_ENDPGM 0, implicit %1
+
+...