diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -343,6 +343,9 @@
     // RVV intrinsics may have illegal operands.
     for (auto VT : {MVT::i8, MVT::i16, MVT::i32})
       setOperationAction(ISD::INTRINSIC_WO_CHAIN, VT, Custom);
+
+    for (auto VT : MVT::integer_scalable_vector_valuetypes())
+      setOperationAction(ISD::SPLAT_VECTOR, VT, Legal);
   }
 
   // Function alignments.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -365,29 +365,57 @@
 //===----------------------------------------------------------------------===//
 // Helpers to define the different patterns.
 //===----------------------------------------------------------------------===//
-class VPatBinarySDNode<SDNode vop,
-                       string instruction_name,
-                       ValueType result_type,
-                       ValueType op_type,
-                       ValueType mask_type,
-                       int sew,
-                       LMULInfo vlmul,
-                       VReg RetClass,
-                       VReg op_reg_class> :
+class VPatBinarySDNode_VV<SDNode vop,
+                          string instruction_name,
+                          ValueType result_type,
+                          ValueType op_type,
+                          ValueType mask_type,
+                          int sew,
+                          LMULInfo vlmul,
+                          VReg RetClass,
+                          VReg op_reg_class> :
     Pat<(result_type (vop
                      (op_type op_reg_class:$rs1),
                      (op_type op_reg_class:$rs2))),
-                     (!cast<Instruction>(instruction_name#"_VV_"# vlmul.MX)
+        (!cast<Instruction>(instruction_name#"_VV_"# vlmul.MX)
                      op_reg_class:$rs1,
                      op_reg_class:$rs2,
                      VLMax, sew)>;
 
-multiclass VPatBinarySDNode<SDNode vop, string instruction_name>
+class VPatBinarySDNode_XI<SDNode vop,
+                          string instruction_name,
+                          string suffix,
+                          ValueType result_type,
+                          ValueType vop_type,
+                          ValueType xop_type,
+                          ValueType mask_type,
+                          int sew,
+                          LMULInfo vlmul,
+                          VReg RetClass,
+                          VReg vop_reg_class,
+                          DAGOperand xop_kind> :
+    Pat<(result_type (vop
+                     (vop_type vop_reg_class:$rs1),
+                     (vop_type (splat_vector xop_kind:$rs2)))),
+        (!cast<Instruction>(instruction_name#_#suffix#_# vlmul.MX)
+                     vop_reg_class:$rs1,
+                     xop_kind:$rs2,
+                     VLMax, sew)>;
+
+multiclass VPatBinarySDNode_VV_VX_VI<SDNode vop, string instruction_name,
+                                     Operand ImmType = simm5>
 {
-  foreach vti = AllIntegerVectors in
-    def : VPatBinarySDNode<vop, instruction_name,
-                           vti.Vector, vti.Vector, vti.Mask, vti.SEW,
-                           vti.LMul, vti.RegClass, vti.RegClass>;
+  foreach vti = AllIntegerVectors in {
+    def : VPatBinarySDNode_VV<vop, instruction_name,
+                              vti.Vector, vti.Vector, vti.Mask, vti.SEW,
+                              vti.LMul, vti.RegClass, vti.RegClass>;
+    def : VPatBinarySDNode_XI<vop, instruction_name, "VX",
+                              vti.Vector, vti.Vector, XLenVT, vti.Mask, vti.SEW,
+                              vti.LMul, vti.RegClass, vti.RegClass, GPR>;
+    def : VPatBinarySDNode_XI<vop, instruction_name, "VI",
+                              vti.Vector, vti.Vector, XLenVT, vti.Mask, vti.SEW,
+                              vti.LMul, vti.RegClass, vti.RegClass, ImmType>;
+  }
 }
 
 class VPatBinaryNoMask<string intrinsic_name,
@@ -700,7 +728,7 @@
 //===----------------------------------------------------------------------===//
 
 // Whole-register vector patterns.
-defm "" : VPatBinarySDNode<add, "PseudoVADD">;
+defm "" : VPatBinarySDNode_VV_VX_VI<add, "PseudoVADD">;
 
 //===----------------------------------------------------------------------===//
 // 12. Vector Integer Arithmetic Instructions
diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll
@@ -1943,3 +1943,23 @@
 
   ret <vscale x 16 x i32> %a
 }
+
+define <vscale x 8 x i8> @sdnode_vadd_vx_nxv8i8_i8(<vscale x 8 x i8> %va, i8 signext %b) nounwind {
+; CHECK-LABEL: sdnode_vadd_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, zero, e8,m1,ta,mu
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @sdnode_vadd_vi_nxv8i8_i8(<vscale x 8 x i8> %va) nounwind {
+; CHECK-LABEL: sdnode_vadd_vi_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, zero, e8,m1,ta,mu
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -1
+  %head = insertelement <vscale x 8 x i8> undef, i8 -1, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i8> %vc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll
@@ -2375,3 +2375,23 @@
 
   ret <vscale x 8 x i64> %a
 }
+
+define <vscale x 8 x i8> @sdnode_vadd_vx_nxv8i8_i8(<vscale x 8 x i8> %va, i8 signext %b) nounwind {
+; CHECK-LABEL: sdnode_vadd_vx_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, zero, e8,m1,ta,mu
+; CHECK:       vadd.vx {{v[0-9]+}}, {{v[0-9]+}}, {{a[0-9]+}}
+  %head = insertelement <vscale x 8 x i8> undef, i8 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i8> %vc
+}
+
+define <vscale x 8 x i8> @sdnode_vadd_vi_nxv8i8_i8(<vscale x 8 x i8> %va) nounwind {
+; CHECK-LABEL: sdnode_vadd_vi_nxv8i8_i8
+; CHECK:       vsetvli {{.*}}, zero, e8,m1,ta,mu
+; CHECK:       vadd.vi {{v[0-9]+}}, {{v[0-9]+}}, -1
+  %head = insertelement <vscale x 8 x i8> undef, i8 -1, i32 0
+  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i8> %va, %splat
+  ret <vscale x 8 x i8> %vc
+}