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[RISCV] Define vadc/vmadc/vsbc/vmsbc intrinsics.
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Authored by HsiangKai on Dec 12 2020, 11:32 PM.

Details

Summary

Define vadc/vmadc/vsbc/vmsbc intrinsics and lower to V instructions.

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang@sifive.com>

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Event Timeline

HsiangKai created this revision.Dec 12 2020, 11:32 PM
HsiangKai requested review of this revision.Dec 12 2020, 11:32 PM
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craig.topper added inline comments.Dec 14 2020, 12:40 PM
llvm/test/CodeGen/RISCV/rvv/vmsbc.ll
11 ↗(On Diff #311492)

This test has the ",ta,mu" but none of the other test files do.

craig.topper added a comment.EditedDec 14 2020, 2:59 PM

Do we need to use a NoV0 register class for the output on the vadc/vsbc instructions that have a carry in? from the spec "For vadc and vsbc, an illegal instruction exception is raised if the destination vector register is v0."

I think we might also need earlyclobber on vmadc/vmsbc?

HsiangKai added inline comments.Dec 15 2020, 12:05 AM
llvm/test/CodeGen/RISCV/rvv/vmsbc.ll
11 ↗(On Diff #311492)

I will update other test cases to have ",ta,mu".

Update test cases.

HsiangKai edited the summary of this revision. (Show Details)Dec 15 2020, 12:29 AM
HsiangKai updated this revision to Diff 311829.Dec 15 2020, 1:13 AM

Address @craig.topper's comments.

This revision is now accepted and ready to land.Dec 15 2020, 11:16 AM
This revision was landed with ongoing or failed builds.Dec 15 2020, 2:32 PM
This revision was automatically updated to reflect the committed changes.