Demonstrate how to model RISC-V V intrinsics and lower them to V instructions.
The CodeGen strategy is designed by @rogfer01 from BSC.
HsiangKai on Dec 10 2020, 1:54 AM.Authored by
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The destination vector register group for a masked vector instruction cannot overlap the source mask register (v0), unless the destination vector register is being written with a mask value (e.g., comparisons) or the scalar result of a reduction.