diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -11,6 +11,15 @@
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
+class GenForm<bits<3> Gen> {
+  bit VV = Gen{2};
+  bit VX = Gen{1};
+  bit VI = Gen{0};
+}
+def GenVV_VX_VI : GenForm<0b111>;
+def GenVV_VX: GenForm<0b110>;
+def GenVX_VI: GenForm<0b011>;
+
 // Atomics
 
 // Atomic Intrinsics have multiple versions for different access widths, which
@@ -65,4 +74,76 @@
   // @llvm.riscv.masked.cmpxchg.{i32,i64}.<p>(...)
   defm int_riscv_masked_cmpxchg : MaskedAtomicRMWFiveArgIntrinsics;
 
+
+// optional vl
+multiclass RVV_VL<list<LLVMType> output, list<LLVMType> input,
+list<IntrinsicProperty> attr> {
+
+  defvar vl_input = !listconcat(input, [llvm_anyint_ty]);
+
+  def "" : Intrinsic<output, input, attr>;
+  def _VL : Intrinsic<output, vl_input, attr>;
+}
+
+//  optional mask and maskedoff
+multiclass RVV_M<list<LLVMType> output, list<LLVMType> input,
+list<IntrinsicProperty> attr, bit WithMO = true> {
+  defvar MaskInput = !listconcat(!if(WithMO, [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
+  LLVMMatchType<0>], [LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>]), input);
+
+  defm "" : RVV_VL<output, input, attr>;
+  defm _M : RVV_VL<output, MaskInput, attr>;
+}
+
+// Load unit
+multiclass RVV_LOAD_UNIT {
+  defvar output = [llvm_anyvector_ty];
+  defvar input = [llvm_anyptr_ty];
+  defvar attr = [IntrReadMem, IntrArgMemOnly];
+
+  defm "" : RVV_M<output, input, attr>;
+}
+
+// store unit
+multiclass RVV_STORE_UNIT {
+  defvar output = []<LLVMType>;
+  defvar input = [llvm_anyvector_ty, llvm_anyptr_ty];
+  defvar attr = [IntrWriteMem, IntrArgMemOnly];
+
+  defm "" : RVV_M<output, input, attr, false>;
+}
+//
+// Load/Store
+// support EEW up to ELEN = 64
+foreach EEW = [8, 16, 32, 64] in {
+  defm int_riscv_VLE#EEW#_V : RVV_LOAD_UNIT;
+  defm int_riscv_VSE#EEW#_V : RVV_STORE_UNIT;
+}
+
+
+// with optional mask and maskedoff
+multiclass RVV_ALU_OM<list<LLVMType> output, list<list<LLVMType>> inputs, GenForm Gen> {
+  defvar attr = [IntrNoMem];
+  defvar attr_vi = [IntrNoMem, ImmArg<ArgIndex<1>>];
+
+  if Gen.VV then
+    defm _VV : RVV_M<output, inputs[0], attr>;
+  if Gen.VX then
+    defm _VX : RVV_M<output, inputs[1], attr>;
+  if Gen.VI then
+    defm _VI : RVV_M<output, inputs[2], attr_vi>;
+}
+
+
+defvar RVV_ALU_VV_V_X_I_OM_List = ["VADD"];
+foreach I = RVV_ALU_VV_V_X_I_OM_List in {
+  defvar output = [llvm_anyvector_ty];
+  defvar input_vv =  [LLVMMatchType<0>, LLVMMatchType<0>];
+  defvar input_vx =  [LLVMMatchType<0>, llvm_anyint_ty];
+  defvar input_vi =  [LLVMMatchType<0>, llvm_anyint_ty];
+  defvar inputs = [input_vv, input_vx, input_vi];
+
+  defm int_riscv_#I : RVV_ALU_OM<output, inputs, GenVV_VX_VI>;
+}
+
 } // TargetPrefix = "riscv"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -182,6 +182,54 @@
                          VLMax, sew)>;
 }
 
+multiclass pat_intrinsic_binary<Intrinsic fromOp, Instruction toOp,
+                                ValueType result_type, ValueType op1_type,
+                                ValueType op2_type, ValueType mask_type,
+                                int sew, LMULInfo vlmul, VReg result_reg_class,
+                                VReg op_reg_class, DAGOperand op2_kind> {
+
+    def : Pat<(result_type (fromOp (op1_type op_reg_class:$op1), 
+                                   (op2_type op2_kind:$op2))),
+              (toOp (result_type (IMPLICIT_DEF)), op_reg_class:$op1,
+                                                  op2_kind:$op2,
+                                 (mask_type zero_reg), VLMax, sew)>;
+}
+
+
+
+multiclass pat_intrinsic_binary_common<string op_name, GenForm Gen = GenVV_VX_VI>
+{
+  foreach vti = AllIntegerVectors in {
+    defvar LMulSuffix = vti.LMul.MX;
+    defvar op_vv_name = op_name#_VV;
+    defvar op_vx_name = op_name#_VX;
+    defvar op_vi_name = op_name#_VI;
+
+    if Gen.VV then {
+      defvar intrinsic_vv = !cast<Intrinsic>("int_riscv_"#op_vv_name);
+      defvar pseudo_vv = !cast<Instruction>("Pseudo"#op_vv_name#_#LMulSuffix);
+      defm : pat_intrinsic_binary<intrinsic_vv, pseudo_vv, vti.Vector,
+                                  vti.Vector, vti.Vector, vti.Mask, vti.SEW,
+                                  vti.LMul, vti.RegClass, vti.RegClass,
+                                  vti.RegClass>;
+    }
+    if Gen.VX then {
+      defvar intrinsic_vx = !cast<Intrinsic>("int_riscv_"#op_vx_name);
+      defvar pseudo_vx = !cast<Instruction>("Pseudo"#op_vx_name#_#LMulSuffix);
+      defm : pat_intrinsic_binary<intrinsic_vx, pseudo_vx, vti.Vector,
+                                  vti.Vector, XLenVT, vti.Mask, vti.SEW,
+                                  vti.LMul, vti.RegClass, vti.RegClass, GPR>;
+    }
+    if Gen.VI then {
+      defvar intrinsic_vi = !cast<Intrinsic>("int_riscv_"#op_vi_name);
+      defvar pseudo_vi = !cast<Instruction>("Pseudo"#op_vi_name#_#LMulSuffix);
+      defm : pat_intrinsic_binary<intrinsic_vi, pseudo_vi, vti.Vector,
+                                  vti.Vector, XLenVT, vti.Mask, vti.SEW,
+                                  vti.LMul, vti.RegClass, vti.RegClass, simm5>;
+    }
+  }
+}
+
 multiclass pat_vop_binary_common<SDNode vop,
                                  string instruction_name,
                                  list<VTypeInfo> vtilist>
@@ -253,6 +301,30 @@
   }
 }
 
+multiclass pat_intrinsic_load<string op_name>
+{
+  foreach vti = AllVectors in {
+    defvar intrinsic = !cast<Intrinsic>("int_riscv_"#op_name # vti.SEW # "_V");
+    defvar instruction = !cast<Instruction>("Pseudo"#op_name # vti.SEW # "_V_"#
+                                           vti.LMul.MX);
+  def : Pat<(vti.Vector (intrinsic GPR:$rs1)),
+            (instruction (vti.Vector (IMPLICIT_DEF)), GPR:$rs1,
+                         (vti.Mask zero_reg), VLMax, vti.SEW)>;
+  }
+}
+
+multiclass pat_intrinsic_store<string op_name>
+{
+  foreach vti = AllVectors in {
+    defvar intrinsic = !cast<Intrinsic>("int_riscv_"#op_name # vti.SEW # "_V");
+    defvar instruction = !cast<Instruction>("Pseudo"#op_name # vti.SEW # "_V_"#
+                                           vti.LMul.MX);
+    def : Pat<(intrinsic vti.Vector:$rs2, GPR:$rs1),
+              (instruction vti.RegClass:$rs2, GPR:$rs1, (vti.Mask zero_reg),
+                          VLMax, vti.SEW)>;
+  }
+
+}
 // Patterns.
 multiclass pat_load_store<LLVMType type,
                           LLVMType mask_type,
@@ -291,6 +363,8 @@
                         vti.SEW, vti.LMul, vti.RegClass>;
 }
 
+defm "" : pat_intrinsic_load<"VLE">;
+defm "" :pat_intrinsic_store<"VSE">;
 //===----------------------------------------------------------------------===//
 // 12. Vector Integer Arithmetic Instructions
 //===----------------------------------------------------------------------===//
@@ -305,4 +379,10 @@
 // Whole-register vector patterns.
 defm "" : pat_vop_binary_common<add, "PseudoVADD", AllIntegerVectors>;
 
+
+// intrinsic pattern
+defvar VALU_V_X_I_List = ["VADD"];
+foreach I = VALU_V_X_I_List in  
+  defm "" : pat_intrinsic_binary_common<I, GenVV_VX_VI>;
+
 } // Predicates = [HasStdExtV]
diff --git a/llvm/test/CodeGen/RISCV/rvv/intrinsic-load-add-store-32.ll b/llvm/test/CodeGen/RISCV/rvv/intrinsic-load-add-store-32.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/intrinsic-load-add-store-32.ll
@@ -0,0 +1,118 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple riscv32 -mattr=+experimental-v %s -o - \
+; RUN:     -verify-machineinstrs | FileCheck %s
+; RUN: llc -mtriple riscv64 -mattr=+experimental-v %s -o - \
+; RUN:     -verify-machineinstrs | FileCheck %s
+
+define void @vadd_vint32m1(<vscale x 2 x i32> *%pc, <vscale x 2 x i32> *%pa, <vscale x 2 x i32> *%pb) nounwind {
+; CHECK-LABEL: vadd_vint32m1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a3, zero, e32,m1,tu,mu
+; CHECK-NEXT:    vle32.v v25, (a1)
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,tu,mu
+; CHECK-NEXT:    vle32.v v26, (a2)
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,tu,mu
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsetvli a1, zero, e32,m1,tu,mu
+; CHECK-NEXT:    vse32.v v25, (a0)
+; CHECK-NEXT:    ret
+  %va = tail call <vscale x 2 x i32> @llvm.riscv.VLE32.V.nxv2i32.p0nxv2i32(<vscale x 2 x i32> * %pa)
+  %vb = tail call <vscale x 2 x i32> @llvm.riscv.VLE32.V.nxv2i32.p0nxv2i32(<vscale x 2 x i32> * %pb)
+  %vc = tail call <vscale x 2 x i32> @llvm.riscv.VADD.VV.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb)
+  tail call void @llvm.riscv.VSE32.V.nxv2i32.p0nxv2i32(<vscale x 2 x i32> %vc, <vscale x 2 x i32>* %pc)
+  ret void
+}
+
+define void @vadd_vint32m2(<vscale x 4 x i32> *%pc, <vscale x 4 x i32> *%pa, <vscale x 4 x i32> *%pb) nounwind {
+; CHECK-LABEL: vadd_vint32m2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a3, zero, e32,m2,tu,mu
+; CHECK-NEXT:    vle32.v v26, (a1)
+; CHECK-NEXT:    vsetvli a1, zero, e32,m2,tu,mu
+; CHECK-NEXT:    vle32.v v28, (a2)
+; CHECK-NEXT:    vsetvli a1, zero, e32,m2,tu,mu
+; CHECK-NEXT:    vadd.vv v26, v26, v28
+; CHECK-NEXT:    vsetvli a1, zero, e32,m2,tu,mu
+; CHECK-NEXT:    vse32.v v26, (a0)
+; CHECK-NEXT:    ret
+  %va = tail call <vscale x 4 x i32> @llvm.riscv.VLE32.V.nxv4i32.p0i32(<vscale x 4 x i32> * %pa)
+  %vb = tail call <vscale x 4 x i32> @llvm.riscv.VLE32.V.nxv4i32.p0i32(<vscale x 4 x i32> * %pb)
+  %vc = tail call <vscale x 4 x i32> @llvm.riscv.VADD.VV.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb)
+  tail call void @llvm.riscv.VSE32.V.nxv4i32.p0nxv4i32(<vscale x 4 x i32> %vc, <vscale x 4 x i32>* %pc)
+  ret void
+}
+
+define void @vadd_vint32m4(<vscale x 8 x i32> *%pc, <vscale x 8 x i32> *%pa, <vscale x 8 x i32> *%pb) nounwind {
+; CHECK-LABEL: vadd_vint32m4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a3, zero, e32,m4,tu,mu
+; CHECK-NEXT:    vle32.v v28, (a1)
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,tu,mu
+; CHECK-NEXT:    vle32.v v8, (a2)
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,tu,mu
+; CHECK-NEXT:    vadd.vv v28, v28, v8
+; CHECK-NEXT:    vsetvli a1, zero, e32,m4,tu,mu
+; CHECK-NEXT:    vse32.v v28, (a0)
+; CHECK-NEXT:    ret
+  %va = tail call <vscale x 8 x i32> @llvm.riscv.VLE32.V.nxv8i32.p0i32(<vscale x 8 x i32> * %pa)
+  %vb = tail call <vscale x 8 x i32> @llvm.riscv.VLE32.V.nxv8i32.p0i32(<vscale x 8 x i32> * %pb)
+  %vc = tail call <vscale x 8 x i32> @llvm.riscv.VADD.VV.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb)
+  tail call void @llvm.riscv.VSE32.V.nxv8i32.p0nxv8i32(<vscale x 8 x i32> %vc, <vscale x 8 x i32>* %pc)
+  ret void
+}
+
+define void @vadd_vint32m8(<vscale x 16 x i32> *%pc, <vscale x 16 x i32> *%pa, <vscale x 16 x i32> *%pb) nounwind {
+; CHECK-LABEL: vadd_vint32m8:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a3, zero, e32,m8,tu,mu
+; CHECK-NEXT:    vle32.v v8, (a1)
+; CHECK-NEXT:    vsetvli a1, zero, e32,m8,tu,mu
+; CHECK-NEXT:    vle32.v v16, (a2)
+; CHECK-NEXT:    vsetvli a1, zero, e32,m8,tu,mu
+; CHECK-NEXT:    vadd.vv v8, v8, v16
+; CHECK-NEXT:    vsetvli a1, zero, e32,m8,tu,mu
+; CHECK-NEXT:    vse32.v v8, (a0)
+; CHECK-NEXT:    ret
+  %va = tail call <vscale x 16 x i32> @llvm.riscv.VLE32.V.nxv16i32.p0i32(<vscale x 16 x i32> * %pa)
+  %vb = tail call <vscale x 16 x i32> @llvm.riscv.VLE32.V.nxv16i32.p0i32(<vscale x 16 x i32> * %pb)
+  %vc = tail call <vscale x 16 x i32> @llvm.riscv.VADD.VV.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb)
+  tail call void @llvm.riscv.VSE32.V.nxv16i32.p0nxv16i32(<vscale x 16 x i32> %vc, <vscale x 16 x i32>* %pc)
+  ret void
+}
+
+define void @vadd_vint32mf2(<vscale x 1 x i32> *%pc, <vscale x 1 x i32> *%pa, <vscale x 1 x i32> *%pb) nounwind {
+; CHECK-LABEL: vadd_vint32mf2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a3, zero, e32,mf2,tu,mu
+; CHECK-NEXT:    vle32.v v25, (a1)
+; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,tu,mu
+; CHECK-NEXT:    vle32.v v26, (a2)
+; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,tu,mu
+; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,tu,mu
+; CHECK-NEXT:    vse32.v v25, (a0)
+; CHECK-NEXT:    ret
+  %va = tail call <vscale x 1 x i32> @llvm.riscv.VLE32.V.nxv1i32.p0i32(<vscale x 1 x i32> * %pa)
+  %vb = tail call <vscale x 1 x i32> @llvm.riscv.VLE32.V.nxv1i32.p0i32(<vscale x 1 x i32> * %pb)
+  %vc = tail call <vscale x 1 x i32> @llvm.riscv.VADD.VV.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb)
+  tail call void @llvm.riscv.VSE32.V.nxv1i32.p0nxv1i32(<vscale x 1 x i32> %vc, <vscale x 1 x i32>* %pc)
+  ret void
+}
+declare <vscale x 2 x i32> @llvm.riscv.VLE32.V.nxv2i32.p0nxv2i32(<vscale x 2 x i32>*)
+declare <vscale x 4 x i32> @llvm.riscv.VLE32.V.nxv4i32.p0i32(<vscale x 4 x i32>*)
+declare <vscale x 8 x i32> @llvm.riscv.VLE32.V.nxv8i32.p0i32(<vscale x 8 x i32>*)
+declare <vscale x 16 x i32> @llvm.riscv.VLE32.V.nxv16i32.p0i32(<vscale x 16 x i32>*)
+declare <vscale x 1 x i32> @llvm.riscv.VLE32.V.nxv1i32.p0i32(<vscale x 1 x i32>*)
+
+declare <vscale x 2 x i32> @llvm.riscv.VADD.VV.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>)
+declare <vscale x 4 x i32> @llvm.riscv.VADD.VV.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
+declare <vscale x 8 x i32> @llvm.riscv.VADD.VV.nxv8i32(<vscale x 8 x i32>, <vscale x 8 x i32>)
+declare <vscale x 16 x i32> @llvm.riscv.VADD.VV.nxv16i32(<vscale x 16 x i32>, <vscale x 16 x i32>)
+declare <vscale x 1 x i32> @llvm.riscv.VADD.VV.nxv1i32(<vscale x 1 x i32>, <vscale x 1 x i32>)
+
+declare void @llvm.riscv.VSE32.V.nxv2i32.p0nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>*)
+declare void @llvm.riscv.VSE32.V.nxv4i32.p0nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>*)
+declare void @llvm.riscv.VSE32.V.nxv8i32.p0nxv8i32(<vscale x 8 x i32>, <vscale x 8 x i32>*)
+declare void @llvm.riscv.VSE32.V.nxv16i32.p0nxv16i32(<vscale x 16 x i32>, <vscale x 16 x i32>*)
+declare void @llvm.riscv.VSE32.V.nxv1i32.p0nxv1i32(<vscale x 1 x i32>, <vscale x 1 x i32>*)
+