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Differential D92993

[X86] WIP Swizzle the execution domains for AVX2 targets to prefer integer over floating point
Needs ReviewPublic

Authored by craig.topper on Dec 9 2020, 7:33 PM.

Details

Reviewers
RKSimon
spatel
pengfei
anton-afanasyev
Summary

The execution domain fixing pass defaults to the lowest numbered domain. This patch swizzles the domain numbering at the X86 interface to the pass when AVX2 is enabled so that integer appears to be the lowest numbered domain. This allows us to use the same tables for both cases.

The test updates are incomplete and may no longer apply cleanly. This patch has been sitting on my computer for a while.

Diff Detail

Unit TestsFailed

TimeTest
50 msx64 windows > LLVM.CodeGen/XCore::threads.ll

Event Timeline

craig.topper created this revision.Dec 9 2020, 7:33 PM
Herald added a subscriber: hiraditya. · View Herald TranscriptDec 9 2020, 7:33 PM
craig.topper requested review of this revision.Dec 9 2020, 7:33 PM
Herald added a project: Restricted Project. · View Herald TranscriptDec 9 2020, 7:33 PM
craig.topper mentioned this in D87295: Prefer vpxor over vpxorps for AVX2 PR36127.Dec 9 2020, 7:33 PM
RKSimon added a comment.Dec 10 2020, 8:23 AM

Are you happy to continue work on this or should someone else commandeer it?

llvm/lib/Target/X86/X86InstrInfo.cpp
7624

This probably be set to hasAVX2/hasInt256

7688

This probably be set to hasAVX2/hasInt256

craig.topper updated this revision to Diff 311422.Dec 12 2020, 6:24 PM

change from avx1 to avx2. Update tests

Herald added subscribers: mstorsjo, jfb, arphaman. · View Herald TranscriptDec 12 2020, 6:24 PM
Harbormaster completed remote builds in B82170: Diff 311422.Dec 12 2020, 6:56 PM
craig.topper mentioned this in rG0261ce9e17bd: [X86] Add ExeDomain = SSEPackedSingle to cvtss2sd and cvtsd2ss instrutions..Dec 13 2020, 12:36 PM
craig.topper updated this revision to Diff 311468.Dec 13 2020, 1:22 PM

Rebase after changing the domain for cvtsd2ss/cvtss2sd

Harbormaster completed remote builds in B82201: Diff 311468.Dec 13 2020, 1:52 PM
yubing added a subscriber: yubing.Dec 14 2020, 6:50 PM

Large Diff

This large diff affects 283 files. Files without inline comments have been collapsed. Expand All Files

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Diff 311468

llvm/lib/Target/X86/X86InstrInfo.h

llvm/lib/Target/X86/X86InstrInfo.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===// //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
Lint: Lint
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clang-format not found in user's PATH; not linting file.

Lint: Lint: clang-format not found in user's PATH; not linting file.
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
▲ Show 20 Lines • Show All 7,607 Lines • ▼ Show 20 Lines if (Domain == 1) {
MI.setDesc(get(X86::SHUFPSrri)); MI.setDesc(get(X86::SHUFPSrri));
} }
return true; return true;
} }
} }
return false; return false;
} }
std::pair<uint16_t, uint16_t> std::pair<uint16_t, uint16_t>
RKSimonUnsubmitted
Not Done
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This probably be set to hasAVX2/hasInt256

RKSimon: This probably be set to hasAVX2/hasInt256
X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const { X86InstrInfo::getExecutionDomainImpl(const MachineInstr &MI) const {
uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3; uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
unsigned opcode = MI.getOpcode(); unsigned opcode = MI.getOpcode();
uint16_t validDomains = 0; uint16_t validDomains = 0;
if (domain) { if (domain) {
// Attempt to match for custom instructions. // Attempt to match for custom instructions.
validDomains = getExecutionDomainCustom(MI); validDomains = getExecutionDomainCustom(MI);
if (validDomains) if (validDomains)
return std::make_pair(domain, validDomains); return std::make_pair(domain, validDomains);
Show All 23 Lines if (lookup(opcode, domain, ReplaceableInstrs)) {
else else
validDomains = 0xc; validDomains = 0xc;
} }
} }
} }
return std::make_pair(domain, validDomains); return std::make_pair(domain, validDomains);
} }
void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const { std::pair<uint16_t, uint16_t>
X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
std::pair<uint16_t, uint16_t> Res = getExecutionDomainImpl(MI);
if (Res.first && Subtarget.hasAVX2()) {
// Rotate the domain encodings 1-3 so that 3 becomes 1 to make integer
// prefered.
Res.first = (((Res.first - 1) + 1) % 3) + 1;
Res.second = ((Res.second & 0x6) << 1) | ((Res.second & 0x8) >> 2) |
(Res.second & 0x1);
Lint: Pre-merge checks
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clang-format: please reformat the code

-                  (Res.second & 0x1);
+                 (Res.second & 0x1);
Lint: Pre-merge checks: clang-format: please reformat the code ``` - (Res.second & 0x1); +…
}
return Res;
}
void X86InstrInfo::setExecutionDomainImpl(MachineInstr &MI,
unsigned Domain) const {
assert(Domain>0 && Domain<4 && "Invalid execution domain"); assert(Domain>0 && Domain<4 && "Invalid execution domain");
uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3; uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
assert(dom && "Not an SSE instruction"); assert(dom && "Not an SSE instruction");
// Attempt to match for custom instructions. // Attempt to match for custom instructions.
if (setExecutionDomainCustom(MI, Domain)) if (setExecutionDomainCustom(MI, Domain))
return; return;
RKSimonUnsubmitted
Not Done
ReplyInline Actions

This probably be set to hasAVX2/hasInt256

RKSimon: This probably be set to hasAVX2/hasInt256
const uint16_t *table = lookup(MI.getOpcode(), dom, ReplaceableInstrs); const uint16_t *table = lookup(MI.getOpcode(), dom, ReplaceableInstrs);
if (!table) { // try the other table if (!table) { // try the other table
assert((Subtarget.hasAVX2() || Domain < 3) && assert((Subtarget.hasAVX2() || Domain < 3) &&
"256-bit vector operations only available in AVX2"); "256-bit vector operations only available in AVX2");
table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2); table = lookup(MI.getOpcode(), dom, ReplaceableInstrsAVX2);
} }
if (!table) { // try the FP table if (!table) { // try the FP table
Show All 26 Lines if (!table) { // try the AVX512DQMasked table
table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQMasked); table = lookupAVX512(MI.getOpcode(), dom, ReplaceableInstrsAVX512DQMasked);
if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode())) if (table && Domain == 3 && (dom == 1 || table[3] == MI.getOpcode()))
Domain = 4; Domain = 4;
} }
assert(table && "Cannot change domain"); assert(table && "Cannot change domain");
MI.setDesc(get(table[Domain - 1])); MI.setDesc(get(table[Domain - 1]));
} }
void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
assert(Domain>0 && Domain<4 && "Invalid execution domain");
Lint: Pre-merge checks
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clang-format: please reformat the code

-  assert(Domain>0 && Domain<4 && "Invalid execution domain");
+  assert(Domain > 0 && Domain < 4 && "Invalid execution domain");
Lint: Pre-merge checks: clang-format: please reformat the code ``` - assert(Domain>0 && Domain<4 && "Invalid execution…
if (Subtarget.hasAVX2()) {
// Rotate the domain encoding so that domain 1 becomes 3. So that we prefer
// integer instructions.
Domain = ((Domain - 1) + 2) % 3 + 1;
}
setExecutionDomainImpl(MI, Domain);
}
/// Return the noop instruction to use for a noop. /// Return the noop instruction to use for a noop.
void X86InstrInfo::getNoop(MCInst &NopInst) const { void X86InstrInfo::getNoop(MCInst &NopInst) const {
NopInst.setOpcode(X86::NOOP); NopInst.setOpcode(X86::NOOP);
} }
bool X86InstrInfo::isHighLatencyDef(int opc) const { bool X86InstrInfo::isHighLatencyDef(int opc) const {
switch (opc) { switch (opc) {
default: return false; default: return false;
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llvm/test/CodeGen/X86/sse41-intrinsics-x86.ll

llvm/test/CodeGen/X86/sse41.ll

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