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[X86] Support tilezero intrinsic and c interface for AMX.
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Authored by LuoYuanke on Dec 8 2020, 4:49 AM.

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LuoYuanke created this revision.Dec 8 2020, 4:49 AM
LuoYuanke requested review of this revision.Dec 8 2020, 4:49 AM
Herald added projects: Restricted Project, Restricted Project. · View Herald TranscriptDec 8 2020, 4:49 AM
pengfei added inline comments.Dec 8 2020, 5:48 AM
llvm/lib/Target/X86/X86ExpandPseudo.cpp
499

Can change to i = 3?

llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
4650

Why tilezero needs chain?

LuoYuanke added inline comments.Dec 8 2020, 5:59 AM
llvm/lib/Target/X86/X86ExpandPseudo.cpp
499

Yes, then remove line 498.

llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
4650

I didn't declare "IntrNoMem" in "include/llvm/IR/IntrinsicsX86.td". I can revise the code to declare "IntrNoMem".

Address Pengfei's comments.

LuoYuanke updated this revision to Diff 311375.Dec 12 2020, 4:18 AM

a. Change tilezero back to be chained.

  1. It avoid copy if several tilezero are same. Copy is expensive in AMX.
  2. To keep the original order of amx intrinsics.

b. Refactor __tilezero interface.

LuoYuanke updated this revision to Diff 314157.Dec 30 2020, 6:00 PM

Add avx512f in test case.

pengfei accepted this revision.Dec 30 2020, 7:44 PM

LGTM.

This revision is now accepted and ready to land.Dec 30 2020, 7:44 PM
This revision was landed with ongoing or failed builds.Dec 30 2020, 9:36 PM
This revision was automatically updated to reflect the committed changes.