[Hexagon] Add support for ISD::SMAX/SMIN/UMAX/UMIN instead of custom dag patterns

[RKSimon]

Summary

This should handle the basic integer min/max handling, I may have missed something wrt Hexagon type legalization semantics (for instance it sets add/sub etc to be legal for v4i8/v2i16 types but I couldn't get it to work for min/max).

I haven't been able to get the HVX equivalents to work either - any tips would appreciated.

This is some necessary cleanup work for min/max ops to eventually help us move the add/sub sat patterns into DAGCombine - D91876.

[kparzysz]

Looks great! Thank you for doing this.

llvm/lib/Target/Hexagon/HexagonISelLowering.cpp

HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
 
   if (EmitJumpTables)
     setMinimumJumpTableEntries(MinimumJumpTables);
   else
     setMinimumJumpTableEntries(std::numeric_limits<unsigned>::max());
   setOperationAction(ISD::BR_JT, MVT::Other, Expand);
 
-  setOperationAction(ISD::ABS, MVT::i32, Legal);
-  setOperationAction(ISD::ABS, MVT::i64, Legal);
+  for (unsigned LegalIntOp :
+       {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX}) {
+    setOperationAction(LegalIntOp, MVT::i32, Legal);
+    setOperationAction(LegalIntOp, MVT::i64, Legal);
+  }
 
   // Hexagon has A4_addp_c and A4_subp_c that take and generate a carry bit,
   // but they only operate on i64.
   for (MVT VT : MVT::integer_valuetypes()) {
     setOperationAction(ISD::UADDO,    VT, Custom);
     setOperationAction(ISD::USUBO,    VT, Custom);
     setOperationAction(ISD::SADDO,    VT, Expand);
     setOperationAction(ISD::SSUBO,    VT, Expand);
for (MVT NativeVT : {MVT::v8i1, MVT::v4i1, MVT::v2i1, MVT::v4i8,
     setOperationAction(ISD::AND, NativeVT, Legal);
     setOperationAction(ISD::OR,  NativeVT, Legal);
     setOperationAction(ISD::XOR, NativeVT, Legal);
 
     if (NativeVT.getVectorElementType() != MVT::i1)
       setOperationAction(ISD::SPLAT_VECTOR, NativeVT, Legal);
   }
 
+  for (MVT VT : {MVT::v8i8, MVT::v4i16, MVT::v2i32}) {
+    setOperationAction(ISD::SMIN, VT, Legal);
+    setOperationAction(ISD::SMAX, VT, Legal);
+    setOperationAction(ISD::UMIN, VT, Legal);
+    setOperationAction(ISD::UMAX, VT, Legal);
+  }
+
   // Custom lower unaligned loads.
   // Also, for both loads and stores, verify the alignment of the address
   // in case it is a compile-time constant. This is a usability feature to
   // provide a meaningful error message to users.
   for (MVT VT : {MVT::i16, MVT::i32, MVT::v4i8, MVT::i64, MVT::v8i8,
                  MVT::v2i16, MVT::v4i16, MVT::v2i32}) {
     setOperationAction(ISD::LOAD,  VT, Custom);
     setOperationAction(ISD::STORE, VT, Custom);

llvm/lib/Target/Hexagon/HexagonPatterns.td

 
 // Bitcasts between same-size vector types are no-ops, except for the
 // actual type change.
 multiclass NopCast_pat<ValueType Ty1, ValueType Ty2, RegisterClass RC> {
   def: Pat<(Ty1 (bitconvert (Ty2 RC:$Val))), (Ty1 RC:$Val)>;
   def: Pat<(Ty2 (bitconvert (Ty1 RC:$Val))), (Ty2 RC:$Val)>;
 }
 
-
 // Frags for commonly used SDNodes.
 def Add: pf2<add>;    def And: pf2<and>;    def Sra: pf2<sra>;
 def Sub: pf2<sub>;    def Or:  pf2<or>;     def Srl: pf2<srl>;
 def Mul: pf2<mul>;    def Xor: pf2<xor>;    def Shl: pf2<shl>;
 
+def Smin: pf2<smin>;  def Smax: pf2<smax>;
+def Umin: pf2<umin>;  def Umax: pf2<umax>;
+
 def Rol: pf2<rotl>;
 
 // --(1) Immediate -------------------------------------------------------
 //
 
 def Imm64Lo: SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(int32_t (N->getSExtValue()),
                                    SDLoc(N), MVT::i32);
let AddedComplexity = 200 in {
   defm: SelMinMax16_pats<setle,  A2_min,  A2_max>;
   defm: SelMinMax16_pats<setlt,  A2_min,  A2_max>;
   defm: SelMinMax16_pats<setuge, A2_maxu, A2_minu>;
   defm: SelMinMax16_pats<setugt, A2_maxu, A2_minu>;
   defm: SelMinMax16_pats<setule, A2_minu, A2_maxu>;
   defm: SelMinMax16_pats<setult, A2_minu, A2_maxu>;
 }
 
-let AddedComplexity = 200 in {
-  defm: MinMax_pats<A2_min,   A2_max,   select,  setgt, i1, I32>;
-  defm: MinMax_pats<A2_min,   A2_max,   select,  setge, i1, I32>;
-  defm: MinMax_pats<A2_max,   A2_min,   select,  setlt, i1, I32>;
-  defm: MinMax_pats<A2_max,   A2_min,   select,  setle, i1, I32>;
-  defm: MinMax_pats<A2_minu,  A2_maxu,  select, setugt, i1, I32>;
-  defm: MinMax_pats<A2_minu,  A2_maxu,  select, setuge, i1, I32>;
-  defm: MinMax_pats<A2_maxu,  A2_minu,  select, setult, i1, I32>;
-  defm: MinMax_pats<A2_maxu,  A2_minu,  select, setule, i1, I32>;
-
-  defm: MinMax_pats<A2_minp,  A2_maxp,  select,  setgt, i1, I64>;
-  defm: MinMax_pats<A2_minp,  A2_maxp,  select,  setge, i1, I64>;
-  defm: MinMax_pats<A2_maxp,  A2_minp,  select,  setlt, i1, I64>;
-  defm: MinMax_pats<A2_maxp,  A2_minp,  select,  setle, i1, I64>;
-  defm: MinMax_pats<A2_minup, A2_maxup, select, setugt, i1, I64>;
-  defm: MinMax_pats<A2_minup, A2_maxup, select, setuge, i1, I64>;
-  defm: MinMax_pats<A2_maxup, A2_minup, select, setult, i1, I64>;
-  defm: MinMax_pats<A2_maxup, A2_minup, select, setule, i1, I64>;
-}
+def: OpR_RR_pat<A2_min,   Smin, i32, I32, I32>;
+def: OpR_RR_pat<A2_max,   Smax, i32, I32, I32>;
+def: OpR_RR_pat<A2_minu,  Umin, i32, I32, I32>;
+def: OpR_RR_pat<A2_maxu,  Umax, i32, I32, I32>;
+def: OpR_RR_pat<A2_minp,  Smin, i64, I64, I64>;
+def: OpR_RR_pat<A2_maxp,  Smax, i64, I64, I64>;
+def: OpR_RR_pat<A2_minup, Umin, i64, I64, I64>;
+def: OpR_RR_pat<A2_maxup, Umax, i64, I64, I64>;
 
 let AddedComplexity = 100 in {
   defm: MinMax_pats<F2_sfmin, F2_sfmax, select, setogt, i1, F32>;
   defm: MinMax_pats<F2_sfmin, F2_sfmax, select, setoge, i1, F32>;
   defm: MinMax_pats<F2_sfmax, F2_sfmin, select, setolt, i1, F32>;
   defm: MinMax_pats<F2_sfmax, F2_sfmin, select, setole, i1, F32>;
 }
 
 let AddedComplexity = 100, Predicates = [HasV67] in {
   defm: MinMax_pats<F2_dfmin, F2_dfmax, select, setogt, i1, F64>;
   defm: MinMax_pats<F2_dfmin, F2_dfmax, select, setoge, i1, F64>;
   defm: MinMax_pats<F2_dfmax, F2_dfmin, select, setolt, i1, F64>;
   defm: MinMax_pats<F2_dfmax, F2_dfmin, select, setole, i1, F64>;
 }
 
-defm: MinMax_pats<A2_vminb,  A2_vmaxb,  vselect,  setgt,  v8i1,  V8I8>;
-defm: MinMax_pats<A2_vminb,  A2_vmaxb,  vselect,  setge,  v8i1,  V8I8>;
-defm: MinMax_pats<A2_vminh,  A2_vmaxh,  vselect,  setgt,  v4i1, V4I16>;
-defm: MinMax_pats<A2_vminh,  A2_vmaxh,  vselect,  setge,  v4i1, V4I16>;
-defm: MinMax_pats<A2_vminw,  A2_vmaxw,  vselect,  setgt,  v2i1, V2I32>;
-defm: MinMax_pats<A2_vminw,  A2_vmaxw,  vselect,  setge,  v2i1, V2I32>;
-defm: MinMax_pats<A2_vminub, A2_vmaxub, vselect, setugt,  v8i1,  V8I8>;
-defm: MinMax_pats<A2_vminub, A2_vmaxub, vselect, setuge,  v8i1,  V8I8>;
-defm: MinMax_pats<A2_vminuh, A2_vmaxuh, vselect, setugt,  v4i1, V4I16>;
-defm: MinMax_pats<A2_vminuh, A2_vmaxuh, vselect, setuge,  v4i1, V4I16>;
-defm: MinMax_pats<A2_vminuw, A2_vmaxuw, vselect, setugt,  v2i1, V2I32>;
-defm: MinMax_pats<A2_vminuw, A2_vmaxuw, vselect, setuge,  v2i1, V2I32>;
+def: OpR_RR_pat<A2_vminb,  Smin, v8i8,  V8I8>;
+def: OpR_RR_pat<A2_vmaxb,  Smax, v8i8,  V8I8>;
+def: OpR_RR_pat<A2_vminub, Umin, v8i8,  V8I8>;
+def: OpR_RR_pat<A2_vmaxub, Umax, v8i8,  V8I8>;
+
+def: OpR_RR_pat<A2_vminh,  Smin, v4i16, V4I16>;
+def: OpR_RR_pat<A2_vmaxh,  Smax, v4i16, V4I16>;
+def: OpR_RR_pat<A2_vminuh, Umin, v4i16, V4I16>;
+def: OpR_RR_pat<A2_vmaxuh, Umax, v4i16, V4I16>;
+
+def: OpR_RR_pat<A2_vminw,  Smin, v2i32, V2I32>;
+def: OpR_RR_pat<A2_vmaxw,  Smax, v2i32, V2I32>;
+def: OpR_RR_pat<A2_vminuw, Umin, v2i32, V2I32>;
+def: OpR_RR_pat<A2_vmaxuw, Umax, v2i32, V2I32>;
 
 // --(7) Insert/extract --------------------------------------------------
 //
 
 def SDTHexagonINSERT:
   SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
                        SDTCisInt<0>, SDTCisVT<3, i32>, SDTCisVT<4, i32>]>;
 def HexagonINSERT:    SDNode<"HexagonISD::INSERT",   SDTHexagonINSERT>;

llvm/test/CodeGen/Hexagon/isel-minmax-v64bit.ll

 ; RUN: llc -march=hexagon < %s | FileCheck %s
 
 ; min
 
 ; CHECK-LABEL: test_00:
-; CHECK: r1:0 = vminb(r3:2,r1:0)
+; CHECK: r1:0 = vminb(r1:0,r3:2)
 define <8 x i8> @test_00(<8 x i8> %a0, <8 x i8> %a1) #0 {
   %v0 = icmp slt <8 x i8> %a0, %a1
   %v1 = select <8 x i1> %v0, <8 x i8> %a0, <8 x i8> %a1
   ret <8 x i8> %v1
 }
 
 ; CHECK-LABEL: test_01:
 ; CHECK: r1:0 = vminb(r1:0,r3:2)
 define <8 x i8> @test_01(<8 x i8> %a0, <8 x i8> %a1) #0 {
   %v0 = icmp sle <8 x i8> %a0, %a1
   %v1 = select <8 x i1> %v0, <8 x i8> %a0, <8 x i8> %a1
   ret <8 x i8> %v1
 }
 
 ; CHECK-LABEL: test_02:
-; CHECK: r1:0 = vminh(r3:2,r1:0)
+; CHECK: r1:0 = vminh(r1:0,r3:2)
 define <4 x i16> @test_02(<4 x i16> %a0, <4 x i16> %a1) #0 {
   %v0 = icmp slt <4 x i16> %a0, %a1
   %v1 = select <4 x i1> %v0, <4 x i16> %a0, <4 x i16> %a1
   ret <4 x i16> %v1
 }
 
 ; CHECK-LABEL: test_03:
 ; CHECK: r1:0 = vminh(r1:0,r3:2)
 define <4 x i16> @test_03(<4 x i16> %a0, <4 x i16> %a1) #0 {
   %v0 = icmp sle <4 x i16> %a0, %a1
   %v1 = select <4 x i1> %v0, <4 x i16> %a0, <4 x i16> %a1
   ret <4 x i16> %v1
 }
 
 ; CHECK-LABEL: test_04:
-; CHECK: r1:0 = vminw(r3:2,r1:0)
+; CHECK: r1:0 = vminw(r1:0,r3:2)
 define <2 x i32> @test_04(<2 x i32> %a0, <2 x i32> %a1) #0 {
   %v0 = icmp slt <2 x i32> %a0, %a1
   %v1 = select <2 x i1> %v0, <2 x i32> %a0, <2 x i32> %a1
   ret <2 x i32> %v1
 }
 
 ; CHECK-LABEL: test_05:
 ; CHECK: r1:0 = vminw(r1:0,r3:2)
 define <2 x i32> @test_05(<2 x i32> %a0, <2 x i32> %a1) #0 {
   %v0 = icmp sle <2 x i32> %a0, %a1
   %v1 = select <2 x i1> %v0, <2 x i32> %a0, <2 x i32> %a1
   ret <2 x i32> %v1
 }
 
 ; minu
 
 ; CHECK-LABEL: test_06:
-; CHECK: r1:0 = vminub(r3:2,r1:0)
+; CHECK: r1:0 = vminub(r1:0,r3:2)
 define <8 x i8> @test_06(<8 x i8> %a0, <8 x i8> %a1) #0 {
   %v0 = icmp ult <8 x i8> %a0, %a1
   %v1 = select <8 x i1> %v0, <8 x i8> %a0, <8 x i8> %a1
   ret <8 x i8> %v1
 }
 
 ; CHECK-LABEL: test_07:
 ; CHECK: r1:0 = vminub(r1:0,r3:2)
 define <8 x i8> @test_07(<8 x i8> %a0, <8 x i8> %a1) #0 {
   %v0 = icmp ule <8 x i8> %a0, %a1
   %v1 = select <8 x i1> %v0, <8 x i8> %a0, <8 x i8> %a1
   ret <8 x i8> %v1
 }
 
 ; CHECK-LABEL: test_08:
-; CHECK: r1:0 = vminuh(r3:2,r1:0)
+; CHECK: r1:0 = vminuh(r1:0,r3:2)
 define <4 x i16> @test_08(<4 x i16> %a0, <4 x i16> %a1) #0 {
   %v0 = icmp ult <4 x i16> %a0, %a1
   %v1 = select <4 x i1> %v0, <4 x i16> %a0, <4 x i16> %a1
   ret <4 x i16> %v1
 }
 
 ; CHECK-LABEL: test_09:
 ; CHECK: r1:0 = vminuh(r1:0,r3:2)
 define <4 x i16> @test_09(<4 x i16> %a0, <4 x i16> %a1) #0 {
   %v0 = icmp ule <4 x i16> %a0, %a1
   %v1 = select <4 x i1> %v0, <4 x i16> %a0, <4 x i16> %a1
   ret <4 x i16> %v1
 }
 
 ; CHECK-LABEL: test_0a:
-; CHECK: r1:0 = vminuw(r3:2,r1:0)
+; CHECK: r1:0 = vminuw(r1:0,r3:2)
 define <2 x i32> @test_0a(<2 x i32> %a0, <2 x i32> %a1) #0 {
   %v0 = icmp ult <2 x i32> %a0, %a1
   %v1 = select <2 x i1> %v0, <2 x i32> %a0, <2 x i32> %a1
   ret <2 x i32> %v1
 }
 
 ; CHECK-LABEL: test_0b:
 ; CHECK: r1:0 = vminuw(r1:0,r3:2)

 ; CHECK: r1:0 = vmaxb(r1:0,r3:2)
 define <8 x i8> @test_0c(<8 x i8> %a0, <8 x i8> %a1) #0 {
   %v0 = icmp sgt <8 x i8> %a0, %a1
   %v1 = select <8 x i1> %v0, <8 x i8> %a0, <8 x i8> %a1
   ret <8 x i8> %v1
 }
 
 ; CHECK-LABEL: test_0d:
-; CHECK: r1:0 = vmaxb(r3:2,r1:0)
+; CHECK: r1:0 = vmaxb(r1:0,r3:2)
 define <8 x i8> @test_0d(<8 x i8> %a0, <8 x i8> %a1) #0 {
   %v0 = icmp sge <8 x i8> %a0, %a1
   %v1 = select <8 x i1> %v0, <8 x i8> %a0, <8 x i8> %a1
   ret <8 x i8> %v1
 }
 
 ; CHECK-LABEL: test_0e:
 ; CHECK: r1:0 = vmaxh(r1:0,r3:2)
 define <4 x i16> @test_0e(<4 x i16> %a0, <4 x i16> %a1) #0 {
   %v0 = icmp sgt <4 x i16> %a0, %a1
   %v1 = select <4 x i1> %v0, <4 x i16> %a0, <4 x i16> %a1
   ret <4 x i16> %v1
 }
 
 ; CHECK-LABEL: test_0f:
-; CHECK: r1:0 = vmaxh(r3:2,r1:0)
+; CHECK: r1:0 = vmaxh(r1:0,r3:2)
 define <4 x i16> @test_0f(<4 x i16> %a0, <4 x i16> %a1) #0 {
   %v0 = icmp sge <4 x i16> %a0, %a1
   %v1 = select <4 x i1> %v0, <4 x i16> %a0, <4 x i16> %a1
   ret <4 x i16> %v1
 }
 
 ; CHECK-LABEL: test_10:
 ; CHECK: r1:0 = vmaxw(r1:0,r3:2)
 define <2 x i32> @test_10(<2 x i32> %a0, <2 x i32> %a1) #0 {
   %v0 = icmp sgt <2 x i32> %a0, %a1
   %v1 = select <2 x i1> %v0, <2 x i32> %a0, <2 x i32> %a1
   ret <2 x i32> %v1
 }
 
 ; CHECK-LABEL: test_11:
-; CHECK: r1:0 = vmaxw(r3:2,r1:0)
+; CHECK: r1:0 = vmaxw(r1:0,r3:2)
 define <2 x i32> @test_11(<2 x i32> %a0, <2 x i32> %a1) #0 {
   %v0 = icmp sge <2 x i32> %a0, %a1
   %v1 = select <2 x i1> %v0, <2 x i32> %a0, <2 x i32> %a1
   ret <2 x i32> %v1
 }
 
 ; maxu
 
 ; CHECK-LABEL: test_12:
 ; CHECK: r1:0 = vmaxub(r1:0,r3:2)
 define <8 x i8> @test_12(<8 x i8> %a0, <8 x i8> %a1) #0 {
   %v0 = icmp ugt <8 x i8> %a0, %a1
   %v1 = select <8 x i1> %v0, <8 x i8> %a0, <8 x i8> %a1
   ret <8 x i8> %v1
 }
 
 ; CHECK-LABEL: test_13:
-; CHECK: r1:0 = vmaxub(r3:2,r1:0)
+; CHECK: r1:0 = vmaxub(r1:0,r3:2)
 define <8 x i8> @test_13(<8 x i8> %a0, <8 x i8> %a1) #0 {
   %v0 = icmp uge <8 x i8> %a0, %a1
   %v1 = select <8 x i1> %v0, <8 x i8> %a0, <8 x i8> %a1
   ret <8 x i8> %v1
 }
 
 ; CHECK-LABEL: test_14:
 ; CHECK: r1:0 = vmaxuh(r1:0,r3:2)
 define <4 x i16> @test_14(<4 x i16> %a0, <4 x i16> %a1) #0 {
   %v0 = icmp ugt <4 x i16> %a0, %a1
   %v1 = select <4 x i1> %v0, <4 x i16> %a0, <4 x i16> %a1
   ret <4 x i16> %v1
 }
 
 ; CHECK-LABEL: test_15:
-; CHECK: r1:0 = vmaxuh(r3:2,r1:0)
+; CHECK: r1:0 = vmaxuh(r1:0,r3:2)
 define <4 x i16> @test_15(<4 x i16> %a0, <4 x i16> %a1) #0 {
   %v0 = icmp uge <4 x i16> %a0, %a1
   %v1 = select <4 x i1> %v0, <4 x i16> %a0, <4 x i16> %a1
   ret <4 x i16> %v1
 }
 
 ; CHECK-LABEL: test_16:
 ; CHECK: r1:0 = vmaxuw(r1:0,r3:2)
 define <2 x i32> @test_16(<2 x i32> %a0, <2 x i32> %a1) #0 {
   %v0 = icmp ugt <2 x i32> %a0, %a1
   %v1 = select <2 x i1> %v0, <2 x i32> %a0, <2 x i32> %a1
   ret <2 x i32> %v1
 }
 
 ; CHECK-LABEL: test_17:
-; CHECK: r1:0 = vmaxuw(r3:2,r1:0)
+; CHECK: r1:0 = vmaxuw(r1:0,r3:2)
 define <2 x i32> @test_17(<2 x i32> %a0, <2 x i32> %a1) #0 {
   %v0 = icmp uge <2 x i32> %a0, %a1
   %v1 = select <2 x i1> %v0, <2 x i32> %a0, <2 x i32> %a1
   ret <2 x i32> %v1
 }