Index: lldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_arm64.cpp
===================================================================
--- lldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_arm64.cpp
+++ lldb/source/Plugins/Process/FreeBSD/RegisterContextPOSIXProcessMonitor_arm64.cpp
@@ -37,7 +37,7 @@
 
 bool RegisterContextPOSIXProcessMonitor_arm64::ReadGPR() {
   ProcessMonitor &monitor = GetMonitor();
-  return monitor.ReadGPR(m_thread.GetID(), &m_gpr_arm64, GetGPRSize());
+  return monitor.ReadGPR(m_thread.GetID(), &m_gpr_arm64, sizeof m_gpr_arm64);
 }
 
 bool RegisterContextPOSIXProcessMonitor_arm64::ReadFPR() {
@@ -47,7 +47,7 @@
 
 bool RegisterContextPOSIXProcessMonitor_arm64::WriteGPR() {
   ProcessMonitor &monitor = GetMonitor();
-  return monitor.WriteGPR(m_thread.GetID(), &m_gpr_arm64, GetGPRSize());
+  return monitor.WriteGPR(m_thread.GetID(), &m_gpr_arm64, sizeof m_gpr_arm64);
 }
 
 bool RegisterContextPOSIXProcessMonitor_arm64::WriteFPR() {
Index: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
===================================================================
--- lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
+++ lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
@@ -96,6 +96,8 @@
 
   size_t GetFPRSize() override { return sizeof(m_fpr); }
 
+  size_t GetGPRBufferSize() { return sizeof(m_gpr_arm64); }
+
 private:
   bool m_gpr_is_valid;
   bool m_fpu_is_valid;
Index: lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
===================================================================
--- lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
+++ lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
@@ -936,9 +936,9 @@
 
   struct iovec ioVec;
   ioVec.iov_base = GetGPRBuffer();
-  ioVec.iov_len = GetGPRSize();
+  ioVec.iov_len = GetGPRBufferSize();
 
-  error = ReadRegisterSet(&ioVec, GetGPRSize(), NT_PRSTATUS);
+  error = ReadRegisterSet(&ioVec, GetGPRBufferSize(), NT_PRSTATUS);
 
   if (error.Success())
     m_gpr_is_valid = true;
@@ -953,11 +953,11 @@
 
   struct iovec ioVec;
   ioVec.iov_base = GetGPRBuffer();
-  ioVec.iov_len = GetGPRSize();
+  ioVec.iov_len = GetGPRBufferSize();
 
   m_gpr_is_valid = false;
 
-  return WriteRegisterSet(&ioVec, GetGPRSize(), NT_PRSTATUS);
+  return WriteRegisterSet(&ioVec, GetGPRBufferSize(), NT_PRSTATUS);
 }
 
 Status NativeRegisterContextLinux_arm64::ReadFPR() {
Index: lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
===================================================================
--- lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
+++ lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
@@ -36,6 +36,7 @@
     uint64_t sp;    // x31
     uint64_t pc;    // pc
     uint32_t cpsr;  // cpsr
+    uint32_t pad;   // 4-byte pad for 8-byte alignment
   };
 
   // based on RegisterContextDarwin_arm64.h
Index: lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
===================================================================
--- lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
+++ lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
@@ -15,15 +15,20 @@
 
 #include "RegisterInfoPOSIX_arm64.h"
 
+#define GPR_PAD_BYTES_ARM64 sizeof(uint32_t)
+#define GPR_REGS_SIZE_ARM64                                                    \
+  (sizeof(RegisterInfoPOSIX_arm64::GPR) - GPR_PAD_BYTES_ARM64)
+#define FPU_REGS_SIZE_ARM64 sizeof(RegisterInfoPOSIX_arm64::FPU)
+#define EXC_REGS_SIZE_ARM64 sizeof(RegisterInfoPOSIX_arm64::EXC)
 // Based on RegisterContextDarwin_arm64.cpp
 #define GPR_OFFSET(idx) ((idx)*8)
 #define GPR_OFFSET_NAME(reg)                                                   \
   (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::GPR, reg))
 
-#define FPU_OFFSET(idx) ((idx)*16 + sizeof(RegisterInfoPOSIX_arm64::GPR))
+#define FPU_OFFSET(idx) ((idx)*16 + GPR_REGS_SIZE_ARM64)
 #define FPU_OFFSET_NAME(reg)                                                   \
   (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::FPU, reg) +                \
-   sizeof(RegisterInfoPOSIX_arm64::GPR))
+   GPR_REGS_SIZE_ARM64)
 
 // This information is based on AArch64 with SVE architecture reference manual.
 // AArch64 with SVE has 32 Z and 16 P vector registers. There is also an FFR
@@ -39,19 +44,16 @@
 // vector length requires register context to update sizes of SVE Z, P and FFR.
 // Also register context needs to update byte offsets of all registers affected
 // by the change in vector length.
-#define SVE_REGS_DEFAULT_OFFSET_LINUX sizeof(RegisterInfoPOSIX_arm64::GPR)
+#define SVE_REGS_DEFAULT_OFFSET_LINUX GPR_REGS_SIZE_ARM64
 
 #define SVE_OFFSET_VG SVE_REGS_DEFAULT_OFFSET_LINUX
 
 #define EXC_OFFSET_NAME(reg)                                                   \
   (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::EXC, reg) +                \
-   sizeof(RegisterInfoPOSIX_arm64::GPR) +                                      \
-   sizeof(RegisterInfoPOSIX_arm64::FPU))
+   GPR_REGS_SIZE_ARM64 + FPU_REGS_SIZE_ARM64)
 #define DBG_OFFSET_NAME(reg)                                                   \
   (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::DBG, reg) +                \
-   sizeof(RegisterInfoPOSIX_arm64::GPR) +                                      \
-   sizeof(RegisterInfoPOSIX_arm64::FPU) +                                      \
-   sizeof(RegisterInfoPOSIX_arm64::EXC))
+   GPR_REGS_SIZE_ARM64 + FPU_REGS_SIZE_ARM64 + EXC_REGS_SIZE_ARM64)
 
 #define DEFINE_DBG(reg, i)                                                     \
   #reg, NULL,                                                                  \
@@ -62,9 +64,7 @@
                                dbg_##reg##i },                                 \
                                NULL, NULL, NULL, 0
 #define REG_CONTEXT_SIZE                                                       \
-  (sizeof(RegisterInfoPOSIX_arm64::GPR) +                                      \
-   sizeof(RegisterInfoPOSIX_arm64::FPU) +                                      \
-   sizeof(RegisterInfoPOSIX_arm64::EXC))
+  (GPR_REGS_SIZE_ARM64 + FPU_REGS_SIZE_ARM64 + EXC_REGS_SIZE_ARM64)
 
 // Include RegisterInfos_arm64 to declare our g_register_infos_arm64 structure.
 #define DECLARE_REGISTER_INFOS_ARM64_STRUCT
@@ -214,7 +214,7 @@
 }
 
 size_t RegisterInfoPOSIX_arm64::GetGPRSize() const {
-  return sizeof(struct RegisterInfoPOSIX_arm64::GPR);
+  return GPR_REGS_SIZE_ARM64;
 }
 
 size_t RegisterInfoPOSIX_arm64::GetFPRSize() const {