Index: lib/Target/Mips/Disassembler/MipsDisassembler.cpp =================================================================== --- lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -249,6 +249,11 @@ uint64_t Address, const void *Decoder); +static DecodeStatus DecodePrefeOpMM(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address, @@ -1101,6 +1106,23 @@ return MCDisassembler::Success; } +static DecodeStatus DecodePrefeOpMM(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder) { + int Offset = SignExtend32<9>(Insn & 0x1ff); + unsigned Base = fieldFromInstruction(Insn, 16, 5); + unsigned Hint = fieldFromInstruction(Insn, 21, 5); + + Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + + Inst.addOperand(MCOperand::CreateReg(Base)); + Inst.addOperand(MCOperand::CreateImm(Offset)); + Inst.addOperand(MCOperand::CreateImm(Hint)); + + return MCDisassembler::Success; +} + static DecodeStatus DecodeCacheOpR6(MCInst &Inst, unsigned Insn, uint64_t Address, Index: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h +++ lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h @@ -171,6 +171,9 @@ unsigned getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; + unsigned getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; Index: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp +++ lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp @@ -752,6 +752,18 @@ } unsigned MipsMCCodeEmitter:: +getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + // Base register is encoded in bits 20-16, offset is encoded in bits 11-0. + assert(MI.getOperand(OpNo).isReg()); + unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16; + unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); + + return (OffBits & 0x1FF) | RegBits; +} + +unsigned MipsMCCodeEmitter:: getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo, SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const { Index: lib/Target/Mips/MicroMipsInstrFormats.td =================================================================== --- lib/Target/Mips/MicroMipsInstrFormats.td +++ lib/Target/Mips/MicroMipsInstrFormats.td @@ -922,6 +922,22 @@ let Inst{11-0} = offset; } +class CACHE_PREFE_FM_MM op, bits<3> funct> : MMArch { + bits<21> addr; + bits<5> hint; + bits<5> base = addr{20-16}; + bits<9> offset = addr{8-0}; + + bits<32> Inst; + + let Inst{31-26} = op; + let Inst{25-21} = hint; + let Inst{20-16} = base; + let Inst{15-12} = 0xA; + let Inst{11-9} = funct; + let Inst{8-0} = offset; +} + class BARRIER_FM_MM op> : MMArch { bits<32> Inst; Index: lib/Target/Mips/MicroMipsInstrInfo.td =================================================================== --- lib/Target/Mips/MicroMipsInstrInfo.td +++ lib/Target/Mips/MicroMipsInstrInfo.td @@ -105,6 +105,14 @@ let EncoderMethod = "getMemEncodingMMGPImm7Lsl2"; } +def mem_mm_9 : Operand { + let PrintMethod = "printMemOperand"; + let MIOperandInfo = (ops GPR32, simm12); + let EncoderMethod = "getMemEncodingMMImm9"; + let ParserMatchClass = MipsMemAsmOperand; + let OperandType = "OPERAND_MEMORY"; +} + def mem_mm_12 : Operand { let PrintMethod = "printMemOperand"; let MIOperandInfo = (ops GPR32, simm12); @@ -860,6 +868,13 @@ def PREF_MM : MMRel, CacheOp<"pref", mem_mm_12>, CACHE_PREF_FM_MM<0x18, 0x2>; } + + let DecoderMethod = "DecodePrefeOpMM" in { + def PREFE_MM : MMRel, CacheOp<"prefe", mem_mm_9>, + CACHE_PREFE_FM_MM<0x18, 0x2>; + def CACHEE_MM : MMRel, CacheOp<"cachee", mem_mm_12>, + CACHE_PREFE_FM_MM<0x18, 0x3>; + } def SSNOP_MM : MMRel, Barrier<"ssnop">, BARRIER_FM_MM<0x1>; def EHB_MM : MMRel, Barrier<"ehb">, BARRIER_FM_MM<0x3>; def PAUSE_MM : MMRel, Barrier<"pause">, BARRIER_FM_MM<0x5>; Index: test/MC/Disassembler/Mips/micromips.txt =================================================================== --- test/MC/Disassembler/Mips/micromips.txt +++ test/MC/Disassembler/Mips/micromips.txt @@ -504,3 +504,9 @@ # CHECK: movep $5, $6, $2, $3 0x84 0x34 + +# CHECK: prefe 1, 8($5) +0x60 0x25 0xa4 0x08 + +# CHECK: cachee 1, 8($5) +0x60 0x25 0xa6 0x08 Index: test/MC/Disassembler/Mips/micromips_le.txt =================================================================== --- test/MC/Disassembler/Mips/micromips_le.txt +++ test/MC/Disassembler/Mips/micromips_le.txt @@ -504,3 +504,9 @@ # CHECK: movep $5, $6, $2, $3 0x34 0x84 + +# CHECK: prefe 1, 8($5) +0x25 0x60 0x08 0xa4 + +# CHECK: cachee 1, 8($5) +0x25 0x60 0x08 0xa6 Index: test/MC/Mips/micromips-control-instructions.s =================================================================== --- test/MC/Mips/micromips-control-instructions.s +++ test/MC/Mips/micromips-control-instructions.s @@ -39,6 +39,8 @@ # CHECK-EL: tlbr # encoding: [0x00,0x00,0x7c,0x13] # CHECK-EL: tlbwi # encoding: [0x00,0x00,0x7c,0x23] # CHECK-EL: tlbwr # encoding: [0x00,0x00,0x7c,0x33] +# CHECK-EL: prefe 1, 8($5) # encoding: [0x25,0x60,0x08,0xa4] +# CHECK-EL: cachee 1, 8($5) # encoding: [0x25,0x60,0x08,0xa6] #------------------------------------------------------------------------------ # Big endian #------------------------------------------------------------------------------ @@ -72,6 +74,8 @@ # CHECK-EB: tlbr # encoding: [0x00,0x00,0x13,0x7c] # CHECK-EB: tlbwi # encoding: [0x00,0x00,0x23,0x7c] # CHECK-EB: tlbwr # encoding: [0x00,0x00,0x33,0x7c] +# CHECK-EB: prefe 1, 8($5) # encoding: [0x60,0x25,0xa4,0x08] +# CHECK-EB: cachee 1, 8($5) # encoding: [0x60,0x25,0xa6,0x08] sdbbp sdbbp 34 @@ -100,3 +104,5 @@ tlbr tlbwi tlbwr + prefe 1, 8($5) + cachee 1, 8($5)