[NFC][AMDGPU] Remove some generic pointers in memory-legalizer tests

[scott.linder]

Summary

These tests implicitly depend on the target supporting generic pointers,
so to prepare for testing them on GFX6 (which lacks FLAT) remove the
dependency where possible.

[rampitec]

LGTM

llvm/test/CodeGen/AMDGPU/memory-legalizer-load.ll

 ; GCN-LABEL: {{^}}nontemporal_private_0:
 ; GFX89: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offen glc slc{{$}}
 ; GFX10: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offen slc{{$}}
 ; GFX10:         .amdhsa_kernel nontemporal_private_0
 ; GFX10WGP-NOT:  .amdhsa_workgroup_processor_mode 0
 ; GFX10CU:       .amdhsa_workgroup_processor_mode 0
 ; GFX10-NOT:     .amdhsa_memory_ordered 0
 define amdgpu_kernel void @nontemporal_private_0(
-    i32 addrspace(5)* %in, i32* %out) {
+    i32 addrspace(5)* %in, i32 addrspace(1)* %out) {
 entry:
   %val = load i32, i32 addrspace(5)* %in, align 4, !nontemporal !0
-  store i32 %val, i32* %out
+  store i32 %val, i32 addrspace(1)* %out
   ret void
 }
 
 ; GCN-LABEL: {{^}}nontemporal_private_1:
 ; GFX89: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offen glc slc{{$}}
 ; GFX10: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offen slc{{$}}
 ; GFX10:         .amdhsa_kernel nontemporal_private_1
 ; GFX10WGP-NOT:  .amdhsa_workgroup_processor_mode 0
 ; GFX10CU:       .amdhsa_workgroup_processor_mode 0
 ; GFX10-NOT:     .amdhsa_memory_ordered 0
 define amdgpu_kernel void @nontemporal_private_1(
-    i32 addrspace(5)* %in, i32* %out) {
+    i32 addrspace(5)* %in, i32 addrspace(1)* %out) {
 entry:
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %val.gep = getelementptr inbounds i32, i32 addrspace(5)* %in, i32 %tid
   %val = load i32, i32 addrspace(5)* %val.gep, align 4, !nontemporal !0
-  store i32 %val, i32* %out
+  store i32 %val, i32 addrspace(1)* %out
   ret void
 }
 
 ; GCN-LABEL: {{^}}nontemporal_global_0:
 ; GCN: s_load_dword s{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0x0{{$}}
 ; GFX10:         .amdhsa_kernel nontemporal_global_0
 ; GFX10WGP-NOT:  .amdhsa_workgroup_processor_mode 0
 ; GFX10CU:       .amdhsa_workgroup_processor_mode 0
 ; GFX10-NOT:     .amdhsa_memory_ordered 0
 define amdgpu_kernel void @nontemporal_global_0(
-    i32 addrspace(1)* %in, i32* %out) {
+    i32 addrspace(1)* %in, i32 addrspace(1)* %out) {
 entry:
   %val = load i32, i32 addrspace(1)* %in, align 4, !nontemporal !0
-  store i32 %val, i32* %out
+  store i32 %val, i32 addrspace(1)* %out
   ret void
 }
 
 ; GCN-LABEL: {{^}}nontemporal_global_1:
 ; GFX8:  flat_load_dword v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}] glc slc{{$}}
 ; GFX9:  global_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}] glc slc{{$}}
 ; GFX10: global_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}] slc{{$}}
 ; GFX10:         .amdhsa_kernel nontemporal_global_1
 ; GFX10WGP-NOT:  .amdhsa_workgroup_processor_mode 0
 ; GFX10CU:       .amdhsa_workgroup_processor_mode 0
 ; GFX10-NOT:     .amdhsa_memory_ordered 0
 define amdgpu_kernel void @nontemporal_global_1(
-    i32 addrspace(1)* %in, i32* %out) {
+    i32 addrspace(1)* %in, i32 addrspace(1)* %out) {
 entry:
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %val.gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 %tid
   %val = load i32, i32 addrspace(1)* %val.gep, align 4, !nontemporal !0
-  store i32 %val, i32* %out
+  store i32 %val, i32 addrspace(1)* %out
   ret void
 }
 
 ; GCN-LABEL: {{^}}nontemporal_local_0:
 ; GCN: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}}{{$}}
 ; GFX10:         .amdhsa_kernel nontemporal_local_0
 ; GFX10WGP-NOT:  .amdhsa_workgroup_processor_mode 0
 ; GFX10CU:       .amdhsa_workgroup_processor_mode 0
 ; GFX10-NOT:     .amdhsa_memory_ordered 0
 define amdgpu_kernel void @nontemporal_local_0(
-    i32 addrspace(3)* %in, i32* %out) {
+    i32 addrspace(3)* %in, i32 addrspace(1)* %out) {
 entry:
   %val = load i32, i32 addrspace(3)* %in, align 4, !nontemporal !0
-  store i32 %val, i32* %out
+  store i32 %val, i32 addrspace(1)* %out
   ret void
 }
 
 ; GCN-LABEL: {{^}}nontemporal_local_1:
 ; GCN: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}}{{$}}
 ; GFX10:         .amdhsa_kernel nontemporal_local_1
 ; GFX10WGP-NOT:  .amdhsa_workgroup_processor_mode 0
 ; GFX10CU:       .amdhsa_workgroup_processor_mode 0
 ; GFX10-NOT:     .amdhsa_memory_ordered 0
 define amdgpu_kernel void @nontemporal_local_1(
-    i32 addrspace(3)* %in, i32* %out) {
+    i32 addrspace(3)* %in, i32 addrspace(1)* %out) {
 entry:
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %val.gep = getelementptr inbounds i32, i32 addrspace(3)* %in, i32 %tid
   %val = load i32, i32 addrspace(3)* %val.gep, align 4, !nontemporal !0
-  store i32 %val, i32* %out
+  store i32 %val, i32 addrspace(1)* %out
   ret void
 }
 
 ; GCN-LABEL: {{^}}nontemporal_flat_0:
 ; GFX89: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}] glc slc{{$}}
 ; GFX10: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}] slc{{$}}
 ; GFX10:         .amdhsa_kernel nontemporal_flat_0
 ; GFX10WGP-NOT:  .amdhsa_workgroup_processor_mode 0

llvm/test/CodeGen/AMDGPU/memory-legalizer-store.ll

 ; GCN-LABEL: {{^}}nontemporal_private_0:
 ; GFX89: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offen glc slc{{$}}
 ; GFX10: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offen slc{{$}}
 ; GFX10:         .amdhsa_kernel nontemporal_private_0
 ; GFX10WGP-NOT:  .amdhsa_workgroup_processor_mode 0
 ; GFX10CU:       .amdhsa_workgroup_processor_mode 0
 ; GFX10-NOT:     .amdhsa_memory_ordered 0
 define amdgpu_kernel void @nontemporal_private_0(
-    i32* %in, i32 addrspace(5)* %out) {
+    i32 addrspace(1)* %in, i32 addrspace(5)* %out) {
 entry:
-  %val = load i32, i32* %in, align 4
+  %val = load i32, i32 addrspace(1)* %in, align 4
   store i32 %val, i32 addrspace(5)* %out, !nontemporal !0
   ret void
 }
 
 ; GCN-LABEL: {{^}}nontemporal_private_1:
 ; GFX89: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offen glc slc{{$}}
 ; GFX10: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offen slc{{$}}
 ; GFX10:         .amdhsa_kernel nontemporal_private_1
 ; GFX10WGP-NOT:  .amdhsa_workgroup_processor_mode 0
 ; GFX10CU:       .amdhsa_workgroup_processor_mode 0
 ; GFX10-NOT:     .amdhsa_memory_ordered 0
 define amdgpu_kernel void @nontemporal_private_1(
-    i32* %in, i32 addrspace(5)* %out) {
+    i32 addrspace(1)* %in, i32 addrspace(5)* %out) {
 entry:
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
-  %val = load i32, i32* %in, align 4
+  %val = load i32, i32 addrspace(1)* %in, align 4
   %out.gep = getelementptr inbounds i32, i32 addrspace(5)* %out, i32 %tid
   store i32 %val, i32 addrspace(5)* %out.gep, !nontemporal !0
   ret void
 }
 
 ; GCN-LABEL: {{^}}nontemporal_global_0:
 ; GFX8:  flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc slc{{$}}
 ; GFX9:  global_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}} glc slc{{$}}
 ; GFX10: global_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}} slc{{$}}
 ; GFX10:         .amdhsa_kernel nontemporal_global_0
 ; GFX10WGP-NOT:  .amdhsa_workgroup_processor_mode 0
 ; GFX10CU:       .amdhsa_workgroup_processor_mode 0
 ; GFX10-NOT:     .amdhsa_memory_ordered 0
 define amdgpu_kernel void @nontemporal_global_0(
-    i32* %in, i32 addrspace(1)* %out) {
+    i32 addrspace(1)* %in, i32 addrspace(1)* %out) {
 entry:
-  %val = load i32, i32* %in, align 4
+  %val = load i32, i32 addrspace(1)* %in, align 4
   store i32 %val, i32 addrspace(1)* %out, !nontemporal !0
   ret void
 }
 
 ; GCN-LABEL: {{^}}nontemporal_global_1:
 ; GFX8:  flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc slc{{$}}
 ; GFX9:  global_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}] glc slc{{$}}
 ; GFX10: global_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}] slc{{$}}
 ; GFX10:         .amdhsa_kernel nontemporal_global_1
 ; GFX10WGP-NOT:  .amdhsa_workgroup_processor_mode 0
 ; GFX10CU:       .amdhsa_workgroup_processor_mode 0
 ; GFX10-NOT:     .amdhsa_memory_ordered 0
 define amdgpu_kernel void @nontemporal_global_1(
-    i32* %in, i32 addrspace(1)* %out) {
+    i32 addrspace(1)* %in, i32 addrspace(1)* %out) {
 entry:
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
-  %val = load i32, i32* %in, align 4
+  %val = load i32, i32 addrspace(1)* %in, align 4
   %out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %tid
   store i32 %val, i32 addrspace(1)* %out.gep, !nontemporal !0
   ret void
 }
 
 ; GCN-LABEL: {{^}}nontemporal_local_0:
 ; GCN: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}}{{$}}
 ; GFX10:         .amdhsa_kernel nontemporal_local_0
 ; GFX10WGP-NOT:  .amdhsa_workgroup_processor_mode 0
 ; GFX10CU:       .amdhsa_workgroup_processor_mode 0
 ; GFX10-NOT:     .amdhsa_memory_ordered 0
 define amdgpu_kernel void @nontemporal_local_0(
-    i32* %in, i32 addrspace(3)* %out) {
+    i32 addrspace(1)* %in, i32 addrspace(3)* %out) {
 entry:
-  %val = load i32, i32* %in, align 4
+  %val = load i32, i32 addrspace(1)* %in, align 4
   store i32 %val, i32 addrspace(3)* %out, !nontemporal !0
   ret void
 }
 
 ; GCN-LABEL: {{^}}nontemporal_local_1:
 ; GCN: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}}{{$}}
 ; GFX10:         .amdhsa_kernel nontemporal_local_1
 ; GFX10WGP-NOT:  .amdhsa_workgroup_processor_mode 0
 ; GFX10CU:       .amdhsa_workgroup_processor_mode 0
 ; GFX10-NOT:     .amdhsa_memory_ordered 0
 define amdgpu_kernel void @nontemporal_local_1(
-    i32* %in, i32 addrspace(3)* %out) {
+    i32 addrspace(1)* %in, i32 addrspace(3)* %out) {
 entry:
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
-  %val = load i32, i32* %in, align 4
+  %val = load i32, i32 addrspace(1)* %in, align 4
   %out.gep = getelementptr inbounds i32, i32 addrspace(3)* %out, i32 %tid
   store i32 %val, i32 addrspace(3)* %out.gep, !nontemporal !0
   ret void
 }
 
 ; GCN-LABEL: {{^}}nontemporal_flat_0:
 ; GFX89: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc slc{{$}}
 ; GFX10: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} slc{{$}}