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[VE] Add lvm/svm intrinsic instructions
ClosedPublic

Authored by kaz7 on Nov 16 2020, 6:50 AM.

Details

Summary

Add lvm/svm intrinsic instructions and a regression test. Change
RegisterInfo to specify that VM0/VMP0 are constant and reserved
registers. This modifies a vst regression test, so update it.
Also add pseudo instructions for VM512 register classes
and mechanism to expand them after register allocation.

Diff Detail

Event Timeline

kaz7 created this revision.Nov 16 2020, 6:50 AM
kaz7 requested review of this revision.Nov 16 2020, 6:50 AM
simoll added inline comments.Nov 16 2020, 7:22 AM
llvm/lib/Target/VE/VEInstrInfo.cpp
743–744

Looks like a good application for the Register type, here and for Src, VMX, ..

kaz7 updated this revision to Diff 305517.Nov 16 2020, 7:51 AM

Rebased to the upstream/master and change to use Register.

simoll accepted this revision.Nov 16 2020, 8:26 AM
This revision is now accepted and ready to land.Nov 16 2020, 8:26 AM
This revision was landed with ongoing or failed builds.Nov 16 2020, 2:05 PM
This revision was automatically updated to reflect the committed changes.