[PowerPC] Add support for intrinsics dcbfps and dcbstps in P10.

[Esme]

Summary

This patch added support for the intrinsics llvm.ppc.dcbfps and llvm.ppc.dcbstps.
dcbfps and dcbstps are actually extended mnemonics of dcbf.

dcbfps RA,RB ---> dcbf RA,RB,4
dcbstps RA,RB ---> dcbf RA,RB,6

[amyk]

This LGTM.

llvm/test/CodeGen/PowerPC/dcbf-p10.ll

2

I think it would be good to add a BE line when testing new intrinsics.

[Esme]

Added a BE line in the test.

[steven.zhang]

llvm/include/llvm/IR/IntrinsicsPowerPC.td

38

I didn't go into the detail of the definition of the intrinsic. But could you please double confirm if we need to set IntrWriteMem, IntrArgMemOnly as it seems that dbcf stuff is trying to write memory.

[Esme]

llvm/include/llvm/IR/IntrinsicsPowerPC.td

38

Thanks for your comment. The dcbf_ instructions perform the writes to main storage instead of memory. So there is no need to set IntrWriteMem, IntrArgMemOnly. Please correct me if I am wrong.

[Esme]

According to ISA,

DCBF (Data Cache Block Flush) is treated as a Load, except that reference and change recording need not be done.

it is appropriate to set IntrReadMem, IntrArgMemOnly for these dcbf_ instructions.

[steven.zhang]

LGTM now.

[Esme]

@steven.zhang I still have some doubts about the properties setting. According to the behavior described by ISA, it also includes the write operation?

...those locations are written to main storage and additional locations in the block may be written to main storage...

I think it would be a safer way to only set IntrArgMemOnly.

llvm/include/llvm/IR/IntrinsicsPowerPC.td

let TargetPrefix = "ppc" in {  // All intrinsics start with "llvm.ppc.".
   def int_ppc_dcbtst: Intrinsic<[], [llvm_ptr_ty],
     [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
   def int_ppc_dcbt_with_hint: Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty],
     [IntrArgMemOnly, NoCapture<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
   def int_ppc_dcbtst_with_hint: Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty],
     [IntrArgMemOnly, NoCapture<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
   def int_ppc_dcbz  : Intrinsic<[], [llvm_ptr_ty], []>;
   def int_ppc_dcbzl : Intrinsic<[], [llvm_ptr_ty], []>;
+  def int_ppc_dcbfps : Intrinsic<[], [llvm_ptr_ty], []>;
+  def int_ppc_dcbstps: Intrinsic<[], [llvm_ptr_ty], []>;
 
   // Population Count in each Byte.
   def int_ppc_popcntb : Intrinsic<[llvm_i64_ty], [llvm_i64_ty], [IntrNoMem]>;
 
   // sync instruction (i.e. sync 0, a.k.a hwsync)
   def int_ppc_sync : Intrinsic<[], [], []>;
   // isync instruction
   def int_ppc_isync : Intrinsic<[], [], []>;

llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp

case PPC::DCBTSTDS: {
     TmpInst.addOperand(Inst.getOperand(2));
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     Inst = TmpInst;
     break;
   }
   case PPC::DCBFx:
   case PPC::DCBFL:
-  case PPC::DCBFLP: {
+  case PPC::DCBFLP:
+  case PPC::DCBFPS:
+  case PPC::DCBSTPS: {
     int L = 0;
     if (Opcode == PPC::DCBFL)
       L = 1;
     else if (Opcode == PPC::DCBFLP)
       L = 3;
+    else if (Opcode == PPC::DCBFPS)
+      L = 4;
+    else if (Opcode == PPC::DCBSTPS)
+      L = 6;
 
     MCInst TmpInst;
     TmpInst.setOpcode(PPC::DCBF);
     TmpInst.addOperand(MCOperand::createImm(L));
     TmpInst.addOperand(Inst.getOperand(0));
     TmpInst.addOperand(Inst.getOperand(1));
     Inst = TmpInst;
     break;

llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp

if (!IsBookE && TH != 0 && TH != 16)
       O << ", " << (unsigned int) TH;
 
     printAnnotation(O, Annot);
     return;
   }
 
   if (MI->getOpcode() == PPC::DCBF) {
     unsigned char L = MI->getOperand(0).getImm();
-    if (!L || L == 1 || L == 3) {
-      O << "\tdcbf";
-      if (L == 1 || L == 3)
+    if (!L || L == 1 || L == 3 || L == 4 || L == 6) {
+      O << "\tdcb";
+      if (L != 6)
+        O << "f";
+      if (L == 1)
         O << "l";
       if (L == 3)
-        O << "p";
+        O << "lp";
+      if (L == 4)
+        O << "ps";
+      if (L == 6)
+        O << "stps";
       O << " ";
 
       printOperand(MI, 1, O);
       O << ", ";
       printOperand(MI, 2, O);
 
       printAnnotation(O, Annot);
       return;

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 def DCBFLP : PPCAsmPseudo<"dcbflp $dst", (ins memrr:$dst)>;
 
 def : Pat<(int_ppc_isync),  (ISYNC)>;
 def : Pat<(int_ppc_dcbfl xoaddr:$dst),
           (DCBF 1, xoaddr:$dst)>;
 def : Pat<(int_ppc_dcbflp xoaddr:$dst),
           (DCBF 3, xoaddr:$dst)>;
 
+let Predicates = [IsISA3_1] in {
+  def DCBFPS  : PPCAsmPseudo<"dcbfps $dst", (ins memrr:$dst)>;
+  def DCBSTPS : PPCAsmPseudo<"dcbstps $dst", (ins memrr:$dst)>;
+
+  def : Pat<(int_ppc_dcbfps xoaddr:$dst),
+            (DCBF 4, xoaddr:$dst)>;
+  def : Pat<(int_ppc_dcbstps xoaddr:$dst),
+            (DCBF 6, xoaddr:$dst)>;
+}
+
 def : InstAlias<"crset $bx", (CREQV crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
 def : InstAlias<"crclr $bx", (CRXOR crbitrc:$bx, crbitrc:$bx, crbitrc:$bx)>;
 def : InstAlias<"crmove $bx, $by", (CROR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
 def : InstAlias<"crnot $bx, $by", (CRNOR crbitrc:$bx, crbitrc:$by, crbitrc:$by)>;
 
 def : InstAlias<"mftb $Rx", (MFTB gprc:$Rx, 268)>;
 def : InstAlias<"mftbl $Rx", (MFTB gprc:$Rx, 268)>;
 def : InstAlias<"mftbu $Rx", (MFTB gprc:$Rx, 269)>;

llvm/test/CodeGen/PowerPC/dcbf-p10.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s \
+; RUN:     -verify-machineinstrs -ppc-asm-full-reg-names \
+; RUN:     -ppc-vsr-nums-as-vr -mcpu=pwr10 | FileCheck %s
+
+; Function Attrs: nounwind
+define void @dcbfps_test(i8* %a) {
+; CHECK-LABEL: dcbfps_test:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addi r3, r3, 3
+; CHECK-NEXT:    dcbfps 0, r3
+; CHECK-NEXT:    blr
+entry:
+  %add.a = getelementptr inbounds i8, i8* %a, i64 3
+  tail call void @llvm.ppc.dcbfps(i8* %add.a)
+ret void
+}
+
+declare void @llvm.ppc.dcbfps(i8*)
+
+; Function Attrs: nounwind
+define void @dcbstps_test(i8* %a) {
+; CHECK-LABEL: dcbstps_test:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addi r3, r3, 3
+; CHECK-NEXT:    dcbstps 0, r3
+; CHECK-NEXT:    blr
+entry:
+  %add.a = getelementptr inbounds i8, i8* %a, i64 3
+  tail call void @llvm.ppc.dcbstps(i8* %add.a)
+ret void
+}
+
+declare void @llvm.ppc.dcbstps(i8*)