diff --git a/llvm/lib/Object/ELFObjectFile.cpp b/llvm/lib/Object/ELFObjectFile.cpp
--- a/llvm/lib/Object/ELFObjectFile.cpp
+++ b/llvm/lib/Object/ELFObjectFile.cpp
@@ -331,6 +331,12 @@
       case 'c':
         Features.AddFeature(Arch.take_front());
         break;
+      case 'b':
+        Features.AddFeature("experimental-b");
+        break;
+      case 'v':
+        Features.AddFeature("experimental-v");
+        break;
       case 'z':
         if (Arch.consume_front("zfh")) {
           Features.AddFeature("experimental-zfh");
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2139,6 +2139,10 @@
         setFeatureBits(RISCV::FeatureStdExtD, "d");
       } else if (Arch[0] == 'c') {
         setFeatureBits(RISCV::FeatureStdExtC, "c");
+      } else if (Arch[0] == 'b') {
+        setFeatureBits(RISCV::FeatureStdExtB, "experimental-b");
+      } else if (Arch[0] == 'v') {
+        setFeatureBits(RISCV::FeatureStdExtV, "experimental-v");
       } else if (Arch.consume_front("zfh")) {
         setFeatureBits(RISCV::FeatureExtZfh, "experimental-zfh");
         drop_char_num = 3;
@@ -2182,6 +2186,10 @@
         formalArchStr = (Twine(formalArchStr) + "_d2p0").str();
       if (getFeatureBits(RISCV::FeatureStdExtC))
         formalArchStr = (Twine(formalArchStr) + "_c2p0").str();
+      if (getFeatureBits(RISCV::FeatureStdExtB))
+        formalArchStr = (Twine(formalArchStr) + "_b0p92").str();
+      if (getFeatureBits(RISCV::FeatureStdExtV))
+        formalArchStr = (Twine(formalArchStr) + "_v0p9").str();
       if (getFeatureBits(RISCV::FeatureExtZfh))
         formalArchStr = (Twine(formalArchStr) + "_zfh0p1").str();
 
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -60,6 +60,10 @@
     Arch += "_d2p0";
   if (STI.hasFeature(RISCV::FeatureStdExtC))
     Arch += "_c2p0";
+  if (STI.hasFeature(RISCV::FeatureStdExtB))
+    Arch += "_b0p92";
+  if (STI.hasFeature(RISCV::FeatureStdExtV))
+    Arch += "_v0p9";
   if (STI.hasFeature(RISCV::FeatureExtZfh))
     Arch += "_zfh0p1";
 
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -5,6 +5,10 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+f %s -o - | FileCheck --check-prefix=RV32F %s
 ; RUN: llc -mtriple=riscv32 -mattr=+d %s -o - | FileCheck --check-prefix=RV32D %s
 ; RUN: llc -mtriple=riscv32 -mattr=+c %s -o - | FileCheck --check-prefix=RV32C %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-b %s -o - \
+; RUN:   | FileCheck --check-prefix=RV32B %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v %s -o - \
+; RUN:   | FileCheck --check-prefix=RV32V %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh %s -o - \
 ; RUN:   | FileCheck --check-prefix=RV32ZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
@@ -12,6 +16,10 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefix=RV64D %s
 ; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefix=RV64C %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-b %s -o - \
+; RUN:   | FileCheck --check-prefix=RV64B %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v %s -o - \
+; RUN:   | FileCheck --check-prefix=RV64V %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh %s -o - \
 ; RUN:   | FileCheck --check-prefix=RV64ZFH %s
 
@@ -20,12 +28,16 @@
 ; RV32F: .attribute 5, "rv32i2p0_f2p0"
 ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"
+; RV32B: .attribute 5, "rv32i2p0_b0p92"
+; RV32V: .attribute 5, "rv32i2p0_f2p0_v0p9"
 ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1"
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64A: .attribute 5, "rv64i2p0_a2p0"
 ; RV64F: .attribute 5, "rv64i2p0_f2p0"
 ; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0"
 ; RV64C: .attribute 5, "rv64i2p0_c2p0"
+; RV64B: .attribute 5, "rv64i2p0_b0p92"
+; RV64V: .attribute 5, "rv64i2p0_f2p0_v0p9"
 ; RV64ZFH: .attribute 5, "rv64i2p0_f2p0_zfh0p1"
 
 define i32 @addi(i32 %a) {
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -36,5 +36,11 @@
 .attribute arch, "rv32ima2p_fdc"
 # CHECK: attribute      5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
-.attribute arch, "rv32ima2p_fdczfh0p1"
-# CHECK: attribute      5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zfh0p1"
+.attribute arch, "rv32ima2p_fdcb0p92"
+# CHECK: attribute      5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_b0p92"
+
+.attribute arch, "rv32ima2p_fdcb0p92_v0p9"
+# CHECK: attribute      5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_b0p92_v0p9"
+
+.attribute arch, "rv32ima2p_fdcb0p92_v0p9_zfh0p1"
+# CHECK: attribute      5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_b0p92_v0p9_zfh0p1"
diff --git a/llvm/test/MC/RISCV/attribute.s b/llvm/test/MC/RISCV/attribute.s
--- a/llvm/test/MC/RISCV/attribute.s
+++ b/llvm/test/MC/RISCV/attribute.s
@@ -6,8 +6,8 @@
 .attribute stack_align, 16
 # CHECK: attribute      4, 16
 
-.attribute arch, "rv32i2p0_m2p0_a2p0_c2p0_zfh0p1"
-# CHECK: attribute      5, "rv32i2p0_m2p0_a2p0_f2p0_c2p0_zfh0p1"
+.attribute arch, "rv32i2p0_m2p0_a2p0_c2p0_b0p92_v0p9_zfh0p1"
+# CHECK: attribute      5, "rv32i2p0_m2p0_a2p0_f2p0_c2p0_b0p92_v0p9_zfh0p1"
 
 .attribute unaligned_access, 0
 # CHECK: attribute      6, 0