[RISCV] ELF attribute for B and V extension.

[HsiangKai]

Summary

ELF attribute for B and V extension.

[jrtc27]

What about all the Zb*?

[kito-cheng]

I think zv* need to set too, seems like we should have more word about extension is consisted with several sub-extensions on the ELF attribute spec.

[HsiangKai]

D94931 is more complete.

llvm/lib/Object/ELFObjectFile.cpp

while (!Arch.empty()) {
         LLVM_FALLTHROUGH;
       case 'e':
       case 'm':
       case 'a':
       case 'f':
       case 'c':
         Features.AddFeature(Arch.take_front());
         break;
+      case 'b':
+        Features.AddFeature("experimental-b");
+        break;
+      case 'v':
+        Features.AddFeature("experimental-v");
+        break;
       case 'z':
         if (Arch.consume_front("zfh")) {
           Features.AddFeature("experimental-zfh");
           Features.AddFeature("f"); // Zfh implies F extension.
         }
         break;
       }
 

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

while (!Arch.empty()) {
         setFeatureBits(RISCV::FeatureStdExtA, "a");
       else if (Arch[0] == 'f')
         setFeatureBits(RISCV::FeatureStdExtF, "f");
       else if (Arch[0] == 'd') {
         setFeatureBits(RISCV::FeatureStdExtF, "f");
         setFeatureBits(RISCV::FeatureStdExtD, "d");
       } else if (Arch[0] == 'c') {
         setFeatureBits(RISCV::FeatureStdExtC, "c");
+      } else if (Arch[0] == 'b') {
+        setFeatureBits(RISCV::FeatureStdExtB, "experimental-b");
+      } else if (Arch[0] == 'v') {
+        setFeatureBits(RISCV::FeatureStdExtV, "experimental-v");
       } else if (Arch.consume_front("zfh")) {
         setFeatureBits(RISCV::FeatureExtZfh, "experimental-zfh");
         drop_char_num = 3;
       } else
         return Error(ValueExprLoc, "bad arch string " + Arch);
 
       Arch = Arch.drop_front(drop_char_num);
       int major = 0;
if (Tag != RISCVAttrs::ARCH) {
       if (getFeatureBits(RISCV::FeatureStdExtA))
         formalArchStr = (Twine(formalArchStr) + "_a2p0").str();
       if (getFeatureBits(RISCV::FeatureStdExtF))
         formalArchStr = (Twine(formalArchStr) + "_f2p0").str();
       if (getFeatureBits(RISCV::FeatureStdExtD))
         formalArchStr = (Twine(formalArchStr) + "_d2p0").str();
       if (getFeatureBits(RISCV::FeatureStdExtC))
         formalArchStr = (Twine(formalArchStr) + "_c2p0").str();
+      if (getFeatureBits(RISCV::FeatureStdExtB))
+        formalArchStr = (Twine(formalArchStr) + "_b0p92").str();
+      if (getFeatureBits(RISCV::FeatureStdExtV))
+        formalArchStr = (Twine(formalArchStr) + "_v0p9").str();
       if (getFeatureBits(RISCV::FeatureExtZfh))
         formalArchStr = (Twine(formalArchStr) + "_zfh0p1").str();
 
       getTargetStreamer().emitTextAttribute(Tag, formalArchStr);
     }
   }
 
   return false;

llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp

void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
   if (STI.hasFeature(RISCV::FeatureStdExtA))
     Arch += "_a2p0";
   if (STI.hasFeature(RISCV::FeatureStdExtF))
     Arch += "_f2p0";
   if (STI.hasFeature(RISCV::FeatureStdExtD))
     Arch += "_d2p0";
   if (STI.hasFeature(RISCV::FeatureStdExtC))
     Arch += "_c2p0";
+  if (STI.hasFeature(RISCV::FeatureStdExtB))
+    Arch += "_b0p92";
+  if (STI.hasFeature(RISCV::FeatureStdExtV))
+    Arch += "_v0p9";
   if (STI.hasFeature(RISCV::FeatureExtZfh))
     Arch += "_zfh0p1";
 
   emitTextAttribute(RISCVAttrs::ARCH, Arch);
 }
 
 // This part is for ascii assembly output
 RISCVTargetAsmStreamer::RISCVTargetAsmStreamer(MCStreamer &S,

llvm/test/CodeGen/RISCV/attributes.ll

 ;; Generate ELF attributes from llc.
 
 ; RUN: llc -mtriple=riscv32 -mattr=+m %s -o - | FileCheck --check-prefix=RV32M %s
 ; RUN: llc -mtriple=riscv32 -mattr=+a %s -o - | FileCheck --check-prefix=RV32A %s
 ; RUN: llc -mtriple=riscv32 -mattr=+f %s -o - | FileCheck --check-prefix=RV32F %s
 ; RUN: llc -mtriple=riscv32 -mattr=+d %s -o - | FileCheck --check-prefix=RV32D %s
 ; RUN: llc -mtriple=riscv32 -mattr=+c %s -o - | FileCheck --check-prefix=RV32C %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-b %s -o - \
+; RUN:   | FileCheck --check-prefix=RV32B %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v %s -o - \
+; RUN:   | FileCheck --check-prefix=RV32V %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfh %s -o - \
 ; RUN:   | FileCheck --check-prefix=RV32ZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefix=RV64A %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefix=RV64F %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefix=RV64D %s
 ; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefix=RV64C %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-b %s -o - \
+; RUN:   | FileCheck --check-prefix=RV64B %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v %s -o - \
+; RUN:   | FileCheck --check-prefix=RV64V %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfh %s -o - \
 ; RUN:   | FileCheck --check-prefix=RV64ZFH %s
 
 ; RV32M: .attribute 5, "rv32i2p0_m2p0"
 ; RV32A: .attribute 5, "rv32i2p0_a2p0"
 ; RV32F: .attribute 5, "rv32i2p0_f2p0"
 ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"
+; RV32B: .attribute 5, "rv32i2p0_b0p92"
+; RV32V: .attribute 5, "rv32i2p0_f2p0_v0p9"
 ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1"
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64A: .attribute 5, "rv64i2p0_a2p0"
 ; RV64F: .attribute 5, "rv64i2p0_f2p0"
 ; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0"
 ; RV64C: .attribute 5, "rv64i2p0_c2p0"
+; RV64B: .attribute 5, "rv64i2p0_b0p92"
+; RV64V: .attribute 5, "rv64i2p0_f2p0_v0p9"
 ; RV64ZFH: .attribute 5, "rv64i2p0_f2p0_zfh0p1"
 
 define i32 @addi(i32 %a) {
   %1 = add i32 %a, 1
   ret i32 %1
 }

llvm/test/MC/RISCV/attribute-arch.s

 # CHECK: attribute      5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
 .attribute arch, "rv32ima2p0_fdc"
 # CHECK: attribute      5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
 .attribute arch, "rv32ima2p_fdc"
 # CHECK: attribute      5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
-.attribute arch, "rv32ima2p_fdczfh0p1"
-# CHECK: attribute      5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zfh0p1"
+.attribute arch, "rv32ima2p_fdcb0p92"
+# CHECK: attribute      5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_b0p92"
+
+.attribute arch, "rv32ima2p_fdcb0p92_v0p9"
+# CHECK: attribute      5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_b0p92_v0p9"
+
+.attribute arch, "rv32ima2p_fdcb0p92_v0p9_zfh0p1"
+# CHECK: attribute      5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_b0p92_v0p9_zfh0p1"

llvm/test/MC/RISCV/attribute.s

 ## Test llvm-mc could handle .attribute correctly.
 
 # RUN: llvm-mc %s -triple=riscv32 -filetype=asm | FileCheck %s
 # RUN: llvm-mc %s -triple=riscv64 -filetype=asm | FileCheck %s
 
 .attribute stack_align, 16
 # CHECK: attribute      4, 16
 
-.attribute arch, "rv32i2p0_m2p0_a2p0_c2p0_zfh0p1"
-# CHECK: attribute      5, "rv32i2p0_m2p0_a2p0_f2p0_c2p0_zfh0p1"
+.attribute arch, "rv32i2p0_m2p0_a2p0_c2p0_b0p92_v0p9_zfh0p1"
+# CHECK: attribute      5, "rv32i2p0_m2p0_a2p0_f2p0_c2p0_b0p92_v0p9_zfh0p1"
 
 .attribute unaligned_access, 0
 # CHECK: attribute      6, 0
 
 .attribute priv_spec, 2
 # CHECK: attribute      8, 2
 
 .attribute priv_spec_minor, 0
 # CHECK: attribute      10, 0
 
 .attribute priv_spec_revision, 0
 # CHECK: attribute      12, 0