diff --git a/llvm/include/llvm/IR/IntrinsicsNVVM.td b/llvm/include/llvm/IR/IntrinsicsNVVM.td --- a/llvm/include/llvm/IR/IntrinsicsNVVM.td +++ b/llvm/include/llvm/IR/IntrinsicsNVVM.td @@ -128,7 +128,7 @@ !eq(A.ptx_elt_type, "u4") : [A], !eq(A.ptx_elt_type, "b1") : [A], // the rest are FP ops identified by accumulator & result type. - 1: [D, C] + true: [D, C] ); string ret = !foldl("", id_frags, a, b, !strconcat(a, ".", b.ptx_elt_type)); } @@ -294,7 +294,7 @@ !eq(t, "s4") : [], !eq(t, "u4") : [], // All other (non sub-int) are OK. - 1: [1] + true: [1] ); } @@ -307,8 +307,8 @@ string Name = "int_nvvm_shfl_" # Suffix; string Builtin = "__nvvm_shfl_" # Suffix; string IntrName = "llvm.nvvm.shfl." # !subst("_",".", Suffix); - list withGccBuiltin = !if(return_pred, [], [1]); - list withoutGccBuiltin = !if(return_pred, [1], []); + bit withGccBuiltin = !not(return_pred); + bit withoutGccBuiltin = return_pred; LLVMType OpType = !cond( !eq(type,"i32"): llvm_i32_ty, !eq(type,"f32"): llvm_float_ty); @@ -3998,18 +3998,18 @@ // SHUFFLE // // Generate intrinsics for all variants of shfl instruction. -foreach sync = [0, 1] in { +foreach sync = [false, true] in { foreach mode = ["up", "down", "bfly", "idx"] in { foreach type = ["i32", "f32"] in { - foreach return_pred = [0, 1] in { + foreach return_pred = [false, true] in { foreach i = [SHFL_INFO] in { - foreach _ = i.withGccBuiltin in { + if i.withGccBuiltin then { def i.Name : GCCBuiltin, Intrinsic; } - foreach _ = i.withoutGccBuiltin in { + if i.withoutGccBuiltin then { def i.Name : Intrinsic; }