[WebAssembly] Support fp reg class in r constraint

[snek]

Apologies, I didn't realize uploading this would immediately request review... I still need to figure out tests.

[aheejin]

This comment was removed by aheejin.

[snek]

Could someone point me to where tests for this sort of thing are?

[aheejin]

It seems we have inline asm tests here: https://github.com/llvm/llvm-project/blob/master/llvm/test/CodeGen/WebAssembly/inline-asm.ll

[aheejin]

LGTM. Do you have commit access? If not, I can commit this for you. You can also provide your name and email address if you want, so that I can use your info for the commit, as described here: https://llvm.org/docs/Phabricator.html#committing-someone-s-change-from-phabricator

[snek]

I don't have commit perms (or at least I hope I don't, seeing as this is my first contribution). You can put the author in as snek <[e-mail]>.

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

case 'r':
           return std::make_pair(0U, &WebAssembly::V128RegClass);
       }
       if (VT.isInteger() && !VT.isVector()) {
         if (VT.getSizeInBits() <= 32)
           return std::make_pair(0U, &WebAssembly::I32RegClass);
         if (VT.getSizeInBits() <= 64)
           return std::make_pair(0U, &WebAssembly::I64RegClass);
       }
+      if (VT.isFloatingPoint() && !VT.isVector()) {
+        switch (VT.getSizeInBits()) {
+        case 32:
+          return std::make_pair(0U, &WebAssembly::F32RegClass);
+        case 64:
+          return std::make_pair(0U, &WebAssembly::F64RegClass);
+        default:
+          break;
+        }
+      }
       break;
     default:
       break;
     }
   }
 
   return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
 }

llvm/test/CodeGen/WebAssembly/inline-asm.ll

 ; CHECK-NEXT: local.get $push0=, 0{{$}}
 ; CHECK-NEXT: return $pop0{{$}}
 define i64 @foo_i64(i64 %r) {
 entry:
   %0 = tail call i64 asm sideeffect "# $0 = aaa($1)", "=r,r"(i64 %r) #0, !srcloc !0
   ret i64 %0
 }
 
+; CHECK-LABEL: foo_float:
+; CHECK-NEXT: .functype foo_float (f32) -> (f32){{$}}
+; CHECK-NEXT: #APP{{$}}
+; CHECK-NEXT: # 0 = aaa(0){{$}}
+; CHECK-NEXT: #NO_APP{{$}}
+; CHECK-NEXT: local.get $push0=, 0{{$}}
+; CHECK-NEXT: return $pop0{{$}}
+define float @foo_float(float %r) {
+entry:
+  %0 = tail call float asm sideeffect "# $0 = aaa($1)", "=r,r"(float %r) #0, !srcloc !0
+  ret float %0
+}
+
+; CHECK-LABEL: foo_double:
+; CHECK-NEXT: .functype foo_double (f64) -> (f64){{$}}
+; CHECK-NEXT: #APP{{$}}
+; CHECK-NEXT: # 0 = aaa(0){{$}}
+; CHECK-NEXT: #NO_APP{{$}}
+; CHECK-NEXT: local.get $push0=, 0{{$}}
+; CHECK-NEXT: return $pop0{{$}}
+define double @foo_double(double %r) {
+entry:
+  %0 = tail call double asm sideeffect "# $0 = aaa($1)", "=r,r"(double %r) #0, !srcloc !0
+  ret double %0
+}
+
 ; CHECK-LABEL: X_i16:
 ; CHECK: foo 1{{$}}
 ; CHECK: local.get $push[[S0:[0-9]+]]=, 0{{$}}
 ; CHECK-NEXT: local.get $push[[S1:[0-9]+]]=, 1{{$}}
 ; CHECK-NEXT: i32.store16 0($pop[[S0]]), $pop[[S1]]{{$}}
 define void @X_i16(i16 * %t) {
   call void asm sideeffect "foo $0", "=*X,~{dirflag},~{fpsr},~{flags},~{memory}"(i16* %t)
   ret void