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Differential D90854

[RISCV] Custom lowering of FLT_ROUNDS_
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Authored by sepavloff on Nov 5 2020, 8:06 AM.

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Reviewers
asb
craig.topper
luismarques
jrtc27
lenary

Diff Detail

Event Timeline

sepavloff created this revision.Nov 5 2020, 8:06 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 5 2020, 8:06 AM
Herald added subscribers: frasercrmck, NickHung, evandro and 23 others. · View Herald Transcript
sepavloff requested review of this revision.Nov 5 2020, 8:06 AM
Herald added a subscriber: MaskRay. · View Herald TranscriptNov 5 2020, 8:06 AM
sepavloff added a parent revision: D90853: [RISCV] Add DAG nodes to represent read/write CSR.Nov 5 2020, 8:07 AM
Harbormaster completed remote builds in B77704: Diff 303125.Nov 5 2020, 8:14 AM
sepavloff updated this revision to Diff 304877.Nov 12 2020, 9:47 AM

Small changes similar to those made in D91242

jrtc27 added inline comments.Nov 12 2020, 9:52 AM
llvm/lib/Target/RISCV/RISCVISelLowering.h
258–262
sepavloff updated this revision to Diff 304889.Nov 12 2020, 10:12 AM

Fixed comments

  • IEEE-754 rounding direction names are replaced by llvm::RoundingMode enumerators,
  • Fixed comment for RDN.
Harbormaster completed remote builds in B78640: Diff 304877.Nov 12 2020, 10:46 AM
Harbormaster completed remote builds in B78646: Diff 304889.Nov 12 2020, 11:05 AM
lenary resigned from this revision.Jan 14 2021, 9:46 AM
sepavloff mentioned this in D94163: [RISCV] Set dependency on floating point CSRs, 1/3.Mar 4 2021, 10:48 PM
sepavloff updated this revision to Diff 332680.Tue, Mar 23, 8:12 AM

Adapted the patch for alternative CSR implementation

Herald added a subscriber: vkmr. · View Herald TranscriptTue, Mar 23, 8:12 AM
Harbormaster completed remote builds in B95275: Diff 332680.Tue, Mar 23, 8:12 AM
sepavloff edited parent revisions, added: D99083: [RISCV] Introduce floating point control and state registers; removed: D90853: [RISCV] Add DAG nodes to represent read/write CSR.Tue, Mar 23, 8:15 AM
sepavloff mentioned this in D99083: [RISCV] Introduce floating point control and state registers.Wed, Apr 7, 8:47 PM

Revision Contents
Changeset List

PathSize
llvm/
lib/
Target/
RISCV/
21 lines
47 lines
test/
CodeGen/
RISCV/
27 lines

Diff 332680

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llvm/lib/Target/RISCV/RISCVISelLowering.h

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llvm/lib/Target/RISCV/RISCVISelLowering.cpp

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llvm/test/CodeGen/RISCV/fpenv.ll

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