diff --git a/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp b/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
--- a/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
+++ b/llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
@@ -1374,9 +1374,38 @@
     return ResTy;
 
   switch (getLexer().getKind()) {
-  case AsmToken::LParen:
-    // FIXME: Parsing "(" + %vreg + ", " + %vreg + ")"
-    // FALLTHROUGH
+  case AsmToken::LParen: {
+    // Parsing "(" + %vreg + ", " + %vreg + ")"
+    const AsmToken Tok1 = Parser.getTok();
+    Parser.Lex(); // Eat the '('.
+
+    unsigned RegNo1;
+    SMLoc S1, E1;
+    if (tryParseRegister(RegNo1, S1, E1) != MatchOperand_Success) {
+      getLexer().UnLex(Tok1);
+      return MatchOperand_NoMatch;
+    }
+
+    if (!Parser.getTok().is(AsmToken::Comma))
+      return MatchOperand_ParseFail;
+    Parser.Lex(); // Eat the ','.
+
+    unsigned RegNo2;
+    SMLoc S2, E2;
+    if (tryParseRegister(RegNo2, S2, E2) != MatchOperand_Success)
+      return MatchOperand_ParseFail;
+
+    if (!Parser.getTok().is(AsmToken::RParen))
+      return MatchOperand_ParseFail;
+
+    Operands.push_back(VEOperand::CreateToken(Tok1.getString(), Tok1.getLoc()));
+    Operands.push_back(VEOperand::CreateReg(RegNo1, S1, E1));
+    Operands.push_back(VEOperand::CreateReg(RegNo2, S2, E2));
+    Operands.push_back(VEOperand::CreateToken(Parser.getTok().getString(),
+                                              Parser.getTok().getLoc()));
+    Parser.Lex(); // Eat the ')'.
+    break;
+  }
   default: {
     std::unique_ptr<VEOperand> Op;
     ResTy = parseVEAsmOperand(Op);
diff --git a/llvm/lib/Target/VE/VEInstrVec.td b/llvm/lib/Target/VE/VEInstrVec.td
--- a/llvm/lib/Target/VE/VEInstrVec.td
+++ b/llvm/lib/Target/VE/VEInstrVec.td
@@ -522,6 +522,48 @@
   let cy = 0, sy = 0 in
   defm "" : RVmm<opcStr, "", opc, RC, RCM, (ins)>;
 }
+// Generic RV multiclass with 2 arguments for shift operations.
+//   e.g. VSLL, VSRL, VSLA, and etc.
+let VE_VLIndex = 3 in
+multiclass RVSm<string opcStr, bits<8>opc, RegisterClass ScaRC,
+                RegisterClass RC, RegisterClass RCM> {
+  let cy = 0, sy = 0, vy = ?, vz = ? in
+  defm vv : RVmm<opcStr, ", $vz, $vy", opc, RC, RCM, (ins RC:$vz, RC:$vy)>;
+  let cs = 1, vz = ? in
+  defm vr : RVmm<opcStr, ", $vz, $sy", opc, RC, RCM, (ins RC:$vz, ScaRC:$sy)>;
+  let cs = 1, cy = 0, vz = ? in
+  defm vi : RVmm<opcStr, ", $vz, $sy", opc, RC, RCM, (ins RC:$vz, uimm7:$sy)>;
+}
+// Generic RV multiclass with 3 arguments for shift operations.
+//   e.g. VSLD and VSRD.
+let VE_VLIndex = 4 in
+multiclass RVSDm<string opcStr, bits<8>opc, RegisterClass RC,
+                 RegisterClass RCM> {
+  let vy = ?, vz = ? in
+  defm vvr : RVmm<opcStr, ", ($vy, ${vz}), $sy", opc, RC, RCM,
+                 (ins RC:$vy, RC:$vz, I64:$sy)>;
+  let cy = 0, vy = ?, vz = ? in
+  defm vvi : RVmm<opcStr, ", ($vy, ${vz}), $sy", opc, RC, RCM,
+                 (ins RC:$vy, RC:$vz, uimm7:$sy)>;
+}
+// Special RV multiclass with 3 arguments.
+//   e.g. VSFA
+let VE_VLIndex = 4 in
+multiclass RVSAm<string opcStr, bits<8>opc, RegisterClass RC,
+                 RegisterClass RCM> {
+  let cz = 1, sz = ?, vz = ? in
+  defm vrr : RVmm<opcStr, ", $vz, $sy, $sz", opc, RC, RCM,
+                  (ins RC:$vz, I64:$sy, I64:$sz)>;
+  let cz = 0, sz = ?, vz = ? in
+  defm vrm : RVmm<opcStr, ", $vz, $sy, $sz", opc, RC, RCM,
+                  (ins RC:$vz, I64:$sy, mimm:$sz)>;
+  let cy = 0, cz = 1, sz = ?, vz = ? in
+  defm vir : RVmm<opcStr, ", $vz, $sy, $sz", opc, RC, RCM,
+                  (ins RC:$vz, uimm3:$sy, I64:$sz)>;
+  let cy = 0, cz = 0, sz = ?, vz = ? in
+  defm vim : RVmm<opcStr, ", $vz, $sy, $sz", opc, RC, RCM,
+                  (ins RC:$vz, uimm3:$sy, mimm:$sz)>;
+}
 
 // Section 8.10.1 - VADD (Vector Add)
 let cx = 0, cx2 = 0 in
@@ -750,3 +792,60 @@
 let cx = 0, cx2 = 1 in defm PVSEQLO : RV0m<"pvseq.lo", 0x99, V64, VM>;
 let cx = 1, cx2 = 0 in defm PVSEQUP : RV0m<"pvseq.up", 0x99, V64, VM>;
 let cx = 1, cx2 = 1 in defm PVSEQ : RV0m<"pvseq", 0x99, V64, VM512>;
+
+//-----------------------------------------------------------------------------
+// Section 8.12 - Vector Shift Operation Instructions
+//-----------------------------------------------------------------------------
+
+// Section 8.12.1 - VSLL (Vector Shift Left Logical)
+let cx = 0, cx2 = 0 in defm VSLL : RVSm<"vsll", 0xe5, I64, V64, VM>;
+let cx = 0, cx2 = 1 in defm PVSLLLO : RVSm<"pvsll.lo", 0xe5, I32, V64, VM>;
+let cx = 1, cx2 = 0 in defm PVSLLUP : RVSm<"pvsll.up", 0xe5, F32, V64, VM>;
+let cx = 1, cx2 = 1 in defm PVSLL : RVSm<"pvsll", 0xe5, I64, V64, VM512>;
+
+// Section 8.12.2 - VSLD (Vector Shift Left Double)
+defm VSLD : RVSDm<"vsld", 0xe4, V64, VM>;
+
+// Section 8.12.3 - VSRL (Vector Shift Right Logical)
+let cx = 0, cx2 = 0 in defm VSRL : RVSm<"vsrl", 0xf5, I64, V64, VM>;
+let cx = 0, cx2 = 1 in defm PVSRLLO : RVSm<"pvsrl.lo", 0xf5, I32, V64, VM>;
+let cx = 1, cx2 = 0 in defm PVSRLUP : RVSm<"pvsrl.up", 0xf5, F32, V64, VM>;
+let cx = 1, cx2 = 1 in defm PVSRL : RVSm<"pvsrl", 0xf5, I64, V64, VM512>;
+
+// Section 8.12.4 - VSRD (Vector Shift Right Double)
+defm VSRD : RVSDm<"vsrd", 0xf4, V64, VM>;
+
+// Section 8.12.5 - VSLA (Vector Shift Left Arithmetic)
+let cx = 0, cx2 = 0 in defm VSLAWSX : RVSm<"vsla.w.sx", 0xe6, I32, V64, VM>;
+let cx = 0, cx2 = 1 in {
+  defm PVSLALO : RVSm<"pvsla.lo", 0xe6, I32, V64, VM>;
+  let isCodeGenOnly = 1 in defm VSLAWZX : RVSm<"vsla.w.zx", 0xe6, I32, V64, VM>;
+}
+let cx = 1, cx2 = 0 in defm PVSLAUP : RVSm<"pvsla.up", 0xe6, F32, V64, VM>;
+let cx = 1, cx2 = 1 in defm PVSLA : RVSm<"pvsla", 0xe6, I64, V64, VM512>;
+def : MnemonicAlias<"pvsla.lo.sx", "vsla.w.sx">;
+def : MnemonicAlias<"vsla.w.zx", "pvsla.lo">;
+def : MnemonicAlias<"vsla.w", "pvsla.lo">;
+def : MnemonicAlias<"pvsla.lo.zx", "pvsla.lo">;
+
+// Section 8.12.6 - VSLAX (Vector Shift Left Arithmetic)
+defm VSLAL : RVSm<"vsla.l", 0xd4, I64, V64, VM>;
+
+// Section 8.12.7 - VSRA (Vector Shift Right Arithmetic)
+let cx = 0, cx2 = 0 in defm VSRAWSX : RVSm<"vsra.w.sx", 0xf6, I32, V64, VM>;
+let cx = 0, cx2 = 1 in {
+  defm PVSRALO : RVSm<"pvsra.lo", 0xf6, I32, V64, VM>;
+  let isCodeGenOnly = 1 in defm VSRAWZX : RVSm<"vsra.w.zx", 0xf6, I32, V64, VM>;
+}
+let cx = 1, cx2 = 0 in defm PVSRAUP : RVSm<"pvsra.up", 0xf6, F32, V64, VM>;
+let cx = 1, cx2 = 1 in defm PVSRA : RVSm<"pvsra", 0xf6, I64, V64, VM512>;
+def : MnemonicAlias<"pvsra.lo.sx", "vsra.w.sx">;
+def : MnemonicAlias<"vsra.w.zx", "pvsra.lo">;
+def : MnemonicAlias<"vsra.w", "pvsra.lo">;
+def : MnemonicAlias<"pvsra.lo.zx", "pvsra.lo">;
+
+// Section 8.12.8 - VSRAX (Vector Shift Right Arithmetic)
+defm VSRAL : RVSm<"vsra.l", 0xd5, I64, V64, VM>;
+
+// Section 8.12.9 - VSFA (Vector Shift Left and Add)
+defm VSFA : RVSAm<"vsfa", 0xd7, V64, VM>;
diff --git a/llvm/test/MC/VE/VSFA.s b/llvm/test/MC/VE/VSFA.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/VE/VSFA.s
@@ -0,0 +1,24 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: vsfa %v11, %v22, %s20, (22)0
+# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0x0b,0x56,0x94,0x00,0xd7]
+vsfa %v11, %v22, %s20, (22)0
+
+# CHECK-INST: vsfa %vix, %vix, 0, %s21
+# CHECK-ENCODING: encoding: [0x00,0xff,0x00,0xff,0x95,0x00,0x00,0xd7]
+vsfa %vix, %vix, 0, %s21
+
+# CHECK-INST: vsfa %vix, %v22, 7, (22)1
+# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0xff,0x16,0x07,0x00,0xd7]
+vsfa %vix, %v22, 7, (22)1
+
+# CHECK-INST: vsfa %v11, %v22, %s20, %s21, %vm11
+# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0x0b,0x95,0x94,0x0b,0xd7]
+vsfa %v11, %v22, %s20, %s21, %vm11
+
+# CHECK-INST: vsfa %v11, %v23, %s22, (63)0, %vm11
+# CHECK-ENCODING: encoding: [0x00,0x17,0x00,0x0b,0x7f,0x96,0x0b,0xd7]
+vsfa %v11, %v23, %s22, (63)0, %vm11
diff --git a/llvm/test/MC/VE/VSLA.s b/llvm/test/MC/VE/VSLA.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/VE/VSLA.s
@@ -0,0 +1,40 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: vsla.w.sx %v11, %v22, %s20
+# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0x0b,0x00,0x94,0x20,0xe6]
+vsla.w.sx %v11, %v22, %s20
+
+# CHECK-INST: vsla.w.sx %vix, %vix, %vix
+# CHECK-ENCODING: encoding: [0x00,0xff,0xff,0xff,0x00,0x00,0x00,0xe6]
+vsla.w.sx %vix, %vix, %vix
+
+# CHECK-INST: vsla.w.sx %vix, %vix, %vix
+# CHECK-ENCODING: encoding: [0x00,0xff,0xff,0xff,0x00,0x00,0x00,0xe6]
+pvsla.lo.sx %vix, %vix, %vix
+
+# CHECK-INST: pvsla.lo %vix, %v22, 22
+# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0xff,0x00,0x16,0x60,0xe6]
+pvsla.lo %vix, %v22, 22
+
+# CHECK-INST: pvsla.lo %vix, %v22, 22
+# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0xff,0x00,0x16,0x60,0xe6]
+vsla.w.zx %vix, %v22, 22
+
+# CHECK-INST: pvsla.lo %vix, %v22, 22
+# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0xff,0x00,0x16,0x60,0xe6]
+vsla.w %vix, %v22, 22
+
+# CHECK-INST: pvsla.lo %v11, %v22, 127, %vm11
+# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0x0b,0x00,0x7f,0x6b,0xe6]
+pvsla.lo.zx %v11, %v22, 127, %vm11
+
+# CHECK-INST: pvsla.up %v11, %vix, %v22, %vm11
+# CHECK-ENCODING: encoding: [0x00,0xff,0x16,0x0b,0x00,0x00,0x8b,0xe6]
+pvsla.up %v11, %vix, %v22, %vm11
+
+# CHECK-INST: pvsla %v12, %v20, %v22, %vm12
+# CHECK-ENCODING: encoding: [0x00,0x14,0x16,0x0c,0x00,0x00,0xcc,0xe6]
+pvsla %v12, %v20, %v22, %vm12
diff --git a/llvm/test/MC/VE/VSLAX.s b/llvm/test/MC/VE/VSLAX.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/VE/VSLAX.s
@@ -0,0 +1,24 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: vsla.l %v11, %v22, %s20
+# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0x0b,0x00,0x94,0x20,0xd4]
+vsla.l %v11, %v22, %s20
+
+# CHECK-INST: vsla.l %vix, %vix, %vix
+# CHECK-ENCODING: encoding: [0x00,0xff,0xff,0xff,0x00,0x00,0x00,0xd4]
+vsla.l %vix, %vix, %vix
+
+# CHECK-INST: vsla.l %vix, %v22, 22
+# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0xff,0x00,0x16,0x20,0xd4]
+vsla.l %vix, %v22, 22
+
+# CHECK-INST: vsla.l %v11, %v22, 63, %vm11
+# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0x0b,0x00,0x3f,0x2b,0xd4]
+vsla.l %v11, %v22, 63, %vm11
+
+# CHECK-INST: vsla.l %v11, %v23, %v22, %vm11
+# CHECK-ENCODING: encoding: [0x00,0x17,0x16,0x0b,0x00,0x00,0x0b,0xd4]
+vsla.l %v11, %v23, %v22, %vm11
diff --git a/llvm/test/MC/VE/VSLD.s b/llvm/test/MC/VE/VSLD.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/VE/VSLD.s
@@ -0,0 +1,28 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: vsld %v11, (%v22, %v23), %s20
+# CHECK-ENCODING: encoding: [0x00,0x17,0x16,0x0b,0x00,0x94,0x00,0xe4]
+vsld %v11, (%v22, %v23), %s20
+
+# CHECK-INST: vsld %vix, (%vix, %vix), %s23
+# CHECK-ENCODING: encoding: [0x00,0xff,0xff,0xff,0x00,0x97,0x00,0xe4]
+vsld %vix, (%vix, %vix), %s23
+
+# CHECK-INST: vsld %vix, (%v22, %v30), 22
+# CHECK-ENCODING: encoding: [0x00,0x1e,0x16,0xff,0x00,0x16,0x00,0xe4]
+vsld %vix, (%v22, %v30), 22
+
+# CHECK-INST: vsld %v11, (%v22, %vix), 127, %vm11
+# CHECK-ENCODING: encoding: [0x00,0xff,0x16,0x0b,0x00,0x7f,0x0b,0xe4]
+vsld %v11, (%v22, %vix), 127, %vm11
+
+# CHECK-INST: vsld %v11, (%vix, %v22), 21, %vm11
+# CHECK-ENCODING: encoding: [0x00,0x16,0xff,0x0b,0x00,0x15,0x0b,0xe4]
+vsld %v11, (%vix, %v22), 21, %vm11
+
+# CHECK-INST: vsld %v12, (%v20, %v22), 2, %vm12
+# CHECK-ENCODING: encoding: [0x00,0x16,0x14,0x0c,0x00,0x02,0x0c,0xe4]
+vsld %v12, (%v20, %v22), 2, %vm12
diff --git a/llvm/test/MC/VE/VSLL.s b/llvm/test/MC/VE/VSLL.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/VE/VSLL.s
@@ -0,0 +1,28 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: vsll %v11, %v22, %s20
+# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0x0b,0x00,0x94,0x20,0xe5]
+vsll %v11, %v22, %s20
+
+# CHECK-INST: vsll %vix, %vix, %vix
+# CHECK-ENCODING: encoding: [0x00,0xff,0xff,0xff,0x00,0x00,0x00,0xe5]
+vsll %vix, %vix, %vix
+
+# CHECK-INST: pvsll.lo %vix, %v22, 22
+# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0xff,0x00,0x16,0x60,0xe5]
+pvsll.lo %vix, %v22, 22
+
+# CHECK-INST: pvsll.lo %v11, %v22, 127, %vm11
+# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0x0b,0x00,0x7f,0x6b,0xe5]
+pvsll.lo %v11, %v22, 127, %vm11
+
+# CHECK-INST: pvsll.up %v11, %vix, %v22, %vm11
+# CHECK-ENCODING: encoding: [0x00,0xff,0x16,0x0b,0x00,0x00,0x8b,0xe5]
+pvsll.up %v11, %vix, %v22, %vm11
+
+# CHECK-INST: pvsll %v12, %v20, %v22, %vm12
+# CHECK-ENCODING: encoding: [0x00,0x14,0x16,0x0c,0x00,0x00,0xcc,0xe5]
+pvsll %v12, %v20, %v22, %vm12
diff --git a/llvm/test/MC/VE/VSRA.s b/llvm/test/MC/VE/VSRA.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/VE/VSRA.s
@@ -0,0 +1,40 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: vsra.w.sx %v11, %v22, %s20
+# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0x0b,0x00,0x94,0x20,0xf6]
+vsra.w.sx %v11, %v22, %s20
+
+# CHECK-INST: vsra.w.sx %vix, %vix, %vix
+# CHECK-ENCODING: encoding: [0x00,0xff,0xff,0xff,0x00,0x00,0x00,0xf6]
+vsra.w.sx %vix, %vix, %vix
+
+# CHECK-INST: vsra.w.sx %vix, %vix, %vix
+# CHECK-ENCODING: encoding: [0x00,0xff,0xff,0xff,0x00,0x00,0x00,0xf6]
+pvsra.lo.sx %vix, %vix, %vix
+
+# CHECK-INST: pvsra.lo %vix, %v22, 22
+# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0xff,0x00,0x16,0x60,0xf6]
+pvsra.lo %vix, %v22, 22
+
+# CHECK-INST: pvsra.lo %vix, %v22, 22
+# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0xff,0x00,0x16,0x60,0xf6]
+vsra.w.zx %vix, %v22, 22
+
+# CHECK-INST: pvsra.lo %vix, %v22, 22
+# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0xff,0x00,0x16,0x60,0xf6]
+vsra.w %vix, %v22, 22
+
+# CHECK-INST: pvsra.lo %v11, %v22, 127, %vm11
+# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0x0b,0x00,0x7f,0x6b,0xf6]
+pvsra.lo.zx %v11, %v22, 127, %vm11
+
+# CHECK-INST: pvsra.up %v11, %vix, %v22, %vm11
+# CHECK-ENCODING: encoding: [0x00,0xff,0x16,0x0b,0x00,0x00,0x8b,0xf6]
+pvsra.up %v11, %vix, %v22, %vm11
+
+# CHECK-INST: pvsra %v12, %v20, %v22, %vm12
+# CHECK-ENCODING: encoding: [0x00,0x14,0x16,0x0c,0x00,0x00,0xcc,0xf6]
+pvsra %v12, %v20, %v22, %vm12
diff --git a/llvm/test/MC/VE/VSRAX.s b/llvm/test/MC/VE/VSRAX.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/VE/VSRAX.s
@@ -0,0 +1,24 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: vsra.l %v11, %v22, %s20
+# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0x0b,0x00,0x94,0x20,0xd5]
+vsra.l %v11, %v22, %s20
+
+# CHECK-INST: vsra.l %vix, %vix, %vix
+# CHECK-ENCODING: encoding: [0x00,0xff,0xff,0xff,0x00,0x00,0x00,0xd5]
+vsra.l %vix, %vix, %vix
+
+# CHECK-INST: vsra.l %vix, %v22, 22
+# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0xff,0x00,0x16,0x20,0xd5]
+vsra.l %vix, %v22, 22
+
+# CHECK-INST: vsra.l %v11, %v22, 63, %vm11
+# CHECK-ENCODING: encoding: [0x00,0x16,0x00,0x0b,0x00,0x3f,0x2b,0xd5]
+vsra.l %v11, %v22, 63, %vm11
+
+# CHECK-INST: vsra.l %v11, %v23, %v22, %vm11
+# CHECK-ENCODING: encoding: [0x00,0x17,0x16,0x0b,0x00,0x00,0x0b,0xd5]
+vsra.l %v11, %v23, %v22, %vm11