Index: llvm/include/llvm/CodeGen/TargetRegisterInfo.h =================================================================== --- llvm/include/llvm/CodeGen/TargetRegisterInfo.h +++ llvm/include/llvm/CodeGen/TargetRegisterInfo.h @@ -924,6 +924,24 @@ llvm_unreachable("isFrameOffsetLegal does not exist on this target"); } + struct DecomposedOffset { + int64_t FixedOffset; + int64_t ScalableOffset; + Optional ScaleReg; + }; + + /// Decompose a StackOffset into fixed and scalable components, with + /// an optional register used to represent the runtime scaling. + /// ScaleReg must be the DWARF register number that the debugger can use + /// to implement the scaling in an offset expression. For example, + /// for AArch64 this register is the Vector Granule register (VG), + /// which represents the number of 64bit granules in a scalable vector. + virtual DecomposedOffset + decomposeStackOffsetForDwarf(const StackOffset &Offset) const { + assert(!Offset.getScalable() && "Unknown register needed for ScaleReg"); + return {Offset.getFixed(), 0, {}}; + } + /// Spill the register so it can be used by the register scavenger. /// Return true if the register was spilled, false otherwise. /// If this function does not spill the register, the scavenger Index: llvm/include/llvm/IR/DebugInfoMetadata.h =================================================================== --- llvm/include/llvm/IR/DebugInfoMetadata.h +++ llvm/include/llvm/IR/DebugInfoMetadata.h @@ -2660,7 +2660,9 @@ bool isComplex() const; /// Append \p Ops with operations to apply the \p Offset. - static void appendOffset(SmallVectorImpl &Ops, int64_t Offset); + static void appendOffset(SmallVectorImpl &Ops, int64_t Offset, + int64_t ScaledOffset = 0, + const Optional &ScaleReg = {}); /// If this is a constant offset, extract it. If there is no expression, /// return true with an offset of zero. @@ -2684,7 +2686,8 @@ /// Prepend \p DIExpr with a deref and offset operation and optionally turn it /// into a stack value or/and an entry value. static DIExpression *prepend(const DIExpression *Expr, uint8_t Flags, - int64_t Offset = 0); + int64_t Offset = 0, int64_t ScaledOffset = 0, + const Optional &ScaleReg = {}); /// Prepend \p DIExpr with the given opcodes and optionally turn it into a /// stack value. Index: llvm/lib/CodeGen/PrologEpilogInserter.cpp =================================================================== --- llvm/lib/CodeGen/PrologEpilogInserter.cpp +++ llvm/lib/CodeGen/PrologEpilogInserter.cpp @@ -1211,8 +1211,6 @@ StackOffset Offset = TFI->getFrameIndexReference(MF, FrameIdx, Reg); - assert(!Offset.getScalable() && - "Frame offsets with a scalable component are not supported"); MI.getOperand(0).ChangeToRegister(Reg, false /*isDef*/); MI.getOperand(0).setIsDebug(); @@ -1238,7 +1236,10 @@ // Make the DBG_VALUE direct. MI.getDebugOffset().ChangeToRegister(0, false); } - DIExpr = DIExpression::prepend(DIExpr, PrependFlags, Offset.getFixed()); + + auto Decomp = TRI.decomposeStackOffsetForDwarf(Offset); + DIExpr = DIExpression::prepend(DIExpr, PrependFlags, Decomp.FixedOffset, + Decomp.ScalableOffset, Decomp.ScaleReg); MI.getDebugExpressionOp().setMetadata(DIExpr); continue; } Index: llvm/lib/IR/DebugInfoMetadata.cpp =================================================================== --- llvm/lib/IR/DebugInfoMetadata.cpp +++ llvm/lib/IR/DebugInfoMetadata.cpp @@ -1117,8 +1117,9 @@ return None; } -void DIExpression::appendOffset(SmallVectorImpl &Ops, - int64_t Offset) { +void DIExpression::appendOffset(SmallVectorImpl &Ops, int64_t Offset, + int64_t ScaledOffset, + const Optional &ScaleReg) { if (Offset > 0) { Ops.push_back(dwarf::DW_OP_plus_uconst); Ops.push_back(Offset); @@ -1127,6 +1128,23 @@ Ops.push_back(-Offset); Ops.push_back(dwarf::DW_OP_minus); } + + if (ScaledOffset) { + assert(ScaleReg && "Need a register for scale"); + if (ScaledOffset > 0) { + Ops.push_back(dwarf::DW_OP_constu); + Ops.push_back(ScaledOffset); + Ops.append({dwarf::DW_OP_bregx, *ScaleReg, 0ULL}); + Ops.push_back(dwarf::DW_OP_mul); + Ops.push_back(dwarf::DW_OP_plus); + } else if (ScaledOffset < 0) { + Ops.push_back(dwarf::DW_OP_constu); + Ops.push_back(-ScaledOffset); + Ops.append({dwarf::DW_OP_bregx, *ScaleReg, 0ULL}); + Ops.push_back(dwarf::DW_OP_mul); + Ops.push_back(dwarf::DW_OP_minus); + } + } } bool DIExpression::extractIfOffset(int64_t &Offset) const { @@ -1175,12 +1193,14 @@ } DIExpression *DIExpression::prepend(const DIExpression *Expr, uint8_t Flags, - int64_t Offset) { + int64_t Offset, int64_t ScaledOffset, + const Optional &ScaleReg) { SmallVector Ops; if (Flags & DIExpression::DerefBefore) Ops.push_back(dwarf::DW_OP_deref); - appendOffset(Ops, Offset); + appendOffset(Ops, Offset, ScaledOffset, ScaleReg); + if (Flags & DIExpression::DerefAfter) Ops.push_back(dwarf::DW_OP_deref); Index: llvm/lib/Target/AArch64/AArch64FrameLowering.cpp =================================================================== --- llvm/lib/Target/AArch64/AArch64FrameLowering.cpp +++ llvm/lib/Target/AArch64/AArch64FrameLowering.cpp @@ -408,26 +408,25 @@ // { DW_CFA_def_cfa_expression, ULEB128 (sizeof expr), expr } MCCFIInstruction AArch64FrameLowering::createDefCFAExpressionFromSP( const TargetRegisterInfo &TRI, const StackOffset &OffsetFromSP) const { - int64_t NumBytes, NumVGScaledBytes; - AArch64InstrInfo::decomposeStackOffsetForDwarfOffsets(OffsetFromSP, NumBytes, - NumVGScaledBytes); + auto Decomposed = static_cast(TRI) + .decomposeStackOffsetForDwarf(OffsetFromSP); std::string CommentBuffer = "sp"; llvm::raw_string_ostream Comment(CommentBuffer); - // Build up the expression (SP + NumBytes + NumVGScaledBytes * AArch64::VG) + // Build up the expression (SP + FixedOffset + ScalableOffset * AArch64::VG) SmallString<64> Expr; Expr.push_back((uint8_t)(dwarf::DW_OP_breg0 + /*SP*/ 31)); Expr.push_back(0); - appendVGScaledOffsetExpr(Expr, NumBytes, NumVGScaledBytes, - TRI.getDwarfRegNum(AArch64::VG, true), Comment); + appendVGScaledOffsetExpr(Expr, Decomposed.FixedOffset, + Decomposed.ScalableOffset, *Decomposed.ScaleReg, + Comment); // Wrap this into DW_CFA_def_cfa. SmallString<64> DefCfaExpr; DefCfaExpr.push_back(dwarf::DW_CFA_def_cfa_expression); uint8_t buffer[16]; - DefCfaExpr.append(buffer, - buffer + encodeULEB128(Expr.size(), buffer)); + DefCfaExpr.append(buffer, buffer + encodeULEB128(Expr.size(), buffer)); DefCfaExpr.append(Expr.str()); return MCCFIInstruction::createEscape(nullptr, DefCfaExpr.str(), Comment.str()); @@ -436,24 +435,25 @@ MCCFIInstruction AArch64FrameLowering::createCfaOffset( const TargetRegisterInfo &TRI, unsigned Reg, const StackOffset &OffsetFromDefCFA) const { - int64_t NumBytes, NumVGScaledBytes; - AArch64InstrInfo::decomposeStackOffsetForDwarfOffsets( - OffsetFromDefCFA, NumBytes, NumVGScaledBytes); + auto Decomposed = static_cast(TRI) + .decomposeStackOffsetForDwarf(OffsetFromDefCFA); unsigned DwarfReg = TRI.getDwarfRegNum(Reg, true); // Non-scalable offsets can use DW_CFA_offset directly. - if (!NumVGScaledBytes) - return MCCFIInstruction::createOffset(nullptr, DwarfReg, NumBytes); + if (!Decomposed.ScalableOffset) + return MCCFIInstruction::createOffset(nullptr, DwarfReg, + Decomposed.FixedOffset); std::string CommentBuffer; llvm::raw_string_ostream Comment(CommentBuffer); Comment << printReg(Reg, &TRI) << " @ cfa"; - // Build up expression (NumBytes + NumVGScaledBytes * AArch64::VG) + // Build up expression (FixedOffset + ScalableOffset * AArch64::VG) SmallString<64> OffsetExpr; - appendVGScaledOffsetExpr(OffsetExpr, NumBytes, NumVGScaledBytes, - TRI.getDwarfRegNum(AArch64::VG, true), Comment); + appendVGScaledOffsetExpr(OffsetExpr, Decomposed.FixedOffset, + Decomposed.ScalableOffset, *Decomposed.ScaleReg, + Comment); // Wrap this into DW_CFA_expression SmallString<64> CfaExpr; Index: llvm/lib/Target/AArch64/AArch64InstrInfo.h =================================================================== --- llvm/lib/Target/AArch64/AArch64InstrInfo.h +++ llvm/lib/Target/AArch64/AArch64InstrInfo.h @@ -296,9 +296,6 @@ int64_t &NumBytes, int64_t &NumPredicateVectors, int64_t &NumDataVectors); - static void decomposeStackOffsetForDwarfOffsets(const StackOffset &Offset, - int64_t &ByteSized, - int64_t &VGSized); #define GET_INSTRINFO_HELPER_DECLS #include "AArch64GenInstrInfo.inc" Index: llvm/lib/Target/AArch64/AArch64InstrInfo.cpp =================================================================== --- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -3429,22 +3429,6 @@ }); } -void AArch64InstrInfo::decomposeStackOffsetForDwarfOffsets( - const StackOffset &Offset, int64_t &ByteSized, int64_t &VGSized) { - // The smallest scalable element supported by scaled SVE addressing - // modes are predicates, which are 2 scalable bytes in size. So the scalable - // byte offset must always be a multiple of 2. - assert(Offset.getScalable() % 2 == 0 && "Invalid frame offset"); - - // VGSized offsets are divided by '2', because the VG register is the - // the number of 64bit granules as opposed to 128bit vector chunks, - // which is how the 'n' in e.g. MVT::nxv1i8 is modelled. - // So, for a stack offset of 16 MVT::nxv1i8's, the size is n x 16 bytes. - // VG = n * 2 and the dwarf offset must be VG * 8 bytes. - ByteSized = Offset.getFixed(); - VGSized = Offset.getScalable() / 2; -} - /// Returns the offset in parts to which this frame offset can be /// decomposed for the purpose of describing a frame offset. /// For non-scalable offsets this is simply its byte size. Index: llvm/lib/Target/AArch64/AArch64RegisterInfo.h =================================================================== --- llvm/lib/Target/AArch64/AArch64RegisterInfo.h +++ llvm/lib/Target/AArch64/AArch64RegisterInfo.h @@ -135,6 +135,9 @@ unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg, const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override; + + TargetRegisterInfo::DecomposedOffset + decomposeStackOffsetForDwarf(const StackOffset &Offset) const override; }; } // end namespace llvm Index: llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp =================================================================== --- llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp +++ llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp @@ -592,6 +592,25 @@ } } +TargetRegisterInfo::DecomposedOffset +AArch64RegisterInfo::decomposeStackOffsetForDwarf( + const StackOffset &Offset) const { + // The smallest scalable element supported by scaled SVE addressing + // modes are predicates, which are 2 scalable bytes in size. So the scalable + // byte offset must always be a multiple of 2. + assert(Offset.getScalable() % 2 == 0 && "Invalid frame offset"); + + // VGSized offsets are divided by '2', because the VG register is the + // the number of 64bit granules as opposed to 128bit vector chunks, + // which is how the 'n' in e.g. MVT::nxv1i8 is modelled. + // So, for a stack offset of 16 MVT::nxv1i8's, the size is n x 16 bytes. + // VG = n * 2 and the dwarf offset must be VG * 8 bytes. + int64_t ByteSized = Offset.getFixed(); + int64_t VGSized = Offset.getScalable() / 2; + unsigned ScaleReg = getDwarfRegNum(AArch64::VG, true); + return {ByteSized, VGSized, {ScaleReg}}; +} + void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const { @@ -611,7 +630,7 @@ Register FrameReg; // Special handling of dbg_value, stackmap patchpoint statepoint instructions. - if (MI.isDebugValue() || MI.getOpcode() == TargetOpcode::STACKMAP || + if (MI.getOpcode() == TargetOpcode::STACKMAP || MI.getOpcode() == TargetOpcode::PATCHPOINT || MI.getOpcode() == TargetOpcode::STATEPOINT) { StackOffset Offset = Index: llvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir @@ -0,0 +1,127 @@ +# RUN: llc -o %t -filetype=obj -start-before=prologepilog %s +# RUN: llvm-dwarfdump --name="value0" %t | FileCheck %s --check-prefix=CHECK0 +# RUN: llvm-dwarfdump --name="value1" %t | FileCheck %s --check-prefix=CHECK1 +# RUN: llvm-dwarfdump --name="value2" %t | FileCheck %s --check-prefix=CHECK2 +# RUN: llvm-dwarfdump --name="value3" %t | FileCheck %s --check-prefix=CHECK3 +# RUN: llvm-dwarfdump --name="value4" %t | FileCheck %s --check-prefix=CHECK4 +# RUN: llvm-dwarfdump --name="value5" %t | FileCheck %s --check-prefix=CHECK5 + +# CHECK0: : DW_OP_breg31 WSP+8) +# CHECK0: DW_AT_type {{.*}}ty32 +# +# CHECK1: : DW_OP_breg31 WSP+0) +# CHECK1: DW_AT_type {{.*}}ty32 +# +# CHECK2: : DW_OP_breg31 WSP+16, DW_OP_lit16, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) +# CHECK2: DW_AT_type {{.*}}svint32_t +# +# CHECK3: : DW_OP_breg31 WSP+16, DW_OP_lit8, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) +# CHECK3: DW_AT_type {{.*}}svint32_t +# +# CHECK4: : DW_OP_breg31 WSP+16, DW_OP_lit7, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) +# CHECK4: DW_AT_type {{.*}}svbool_t +# +# CHECK5: : DW_OP_breg31 WSP+16, DW_OP_lit6, DW_OP_bregx VG+0, DW_OP_mul, DW_OP_plus) +# CHECK5: DW_AT_type {{.*}}svbool_t + +--- | + ; ModuleID = 'bla.mir' + source_filename = "bla.mir" + target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" + + define void @foo() #0 !dbg !5 { + entry: + unreachable, !dbg !8 + } + + ; Function Attrs: nounwind readnone speculatable willreturn + declare void @llvm.dbg.value(metadata, metadata, metadata) #1 + + attributes #0 = { "target-features"="+sve" } + attributes #1 = { nounwind readnone speculatable willreturn } + + !llvm.dbg.cu = !{!0} + !llvm.debugify = !{!3, !3} + !llvm.module.flags = !{!4} + + !0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1, producer: "debugify", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) + !1 = !DIFile(filename: "bla.mir", directory: "/") + !2 = !{} + !3 = !{i32 1} + !4 = !{i32 2, !"Debug Info Version", i32 3} + !5 = distinct !DISubprogram(name: "foo", linkageName: "foo", scope: null, file: !1, line: 1, type: !6, scopeLine: 1, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !9) + !6 = !DISubroutineType(types: !2) + !7 = !DIBasicType(name: "ty32", size: 32, encoding: DW_ATE_signed) + !8 = !DILocation(line: 1, column: 1, scope: !5) + !9 = !{!10, !11, !12, !13, !14, !15} + !10 = !DILocalVariable(name: "value0", scope: !5, file: !1, line: 1, type: !7) + !11 = !DILocalVariable(name: "value1", scope: !5, file: !1, line: 1, type: !7) + !12 = !DILocalVariable(name: "value2", scope: !5, file: !1, line: 1, type: !16) + !13 = !DILocalVariable(name: "value3", scope: !5, file: !1, line: 1, type: !16) + !14 = !DILocalVariable(name: "value4", scope: !5, file: !1, line: 1, type: !21) + !15 = !DILocalVariable(name: "value5", scope: !5, file: !1, line: 1, type: !21) + !16 = !DIDerivedType(tag: DW_TAG_typedef, name: "svint32_t", file: !1, line: 1, baseType: !17) + !17 = !DIDerivedType(tag: DW_TAG_typedef, name: "__SVInt32_t", file: !1, baseType: !18) + !18 = !DICompositeType(tag: DW_TAG_array_type, baseType: !7, flags: DIFlagVector, elements: !19) + !19 = !{!20} + !20 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 2, DW_OP_bregx, 46, 0, DW_OP_mul, DW_OP_constu, 1, DW_OP_minus)) + !21 = !DIDerivedType(tag: DW_TAG_typedef, name: "svbool_t", file: !1, line: 90, baseType: !22) + !22 = !DIDerivedType(tag: DW_TAG_typedef, name: "__SVBool_t", file: !1, baseType: !23) + !23 = !DICompositeType(tag: DW_TAG_array_type, baseType: !24, flags: DIFlagVector, elements: !25) + !24 = !DIBasicType(name: "unsigned char", size: 8, encoding: DW_ATE_unsigned_char) + !25 = !{!26} + !26 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_constu, 1, DW_OP_bregx, 46, 0, DW_OP_mul, DW_OP_constu, 1, DW_OP_minus)) + + +... +--- +name: foo +alignment: 4 +tracksRegLiveness: true +liveins: + - { reg: '$z0' } + - { reg: '$z1' } + - { reg: '$p0' } + - { reg: '$p1' } + - { reg: '$x0' } + - { reg: '$x1' } +frameInfo: + maxAlignment: 16 + adjustsStack: true + hasCalls: true + maxCallFrameSize: 0 + localFrameSize: 4 +stack: + - { id: 0, size: 8, alignment: 8 } + - { id: 1, size: 8, alignment: 8 } + - { id: 2, size: 16, alignment: 16, stack-id: sve-vec } + - { id: 3, size: 16, alignment: 16, stack-id: sve-vec } + - { id: 4, size: 2, alignment: 2, stack-id: sve-vec } + - { id: 5, size: 2, alignment: 2, stack-id: sve-vec } +machineFunctionInfo: {} +body: | + bb.0.entry: + liveins: $p0, $p1, $w0, $x1, $z0, $z1 + + ; Avoid stack slot scavenging. + $lr = IMPLICIT_DEF + + STRXui killed renamable $x0, %stack.0, 0, debug-location !8 + DBG_VALUE %stack.0, $noreg, !10, !DIExpression(DW_OP_deref), debug-location !8 + STRXui killed renamable $x1, %stack.1, 0, debug-location !8 + DBG_VALUE %stack.1, $noreg, !11, !DIExpression(DW_OP_deref), debug-location !8 + + renamable $p2 = PTRUE_S 31, debug-location !DILocation(line: 4, column: 1, scope: !5) + ST1W_IMM renamable $z0, renamable $p2, %stack.2, 0, debug-location !DILocation(line: 5, column: 1, scope: !5) + DBG_VALUE %stack.2, $noreg, !12, !DIExpression(DW_OP_deref), debug-location !DILocation(line: 5, column: 1, scope: !5) + ST1W_IMM renamable $z1, killed renamable $p2, %stack.3, 0, debug-location !DILocation(line: 6, column: 1, scope: !5) + DBG_VALUE %stack.3, $noreg, !13, !DIExpression(DW_OP_deref), debug-location !DILocation(line: 6, column: 1, scope: !5) + + STR_PXI killed renamable $p0, %stack.4, 0, debug-location !DILocation(line: 2, column: 1, scope: !5) + DBG_VALUE %stack.4, $noreg, !14, !DIExpression(DW_OP_deref), debug-location !DILocation(line: 2, column: 1, scope: !5) + STR_PXI killed renamable $p1, %stack.5, 0, debug-location !DILocation(line: 3, column: 1, scope: !5) + DBG_VALUE %stack.5, $noreg, !15, !DIExpression(DW_OP_deref), debug-location !DILocation(line: 3, column: 1, scope: !5) + + RET_ReallyLR implicit $z0, implicit $z1, debug-location !DILocation(line: 7, column: 1, scope: !5) + +...