diff --git a/llvm/include/llvm/CodeGen/ReachingDefAnalysis.h b/llvm/include/llvm/CodeGen/ReachingDefAnalysis.h --- a/llvm/include/llvm/CodeGen/ReachingDefAnalysis.h +++ b/llvm/include/llvm/CodeGen/ReachingDefAnalysis.h @@ -139,23 +139,25 @@ /// Provides the instruction id of the closest reaching def instruction of /// PhysReg that reaches MI, relative to the begining of MI's basic block. - int getReachingDef(MachineInstr *MI, int PhysReg) const; + int getReachingDef(MachineInstr *MI, MCRegister PhysReg) const; /// Return whether A and B use the same def of PhysReg. - bool hasSameReachingDef(MachineInstr *A, MachineInstr *B, int PhysReg) const; + bool hasSameReachingDef(MachineInstr *A, MachineInstr *B, + MCRegister PhysReg) const; /// Return whether the reaching def for MI also is live out of its parent /// block. - bool isReachingDefLiveOut(MachineInstr *MI, int PhysReg) const; + bool isReachingDefLiveOut(MachineInstr *MI, MCRegister PhysReg) const; /// Return the local MI that produces the live out value for PhysReg, or /// nullptr for a non-live out or non-local def. MachineInstr *getLocalLiveOutMIDef(MachineBasicBlock *MBB, - int PhysReg) const; + MCRegister PhysReg) const; /// If a single MachineInstr creates the reaching definition, then return it. /// Otherwise return null. - MachineInstr *getUniqueReachingMIDef(MachineInstr *MI, int PhysReg) const; + MachineInstr *getUniqueReachingMIDef(MachineInstr *MI, + MCRegister PhysReg) const; /// If a single MachineInstr creates the reaching definition, for MIs operand /// at Idx, then return it. Otherwise return null. @@ -167,44 +169,44 @@ /// Provide whether the register has been defined in the same basic block as, /// and before, MI. - bool hasLocalDefBefore(MachineInstr *MI, int PhysReg) const; + bool hasLocalDefBefore(MachineInstr *MI, MCRegister PhysReg) const; /// Return whether the given register is used after MI, whether it's a local /// use or a live out. - bool isRegUsedAfter(MachineInstr *MI, int PhysReg) const; + bool isRegUsedAfter(MachineInstr *MI, MCRegister PhysReg) const; /// Return whether the given register is defined after MI. - bool isRegDefinedAfter(MachineInstr *MI, int PhysReg) const; + bool isRegDefinedAfter(MachineInstr *MI, MCRegister PhysReg) const; /// Provides the clearance - the number of instructions since the closest /// reaching def instuction of PhysReg that reaches MI. - int getClearance(MachineInstr *MI, MCPhysReg PhysReg) const; + int getClearance(MachineInstr *MI, MCRegister PhysReg) const; /// Provides the uses, in the same block as MI, of register that MI defines. /// This does not consider live-outs. - void getReachingLocalUses(MachineInstr *MI, int PhysReg, + void getReachingLocalUses(MachineInstr *MI, MCRegister PhysReg, InstSet &Uses) const; /// Search MBB for a definition of PhysReg and insert it into Defs. If no /// definition is found, recursively search the predecessor blocks for them. - void getLiveOuts(MachineBasicBlock *MBB, int PhysReg, InstSet &Defs, + void getLiveOuts(MachineBasicBlock *MBB, MCRegister PhysReg, InstSet &Defs, BlockSet &VisitedBBs) const; - void getLiveOuts(MachineBasicBlock *MBB, int PhysReg, InstSet &Defs) const; + void getLiveOuts(MachineBasicBlock *MBB, MCRegister PhysReg, + InstSet &Defs) const; /// For the given block, collect the instructions that use the live-in /// value of the provided register. Return whether the value is still /// live on exit. - bool getLiveInUses(MachineBasicBlock *MBB, int PhysReg, + bool getLiveInUses(MachineBasicBlock *MBB, MCRegister PhysReg, InstSet &Uses) const; /// Collect the users of the value stored in PhysReg, which is defined /// by MI. - void getGlobalUses(MachineInstr *MI, int PhysReg, - InstSet &Uses) const; + void getGlobalUses(MachineInstr *MI, MCRegister PhysReg, InstSet &Uses) const; /// Collect all possible definitions of the value stored in PhysReg, which is /// used by MI. - void getGlobalReachingDefs(MachineInstr *MI, int PhysReg, + void getGlobalReachingDefs(MachineInstr *MI, MCRegister PhysReg, InstSet &Defs) const; /// Return whether From can be moved forwards to just before To. @@ -229,12 +231,13 @@ /// Return whether a MachineInstr could be inserted at MI and safely define /// the given register without affecting the program. - bool isSafeToDefRegAt(MachineInstr *MI, int PhysReg) const; + bool isSafeToDefRegAt(MachineInstr *MI, MCRegister PhysReg) const; /// Return whether a MachineInstr could be inserted at MI and safely define /// the given register without affecting the program, ignoring any effects /// on the provided instructions. - bool isSafeToDefRegAt(MachineInstr *MI, int PhysReg, InstSet &Ignore) const; + bool isSafeToDefRegAt(MachineInstr *MI, MCRegister PhysReg, + InstSet &Ignore) const; private: /// Set up LiveRegs by merging predecessor live-out values. @@ -269,7 +272,8 @@ /// Provides the instruction of the closest reaching def instruction of /// PhysReg that reaches MI, relative to the begining of MI's basic block. - MachineInstr *getReachingLocalMIDef(MachineInstr *MI, int PhysReg) const; + MachineInstr *getReachingLocalMIDef(MachineInstr *MI, + MCRegister PhysReg) const; }; } // namespace llvm diff --git a/llvm/lib/CodeGen/BreakFalseDeps.cpp b/llvm/lib/CodeGen/BreakFalseDeps.cpp --- a/llvm/lib/CodeGen/BreakFalseDeps.cpp +++ b/llvm/lib/CodeGen/BreakFalseDeps.cpp @@ -171,8 +171,8 @@ bool BreakFalseDeps::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx, unsigned Pref) { - Register reg = MI->getOperand(OpIdx).getReg(); - unsigned Clearance = RDA->getClearance(MI, reg); + MCRegister Reg = MI->getOperand(OpIdx).getReg().asMCReg(); + unsigned Clearance = RDA->getClearance(MI, Reg); LLVM_DEBUG(dbgs() << "Clearance: " << Clearance << ", want " << Pref); if (Pref > Clearance) { diff --git a/llvm/lib/CodeGen/RDFRegisters.cpp b/llvm/lib/CodeGen/RDFRegisters.cpp --- a/llvm/lib/CodeGen/RDFRegisters.cpp +++ b/llvm/lib/CodeGen/RDFRegisters.cpp @@ -84,10 +84,10 @@ for (uint32_t M = 1, NM = RegMasks.size(); M <= NM; ++M) { BitVector PU(TRI.getNumRegUnits()); const uint32_t *MB = RegMasks.get(M); - for (unsigned i = 1, e = TRI.getNumRegs(); i != e; ++i) { - if (!(MB[i/32] & (1u << (i%32)))) + for (unsigned I = 1, E = TRI.getNumRegs(); I != E; ++I) { + if (!(MB[I / 32] & (1u << (I % 32)))) continue; - for (MCRegUnitIterator U(i, &TRI); U.isValid(); ++U) + for (MCRegUnitIterator U(MCRegister::from(I), &TRI); U.isValid(); ++U) PU.set(*U); } MaskInfos[M].Units = PU.flip(); diff --git a/llvm/lib/CodeGen/ReachingDefAnalysis.cpp b/llvm/lib/CodeGen/ReachingDefAnalysis.cpp --- a/llvm/lib/CodeGen/ReachingDefAnalysis.cpp +++ b/llvm/lib/CodeGen/ReachingDefAnalysis.cpp @@ -29,7 +29,7 @@ return isValidReg(MO) && MO.isUse(); } -static bool isValidRegUseOf(const MachineOperand &MO, int PhysReg) { +static bool isValidRegUseOf(const MachineOperand &MO, MCRegister PhysReg) { return isValidRegUse(MO) && MO.getReg() == PhysReg; } @@ -37,7 +37,7 @@ return isValidReg(MO) && MO.isDef(); } -static bool isValidRegDefOf(const MachineOperand &MO, int PhysReg) { +static bool isValidRegDefOf(const MachineOperand &MO, MCRegister PhysReg) { return isValidRegDef(MO) && MO.getReg() == PhysReg; } @@ -121,7 +121,8 @@ for (auto &MO : MI->operands()) { if (!isValidRegDef(MO)) continue; - for (MCRegUnitIterator Unit(MO.getReg(), TRI); Unit.isValid(); ++Unit) { + for (MCRegUnitIterator Unit(MO.getReg().asMCReg(), TRI); Unit.isValid(); + ++Unit) { // This instruction explicitly defines the current reg unit. LLVM_DEBUG(dbgs() << printReg(*Unit, TRI) << ":\t" << CurInstr << '\t' << *MI); @@ -252,7 +253,8 @@ #endif } -int ReachingDefAnalysis::getReachingDef(MachineInstr *MI, int PhysReg) const { +int ReachingDefAnalysis::getReachingDef(MachineInstr *MI, + MCRegister PhysReg) const { assert(InstIds.count(MI) && "Unexpected machine instuction."); int InstId = InstIds.lookup(MI); int DefRes = ReachingDefDefaultVal; @@ -271,15 +273,16 @@ return LatestDef; } -MachineInstr* ReachingDefAnalysis::getReachingLocalMIDef(MachineInstr *MI, - int PhysReg) const { +MachineInstr * +ReachingDefAnalysis::getReachingLocalMIDef(MachineInstr *MI, + MCRegister PhysReg) const { return hasLocalDefBefore(MI, PhysReg) ? getInstFromId(MI->getParent(), getReachingDef(MI, PhysReg)) : nullptr; } bool ReachingDefAnalysis::hasSameReachingDef(MachineInstr *A, MachineInstr *B, - int PhysReg) const { + MCRegister PhysReg) const { MachineBasicBlock *ParentA = A->getParent(); MachineBasicBlock *ParentB = B->getParent(); if (ParentA != ParentB) @@ -307,18 +310,19 @@ return nullptr; } -int -ReachingDefAnalysis::getClearance(MachineInstr *MI, MCPhysReg PhysReg) const { +int ReachingDefAnalysis::getClearance(MachineInstr *MI, + MCRegister PhysReg) const { assert(InstIds.count(MI) && "Unexpected machine instuction."); return InstIds.lookup(MI) - getReachingDef(MI, PhysReg); } -bool -ReachingDefAnalysis::hasLocalDefBefore(MachineInstr *MI, int PhysReg) const { +bool ReachingDefAnalysis::hasLocalDefBefore(MachineInstr *MI, + MCRegister PhysReg) const { return getReachingDef(MI, PhysReg) >= 0; } -void ReachingDefAnalysis::getReachingLocalUses(MachineInstr *Def, int PhysReg, +void ReachingDefAnalysis::getReachingLocalUses(MachineInstr *Def, + MCRegister PhysReg, InstSet &Uses) const { MachineBasicBlock *MBB = Def->getParent(); MachineBasicBlock::iterator MI = MachineBasicBlock::iterator(Def); @@ -342,9 +346,9 @@ } } -bool -ReachingDefAnalysis::getLiveInUses(MachineBasicBlock *MBB, int PhysReg, - InstSet &Uses) const { +bool ReachingDefAnalysis::getLiveInUses(MachineBasicBlock *MBB, + MCRegister PhysReg, + InstSet &Uses) const { for (MachineInstr &MI : instructionsWithoutDebug(MBB->instr_begin(), MBB->instr_end())) { for (auto &MO : MI.operands()) { @@ -361,9 +365,8 @@ return isReachingDefLiveOut(&*Last, PhysReg); } -void -ReachingDefAnalysis::getGlobalUses(MachineInstr *MI, int PhysReg, - InstSet &Uses) const { +void ReachingDefAnalysis::getGlobalUses(MachineInstr *MI, MCRegister PhysReg, + InstSet &Uses) const { MachineBasicBlock *MBB = MI->getParent(); // Collect the uses that each def touches within the block. @@ -391,9 +394,9 @@ } } -void -ReachingDefAnalysis::getGlobalReachingDefs(MachineInstr *MI, int PhysReg, - InstSet &Defs) const { +void ReachingDefAnalysis::getGlobalReachingDefs(MachineInstr *MI, + MCRegister PhysReg, + InstSet &Defs) const { if (auto *Def = getUniqueReachingMIDef(MI, PhysReg)) { Defs.insert(Def); return; @@ -403,15 +406,15 @@ getLiveOuts(MBB, PhysReg, Defs); } -void ReachingDefAnalysis::getLiveOuts(MachineBasicBlock *MBB, int PhysReg, - InstSet &Defs) const { +void ReachingDefAnalysis::getLiveOuts(MachineBasicBlock *MBB, + MCRegister PhysReg, InstSet &Defs) const { SmallPtrSet VisitedBBs; getLiveOuts(MBB, PhysReg, Defs, VisitedBBs); } -void -ReachingDefAnalysis::getLiveOuts(MachineBasicBlock *MBB, int PhysReg, - InstSet &Defs, BlockSet &VisitedBBs) const { +void ReachingDefAnalysis::getLiveOuts(MachineBasicBlock *MBB, + MCRegister PhysReg, InstSet &Defs, + BlockSet &VisitedBBs) const { if (VisitedBBs.count(MBB)) return; @@ -428,8 +431,9 @@ getLiveOuts(Pred, PhysReg, Defs, VisitedBBs); } -MachineInstr *ReachingDefAnalysis::getUniqueReachingMIDef(MachineInstr *MI, - int PhysReg) const { +MachineInstr * +ReachingDefAnalysis::getUniqueReachingMIDef(MachineInstr *MI, + MCRegister PhysReg) const { // If there's a local def before MI, return it. MachineInstr *LocalDef = getReachingLocalMIDef(MI, PhysReg); if (LocalDef && InstIds.lookup(LocalDef) < InstIds.lookup(MI)) @@ -460,7 +464,8 @@ return getUniqueReachingMIDef(MI, MO.getReg()); } -bool ReachingDefAnalysis::isRegUsedAfter(MachineInstr *MI, int PhysReg) const { +bool ReachingDefAnalysis::isRegUsedAfter(MachineInstr *MI, + MCRegister PhysReg) const { MachineBasicBlock *MBB = MI->getParent(); LivePhysRegs LiveRegs(*TRI); LiveRegs.addLiveOuts(*MBB); @@ -481,7 +486,7 @@ } bool ReachingDefAnalysis::isRegDefinedAfter(MachineInstr *MI, - int PhysReg) const { + MCRegister PhysReg) const { MachineBasicBlock *MBB = MI->getParent(); auto Last = MBB->getLastNonDebugInstr(); if (Last != MBB->end() && @@ -494,8 +499,8 @@ return false; } -bool -ReachingDefAnalysis::isReachingDefLiveOut(MachineInstr *MI, int PhysReg) const { +bool ReachingDefAnalysis::isReachingDefLiveOut(MachineInstr *MI, + MCRegister PhysReg) const { MachineBasicBlock *MBB = MI->getParent(); LivePhysRegs LiveRegs(*TRI); LiveRegs.addLiveOuts(*MBB); @@ -515,8 +520,9 @@ return true; } -MachineInstr* ReachingDefAnalysis::getLocalLiveOutMIDef(MachineBasicBlock *MBB, - int PhysReg) const { +MachineInstr * +ReachingDefAnalysis::getLocalLiveOutMIDef(MachineBasicBlock *MBB, + MCRegister PhysReg) const { LivePhysRegs LiveRegs(*TRI); LiveRegs.addLiveOuts(*MBB); if (!LiveRegs.contains(PhysReg)) @@ -640,7 +646,7 @@ void ReachingDefAnalysis::collectKilledOperands(MachineInstr *MI, InstSet &Dead) const { Dead.insert(MI); - auto IsDead = [this, &Dead](MachineInstr *Def, int PhysReg) { + auto IsDead = [this, &Dead](MachineInstr *Def, MCRegister PhysReg) { if (mayHaveSideEffects(*Def)) return false; @@ -673,12 +679,12 @@ } bool ReachingDefAnalysis::isSafeToDefRegAt(MachineInstr *MI, - int PhysReg) const { + MCRegister PhysReg) const { SmallPtrSet Ignore; return isSafeToDefRegAt(MI, PhysReg, Ignore); } -bool ReachingDefAnalysis::isSafeToDefRegAt(MachineInstr *MI, int PhysReg, +bool ReachingDefAnalysis::isSafeToDefRegAt(MachineInstr *MI, MCRegister PhysReg, InstSet &Ignore) const { // Check for any uses of the register after MI. if (isRegUsedAfter(MI, PhysReg)) { diff --git a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp --- a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp +++ b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp @@ -537,7 +537,8 @@ for (auto &IT : *MBB) { if (IT.getOpcode() != ARM::t2IT) continue; - RDA.getReachingLocalUses(&IT, ARM::ITSTATE, ITBlocks[&IT]); + RDA.getReachingLocalUses(&IT, MCRegister::from(ARM::ITSTATE), + ITBlocks[&IT]); } } @@ -620,7 +621,7 @@ if (StartInsertPt == Start && Start->getOperand(0).getReg() == ARM::LR) { if (auto *IterCount = RDA.getMIOperand(Start, 0)) { SmallPtrSet Uses; - RDA.getGlobalUses(IterCount, ARM::LR, Uses); + RDA.getGlobalUses(IterCount, MCRegister::from(ARM::LR), Uses); for (auto *Use : Uses) { if (Use != Start && Use != Dec) { LLVM_DEBUG(dbgs() << " ARM Loops: Found LR use: " << *Use); @@ -636,7 +637,7 @@ // we can use this register at InsertPt. MachineInstr *VCTP = VCTPs.back(); TPNumElements = VCTP->getOperand(1); - Register NumElements = TPNumElements.getReg(); + MCRegister NumElements = TPNumElements.getReg().asMCReg(); // If the register is defined within loop, then we can't perform TP. // TODO: Check whether this is just a mov of a register that would be @@ -669,8 +670,9 @@ // insertion point MachineOperand Operand = ElemDef->getOperand(1); if (isMovRegOpcode(ElemDef->getOpcode()) && - RDA.getUniqueReachingMIDef(ElemDef, Operand.getReg()) == - RDA.getUniqueReachingMIDef(&*StartInsertPt, Operand.getReg())) { + RDA.getUniqueReachingMIDef(ElemDef, Operand.getReg().asMCReg()) == + RDA.getUniqueReachingMIDef(&*StartInsertPt, + Operand.getReg().asMCReg())) { TPNumElements = Operand; NumElements = TPNumElements.getReg(); } else { @@ -711,7 +713,7 @@ // preheader, so we need to check that the register isn't redefined // before entering the loop. auto CannotProvideElements = [this](MachineBasicBlock *MBB, - Register NumElements) { + MCRegister NumElements) { if (MBB->empty()) return false; // NumElements is redefined in this block. @@ -748,8 +750,8 @@ // tail predicated loop. Explicitly refer to the vctp operand no matter which // register NumElements has been assigned to, since that is what the // modifications will be using - if (auto *Def = RDA.getUniqueReachingMIDef(&MBB->back(), - VCTP->getOperand(1).getReg())) { + if (auto *Def = RDA.getUniqueReachingMIDef( + &MBB->back(), VCTP->getOperand(1).getReg().asMCReg())) { SmallPtrSet ElementChain; SmallPtrSet Ignore; unsigned ExpectedVectorWidth = getTailPredVectorWidth(VCTP->getOpcode()); @@ -942,7 +944,7 @@ auto HasPredicatedUsers = [this](MachineInstr *MI, const MachineOperand &MO, SmallPtrSetImpl &Predicated) { SmallPtrSet Uses; - RDA.getGlobalUses(MI, MO.getReg(), Uses); + RDA.getGlobalUses(MI, MO.getReg().asMCReg(), Uses); for (auto *Use : Uses) { if (Use != MI && !Predicated.count(Use)) return false; @@ -1058,7 +1060,7 @@ return true; } - unsigned CountReg = Start->getOperand(0).getReg(); + Register CountReg = Start->getOperand(0).getReg(); auto IsMoveLR = [&CountReg](MachineInstr *MI) { return MI->getOpcode() == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::LR && @@ -1069,8 +1071,10 @@ // Find an insertion point: // - Is there a (mov lr, Count) before Start? If so, and nothing else // writes to Count before Start, we can insert at start. - if (auto *LRDef = RDA.getUniqueReachingMIDef(Start, ARM::LR)) { - if (IsMoveLR(LRDef) && RDA.hasSameReachingDef(Start, LRDef, CountReg)) { + if (auto *LRDef = + RDA.getUniqueReachingMIDef(Start, MCRegister::from(ARM::LR))) { + if (IsMoveLR(LRDef) && + RDA.hasSameReachingDef(Start, LRDef, CountReg.asMCReg())) { SmallPtrSet Ignore = { Dec }; if (!TryRemove(LRDef, RDA, ToRemove, Ignore)) return false; @@ -1084,7 +1088,8 @@ // to Count after Start, we can insert at that mov (which will now be // dead). MachineBasicBlock *MBB = Start->getParent(); - if (auto *LRDef = RDA.getLocalLiveOutMIDef(MBB, ARM::LR)) { + if (auto *LRDef = + RDA.getLocalLiveOutMIDef(MBB, MCRegister::from(ARM::LR))) { if (IsMoveLR(LRDef) && RDA.hasSameReachingDef(Start, LRDef, CountReg)) { SmallPtrSet Ignore = { Start, Dec }; if (!TryRemove(LRDef, RDA, ToRemove, Ignore)) @@ -1097,7 +1102,7 @@ // We've found no suitable LR def and Start doesn't use LR directly. Can we // just define LR anyway? - if (!RDA.isSafeToDefRegAt(Start, ARM::LR)) + if (!RDA.isSafeToDefRegAt(Start, MCRegister::from(ARM::LR))) return false; InsertPt = MachineBasicBlock::iterator(Start); @@ -1133,7 +1138,7 @@ // If it does, store it in the VCTPs set, else refuse it. MachineInstr *Prev = VCTPs.back(); if (!Prev->getOperand(1).isIdenticalTo(MI->getOperand(1)) || - !RDA.hasSameReachingDef(Prev, MI, MI->getOperand(1).getReg())) { + !RDA.hasSameReachingDef(Prev, MI, MI->getOperand(1).getReg().asMCReg())) { LLVM_DEBUG(dbgs() << "ARM Loops: Found VCTP with a different reaching " "definition from the main VCTP"); return false; @@ -1324,7 +1329,7 @@ // Check that the only instruction using LoopDec is LoopEnd. // TODO: Check for copy chains that really have no effect. SmallPtrSet Uses; - RDA->getReachingLocalUses(LoLoop.Dec, ARM::LR, Uses); + RDA->getReachingLocalUses(LoLoop.Dec, MCRegister::from(ARM::LR), Uses); if (Uses.size() > 1 || !Uses.count(LoLoop.End)) { LLVM_DEBUG(dbgs() << "ARM Loops: Unable to remove LoopDec.\n"); LoLoop.Revert = true; @@ -1371,7 +1376,8 @@ } // If nothing defines CPSR between LoopDec and LoopEnd, use a t2SUBS. - bool SetFlags = RDA->isSafeToDefRegAt(MI, ARM::CPSR, Ignore); + bool SetFlags = + RDA->isSafeToDefRegAt(MI, MCRegister::from(ARM::CPSR), Ignore); MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2SUBri));