[ARM] [TableGen] Clean up !if(!eq(boolean, 1) and related booleans

[Paul-C-Anagnostopoulos]

Summary

With the addition of the !not operator to TableGen, I'm making a pass over all the targets to clean up the boolean expressions. This is the patch for the ARM.

[lattner]

These seem obvious to me Paul, please feel free to move forward with similar cleanups without individual approval (according to your judgement) or in a single larger patch that touches everything at once.

[Paul-C-Anagnostopoulos]

I figured this revision could sit here for 24 hours just to let the target owners know I was fooling in their backyard.

[dmgreen]

Yeah, LGTM

llvm/lib/Target/ARM/ARMInstrMVE.td

 multiclass MVE_VABSNEG_int_m<string iname, bit negate, bit saturate,
                              SDNode unpred_op, Intrinsic pred_int,
                              MVEVectorVTInfo VTI> {
   def "" : MVE_VABSNEG_int<iname, VTI.Suffix, VTI.Size, negate, saturate>;
   defvar Inst = !cast<Instruction>(NAME);
 
   let Predicates = [HasMVEInt] in {
     // VQABS and VQNEG have more difficult isel patterns defined elsewhere
-    if !eq(saturate, 0) then {
+    if !not(saturate) then {
       def : Pat<(VTI.Vec (unpred_op (VTI.Vec MQPR:$v))),
                 (VTI.Vec (Inst $v))>;
     }
 
     def : Pat<(VTI.Vec (pred_int  (VTI.Vec MQPR:$v), (VTI.Pred VCCR:$mask),
                                   (VTI.Vec MQPR:$inactive))),
               (VTI.Vec (Inst $v, ARMVCCThen, $mask, $inactive))>;
   }
class MVE_VxMOVxN<string iname, string suffix, bit bit_28, bit bit_17,
 
   let Inst{28} = bit_28;
   let Inst{21-20} = 0b11;
   let Inst{19-18} = size;
   let Inst{17} = bit_17;
   let Inst{16} = 0b1;
   let Inst{12} = T;
   let Inst{8} = 0b0;
-  let Inst{7} = !if(!eq(bit_17, 0), 1, 0);
+  let Inst{7} = !not(bit_17);
   let Inst{0} = 0b1;
   let validForTailPredication = 1;
   let retainsPreviousHalfElement = 1;
 }
 
 multiclass MVE_VxMOVxN_halves<string iname, string suffix,
                               bit bit_28, bit bit_17, bits<2> size> {
   def bh : MVE_VxMOVxN<iname # "b", suffix, bit_28, bit_17, size, 0b0>;

 multiclass MVE_VMOVN_p<Instruction Inst, bit top,
                        MVEVectorVTInfo VTI, MVEVectorVTInfo InVTI> {
   // Match the most obvious MVEvmovn(a,b,t), which overwrites the odd or even
   // lanes of a (depending on t) with the even lanes of b.
   def : Pat<(VTI.Vec (MVEvmovn (VTI.Vec MQPR:$Qd_src),
                                (VTI.Vec MQPR:$Qm), (i32 top))),
             (VTI.Vec (Inst (VTI.Vec MQPR:$Qd_src), (VTI.Vec MQPR:$Qm)))>;
 
-  if !eq(top, 0) then {
+  if !not(top) then {
     // If we see MVEvmovn(a,ARMvrev(b),1), that wants to overwrite the odd
     // lanes of a with the odd lanes of b. In other words, the lanes we're
     // _keeping_ from a are the even ones. So we can flip it round and say that
     // this is the same as overwriting the even lanes of b with the even lanes
     // of a, i.e. it's a VMOVNB with the operands reversed.
     defvar vrev = !cast<SDNode>("ARMvrev" # InVTI.LaneBits);
     def : Pat<(VTI.Vec (MVEvmovn (VTI.Vec MQPR:$Qm),
                                  (VTI.Vec (vrev MQPR:$Qd_src)), (i32 1))),