Index: llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp =================================================================== --- llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp +++ llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp @@ -1052,10 +1052,15 @@ ReachingDefAnalysis &RDA, InstSet &ToRemove) { // We can define LR because LR already contains the same value. + // There shouldn't be a def of LR after the start if (Start->getOperand(0).getReg() == ARM::LR) { - InsertPt = MachineBasicBlock::iterator(Start); - InsertBB = Start->getParent(); - return true; + auto *LRDef = RDA.getLocalLiveOutMIDef(Start->getParent(), ARM::LR); + auto *StartLRDef = RDA.getUniqueReachingMIDef(Start, ARM::LR); + if (LRDef == nullptr || StartLRDef == LRDef) { + InsertPt = MachineBasicBlock::iterator(Start); + InsertBB = Start->getParent(); + return true; + } } unsigned CountReg = Start->getOperand(0).getReg(); Index: llvm/test/CodeGen/Thumb2/LowOverheadLoops/lr-def-after-start.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/Thumb2/LowOverheadLoops/lr-def-after-start.mir @@ -0,0 +1,243 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s + +--- | + define arm_aapcs_vfpcc void @do_loop_start_kills_reg(float* %pSrc, i32 %blockSize, float* nocapture %pResult) { + entry: + %0 = add i32 %blockSize, 3 + %1 = icmp slt i32 %blockSize, 4 + %smin = select i1 %1, i32 %blockSize, i32 4 + %2 = sub i32 %0, %smin + %3 = lshr i32 %2, 2 + %4 = add nuw nsw i32 %3, 1 + %5 = icmp slt i32 %blockSize, 4 + %smin3 = select i1 %5, i32 %blockSize, i32 4 + %6 = sub i32 %0, %smin3 + %7 = lshr i32 %6, 2 + %8 = add nuw nsw i32 %7, 1 + call void @llvm.set.loop.iterations.i32(i32 %8) + br label %do.body.i + + do.body.i: ; preds = %do.body.i, %entry + %blkCnt.0.i = phi i32 [ %13, %do.body.i ], [ %blockSize, %entry ] + %sumVec.0.i = phi <4 x float> [ %12, %do.body.i ], [ zeroinitializer, %entry ] + %pSrc.addr.0.i = phi float* [ %add.ptr.i, %do.body.i ], [ %pSrc, %entry ] + %9 = phi i32 [ %8, %entry ], [ %14, %do.body.i ] + %pSrc.addr.0.i2 = bitcast float* %pSrc.addr.0.i to <4 x float>* + %10 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %blkCnt.0.i) + %11 = tail call fast <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %pSrc.addr.0.i2, i32 4, <4 x i1> %10, <4 x float> zeroinitializer) + %12 = tail call fast <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %sumVec.0.i, <4 x float> %11, <4 x i1> %10, <4 x float> %sumVec.0.i) + %add.ptr.i = getelementptr inbounds float, float* %pSrc.addr.0.i, i32 4 + %13 = add i32 %blkCnt.0.i, -4 + %14 = call i32 @llvm.loop.decrement.reg.i32(i32 %9, i32 1) + %15 = icmp ne i32 %14, 0 + br i1 %15, label %do.body.i, label %arm_mean_f32_mve.exit + + arm_mean_f32_mve.exit: ; preds = %do.body.i + %16 = extractelement <4 x float> %12, i32 3 + %add2.i.i = fadd fast float %16, %16 + %conv.i = uitofp i32 %blockSize to float + %div.i = fdiv fast float %add2.i.i, %conv.i + %17 = bitcast float %div.i to i32 + call void @llvm.set.loop.iterations.i32(i32 %4) + br label %do.body + + do.body: ; preds = %do.body, %arm_mean_f32_mve.exit + %blkCnt.0 = phi i32 [ %blockSize, %arm_mean_f32_mve.exit ], [ %26, %do.body ] + %sumVec.0 = phi <4 x float> [ zeroinitializer, %arm_mean_f32_mve.exit ], [ %25, %do.body ] + %pSrc.addr.0 = phi float* [ %pSrc, %arm_mean_f32_mve.exit ], [ %add.ptr, %do.body ] + %18 = phi i32 [ %4, %arm_mean_f32_mve.exit ], [ %27, %do.body ] + %pSrc.addr.01 = bitcast float* %pSrc.addr.0 to <4 x float>* + %19 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %blkCnt.0) + %20 = tail call fast <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %pSrc.addr.01, i32 4, <4 x i1> %19, <4 x float> zeroinitializer) + %21 = insertelement <4 x i32> undef, i32 %17, i64 0 + %22 = shufflevector <4 x i32> %21, <4 x i32> undef, <4 x i32> zeroinitializer + %23 = bitcast <4 x i32> %22 to <4 x float> + %24 = tail call fast <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float> %20, <4 x float> %23, <4 x i1> %19, <4 x float> undef) + %25 = tail call fast <4 x float> @llvm.arm.mve.fma.predicated.v4f32.v4i1(<4 x float> %24, <4 x float> %24, <4 x float> %sumVec.0, <4 x i1> %19) + %add.ptr = getelementptr inbounds float, float* %pSrc.addr.0, i32 4 + %26 = add i32 %blkCnt.0, -4 + %27 = call i32 @llvm.loop.decrement.reg.i32(i32 %18, i32 1) + %28 = icmp ne i32 %27, 0 + br i1 %28, label %do.body, label %do.end + + do.end: ; preds = %do.body + %29 = extractelement <4 x float> %25, i32 3 + %add2.i = fadd fast float %29, %29 + %sub2 = add i32 %blockSize, -1 + %conv = uitofp i32 %sub2 to float + %div = fdiv fast float %add2.i, %conv + store float %div, float* %pResult, align 4 + ret void + } + + declare <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) + declare <4 x float> @llvm.arm.mve.fma.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x float>, <4 x i1>) + declare <4 x i1> @llvm.arm.mve.vctp32(i32) + declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32 immarg, <4 x i1>, <4 x float>) + declare <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) + declare void @llvm.set.loop.iterations.i32(i32) + declare i32 @llvm.loop.decrement.reg.i32(i32, i32) +... +--- +name: do_loop_start_kills_reg +alignment: 2 +tracksRegLiveness: true +registers: [] +liveins: + - { reg: '$r0', virtual-reg: '' } + - { reg: '$r1', virtual-reg: '' } + - { reg: '$r2', virtual-reg: '' } +frameInfo: + stackSize: 8 + offsetAdjustment: 0 + maxAlignment: 4 +fixedStack: [] +stack: + - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, + stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +callSites: [] +constants: [] +machineFunctionInfo: {} +body: | + ; CHECK-LABEL: name: do_loop_start_kills_reg + ; CHECK: bb.0.entry: + ; CHECK: successors: %bb.1(0x80000000) + ; CHECK: liveins: $lr, $r0, $r1, $r2, $r4 + ; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, $r4, killed $lr, implicit-def $sp, implicit $sp + ; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8 + ; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4 + ; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8 + ; CHECK: $r3 = tMOVr $r1, 14 /* CC::al */, $noreg + ; CHECK: tCMPi8 renamable $r1, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK: t2IT 10, 8, implicit-def $itstate + ; CHECK: renamable $r3 = tMOVi8 $noreg, 4, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r3, implicit killed $itstate + ; CHECK: renamable $r12 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK: renamable $r3, dead $cpsr = tSUBrr renamable $r1, killed renamable $r3, 14 /* CC::al */, $noreg + ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 + ; CHECK: renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 3, 14 /* CC::al */, $noreg + ; CHECK: dead renamable $lr = nuw nsw t2ADDrs killed renamable $r12, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg + ; CHECK: $r3 = tMOVr $r1, 14 /* CC::al */, $noreg + ; CHECK: $r12 = tMOVr $r0, 14 /* CC::al */, $noreg + ; CHECK: renamable $lr = tMOVr $r2, 14 /* CC::al */, $noreg + ; CHECK: bb.1.do.body.i: + ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000) + ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r12 + ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg + ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg + ; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr + ; CHECK: MVE_VPST 4, implicit $vpr + ; CHECK: renamable $r12, renamable $q1 = MVE_VLDRWU32_post killed renamable $r12, 16, 1, renamable $vpr :: (load 16 from %ir.pSrc.addr.0.i2, align 4) + ; CHECK: renamable $q0 = MVE_VADDf32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, killed renamable $q0 + ; CHECK: tBcc %bb.1, 1 /* CC::ne */, killed $cpsr + ; CHECK: tB %bb.2, 14 /* CC::al */, $noreg + ; CHECK: bb.2.arm_mean_f32_mve.exit: + ; CHECK: successors: %bb.3(0x80000000) + ; CHECK: liveins: $q0, $r0, $r1, $r2, $r4 + ; CHECK: $s4 = VMOVSR $r1, 14 /* CC::al */, $noreg + ; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, killed renamable $s3, 14 /* CC::al */, $noreg, implicit killed $q0 + ; CHECK: $r3 = tMOVr $r1, 14 /* CC::al */, $noreg + ; CHECK: renamable $s4 = VUITOS killed renamable $s4, 14 /* CC::al */, $noreg + ; CHECK: $lr = t2DLS killed $r4 + ; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s4, 14 /* CC::al */, $noreg + ; CHECK: renamable $r12 = VMOVRS killed renamable $s0, 14 /* CC::al */, $noreg + ; CHECK: renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 + ; CHECK: bb.3.do.body: + ; CHECK: successors: %bb.3(0x7c000000), %bb.4(0x04000000) + ; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r12 + ; CHECK: renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg + ; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg + ; CHECK: MVE_VPST 2, implicit $vpr + ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load 16 from %ir.pSrc.addr.01, align 4) + ; CHECK: renamable $q1 = MVE_VSUB_qr_f32 killed renamable $q1, renamable $r12, 1, renamable $vpr, undef renamable $q1 + ; CHECK: renamable $q0 = MVE_VFMAf32 killed renamable $q0, killed renamable $q1, killed renamable $q1, 1, killed renamable $vpr + ; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.3 + ; CHECK: bb.4.do.end: + ; CHECK: liveins: $q0, $r1, $r2 + ; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 1, 14 /* CC::al */, $noreg + ; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, killed renamable $s3, 14 /* CC::al */, $noreg, implicit killed $q0 + ; CHECK: $s2 = VMOVSR killed $r0, 14 /* CC::al */, $noreg + ; CHECK: renamable $s2 = VUITOS killed renamable $s2, 14 /* CC::al */, $noreg + ; CHECK: renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg + ; CHECK: VSTRS killed renamable $s0, killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (store 4 into %ir.pResult) + ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc + bb.0.entry: + successors: %bb.1(0x80000000) + liveins: $r0, $r1, $r2, $r4, $lr + + frame-setup tPUSH 14 /* CC::al */, $noreg, $r4, killed $lr, implicit-def $sp, implicit $sp + frame-setup CFI_INSTRUCTION def_cfa_offset 8 + frame-setup CFI_INSTRUCTION offset $lr, -4 + frame-setup CFI_INSTRUCTION offset $r4, -8 + $r3 = tMOVr $r1, 14 /* CC::al */, $noreg + tCMPi8 renamable $r1, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr + t2IT 10, 8, implicit-def $itstate + renamable $r3 = tMOVi8 $noreg, 4, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r3, implicit killed $itstate + renamable $r12 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg + renamable $r3, dead $cpsr = tSUBrr renamable $r1, killed renamable $r3, 14 /* CC::al */, $noreg + renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 + renamable $r3, dead $cpsr = tADDi8 killed renamable $r3, 3, 14 /* CC::al */, $noreg + renamable $lr = nuw nsw t2ADDrs killed renamable $r12, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg + $r3 = tMOVr $r1, 14 /* CC::al */, $noreg + $r12 = tMOVr $r0, 14 /* CC::al */, $noreg + t2DoLoopStart renamable $lr + renamable $lr = tMOVr $r2, 14 /* CC::al */, $noreg + + bb.1.do.body.i: + successors: %bb.1(0x7c000000), %bb.2(0x04000000) + liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r12, $lr + + renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg + renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg + renamable $lr = t2LoopDec renamable $lr, 1 + MVE_VPST 4, implicit $vpr + renamable $r12, renamable $q1 = MVE_VLDRWU32_post killed renamable $r12, 16, 1, renamable $vpr :: (load 16 from %ir.pSrc.addr.0.i2, align 4) + renamable $q0 = MVE_VADDf32 killed renamable $q0, killed renamable $q1, 1, killed renamable $vpr, renamable $q0 + t2LoopEnd renamable $lr, %bb.1.do.body.i, implicit-def dead $cpsr + tB %bb.2.arm_mean_f32_mve.exit, 14 /* CC::al */, $noreg + + bb.2.arm_mean_f32_mve.exit: + successors: %bb.3(0x80000000) + liveins: $q0, $r0, $r1, $r2, $r4 + + $s4 = VMOVSR $r1, 14 /* CC::al */, $noreg + $lr = tMOVr $r4, 14 /* CC::al */, $noreg + renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, renamable $s3, 14 /* CC::al */, $noreg, implicit $q0 + $r3 = tMOVr $r1, 14 /* CC::al */, $noreg + renamable $s4 = VUITOS killed renamable $s4, 14 /* CC::al */, $noreg + t2DoLoopStart killed $r4 + renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s4, 14 /* CC::al */, $noreg + renamable $r12 = VMOVRS killed renamable $s0, 14 /* CC::al */, $noreg + renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q0 + + bb.3.do.body: + successors: %bb.3(0x7c000000), %bb.4(0x04000000) + liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r12 + + renamable $vpr = MVE_VCTP32 renamable $r3, 0, $noreg + renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg + renamable $lr = t2LoopDec killed renamable $lr, 1 + MVE_VPST 2, implicit $vpr + renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr :: (load 16 from %ir.pSrc.addr.01, align 4) + renamable $q1 = MVE_VSUB_qr_f32 killed renamable $q1, renamable $r12, 1, renamable $vpr, undef renamable $q1 + renamable $q0 = MVE_VFMAf32 killed renamable $q0, killed renamable $q1, renamable $q1, 1, killed renamable $vpr + t2LoopEnd renamable $lr, %bb.3.do.body, implicit-def dead $cpsr + tB %bb.4.do.end, 14 /* CC::al */, $noreg + + bb.4.do.end: + liveins: $q0, $r1, $r2 + + renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 1, 14 /* CC::al */, $noreg + renamable $s0 = nnan ninf nsz arcp contract afn reassoc VADDS killed renamable $s3, renamable $s3, 14 /* CC::al */, $noreg, implicit $q0 + $s2 = VMOVSR killed $r0, 14 /* CC::al */, $noreg + renamable $s2 = VUITOS killed renamable $s2, 14 /* CC::al */, $noreg + renamable $s0 = nnan ninf nsz arcp contract afn reassoc VDIVS killed renamable $s0, killed renamable $s2, 14 /* CC::al */, $noreg + VSTRS killed renamable $s0, killed renamable $r2, 0, 14 /* CC::al */, $noreg :: (store 4 into %ir.pResult) + frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc + +... +