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[mlir] Simplify DDR matching patterns with equal operands for operators where it's applicable.
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Authored by rdzhabarov on Oct 16 2020, 3:10 PM.

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Summary

This https://reviews.llvm.org/D89254 diff introduced implicit matching between same name operands.
Change docs and some usages accordingly.

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Event Timeline

rdzhabarov created this revision.Oct 16 2020, 3:10 PM
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rdzhabarov requested review of this revision.Oct 16 2020, 3:10 PM

Nice

mlir/docs/DeclarativeRewrites.md
142

s/automatic// ?

(and perhaps s/enforces/ensures/)

mlir/include/mlir/IR/OpBase.td
2294–2295

While here, seems bind fits the tense better.

2296

I'd differentiate here: for me (my mental model) is one operand is bound and the other(s) verified. Only one value has that name, the rest are just verified to be equal to it (conceptually they need never even be named or bound, and that we do today is an implementation detail).

2316

The above also changes this explanation here

commented.

mlir/include/mlir/IR/OpBase.td
2294–2295

sg

2296

I'm happy to change to what makes more sense.

Operands in the source pattern could have the same name. This makes one operand to be bound to that name and the rest verified to be equal.

Let me know.

rdzhabarov marked 4 inline comments as done.Oct 16 2020, 5:02 PM

fixed.

fix wording.

jpienaar accepted this revision.Oct 19 2020, 2:53 PM

Nice, thanks!

mlir/include/mlir/IR/OpBase.td
2296

Looks good, minor nit: This bounds one operand to the name while verifying the rest are all equal? [the "to be bound" feels like it could be simplified and the previous is one suggestion]

This revision is now accepted and ready to land.Oct 19 2020, 2:53 PM
rdzhabarov marked an inline comment as done.Oct 19 2020, 9:50 PM