[AMDGPU] flat scratch ST addressing mode on gfx10

[rampitec]

Summary

GFX10 enables third addressing mode for flat scratch instructions,
an ST mode. In that mode both register operands are omitted and
only swizzled offset is used in addition to flat_scratch base.

[foad]

LGTM.

llvm/lib/Target/AMDGPU/FLATInstructions.td

239

Use !not? See D89331.

[rampitec]

• Use !not in td file.
• Only enable ST mode from gfx1030.

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h

754

Add a comment explaining what this means

[rampitec]

Added comment.

[foad]

llvm/lib/Target/AMDGPU/AMDGPU.td

1140–1141

I think technically the assembler/disassembler support should be in GFX10.1, it's just that we don't want the compiler to generate them until GFX10.3 because of hardware bugs. Maybe at least add a comment explaining why the predicate is FeatureGFX10_3Insts here?

[rampitec]

llvm/lib/Target/AMDGPU/AMDGPU.td

1140–1141

Given the errata there is no difference to Vega. It was possible to encode off/off from start. It just plain does not work and no point to support or allow.

llvm/lib/Target/AMDGPU/AMDGPU.td

def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
   AssemblerPredicate<(all_of FeatureFlatGlobalInsts)>;
 def HasFlatScratchInsts : Predicate<"Subtarget->hasFlatScratchInsts()">,
   AssemblerPredicate<(all_of FeatureFlatScratchInsts)>;
 def HasScalarFlatScratchInsts : Predicate<"Subtarget->hasScalarFlatScratchInsts()">,
   AssemblerPredicate<(all_of FeatureScalarFlatScratchInsts)>;
 def HasD16LoadStore : Predicate<"Subtarget->hasD16LoadStore()">,
   AssemblerPredicate<(all_of FeatureGFX9Insts)>;
 
+def HasFlatScratchSTMode : Predicate<"Subtarget->hasFlatScratchSTMode()">,
+  AssemblerPredicate<(any_of FeatureGFX10_3Insts)>;
+
 def HasGFX10_BEncoding : Predicate<"Subtarget->hasGFX10_BEncoding()">,
   AssemblerPredicate<(all_of FeatureGFX10_BEncoding)>;
 
 def HasUnpackedD16VMem : Predicate<"Subtarget->hasUnpackedD16VMem()">,
   AssemblerPredicate<(all_of FeatureUnpackedD16VMem)>;
 def HasPackedD16VMem : Predicate<"!Subtarget->hasUnpackedD16VMem()">,
   AssemblerPredicate<(all_of (not FeatureUnpackedD16VMem))>;
 

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h

public:
   bool hasFlatGlobalInsts() const {
     return FlatGlobalInsts;
   }
 
   bool hasFlatScratchInsts() const {
     return FlatScratchInsts;
   }
 
+  // Check if target supports ST addressing mode with FLAT scratch instructions.
+  // The ST addressing mode means no registers are used, either VGPR or SGPR,
+  // but only immediate offset is swizzled and added to the FLAT scratch base.
+  bool hasFlatScratchSTMode() const {
+    return hasFlatScratchInsts() && hasGFX10_3Insts();
+  }
+
   bool hasScalarFlatScratchInsts() const {
     return ScalarFlatScratchInsts;
   }
 
   bool hasGlobalAddTidInsts() const {
     return GFX10_BEncoding;
   }
 

llvm/lib/Target/AMDGPU/FLATInstructions.td

class FLAT_Global_Store_AddTid_Pseudo <string opName, RegisterClass vdataClass,
   let has_vaddr = 0;
   let has_saddr = 1;
   let enabled_saddr = 1;
   let maybeAtomic = 1;
 }
 
 class FLAT_Scratch_Load_Pseudo <string opName, RegisterClass regClass,
   bit HasTiedOutput = 0,
-  bit EnableSaddr = 0>: FLAT_Pseudo<
+  bit EnableSaddr = 0,
+  bit EnableVaddr = !not(EnableSaddr)>
+  : FLAT_Pseudo<
   opName,
   (outs regClass:$vdst),
   !con(
      !if(EnableSaddr,
-        (ins SReg_32_XEXEC_HI:$saddr, flat_offset:$offset),
-        (ins VGPR_32:$vaddr, flat_offset:$offset)),
+       !if(EnableVaddr,
+         (ins VGPR_32:$vaddr, flat_offset:$offset),
+         (ins flat_offset:$offset))),
      !if(HasTiedOutput, (ins GLC:$glc, SLC:$slc, DLC:$dlc, regClass:$vdst_in),
                         (ins GLC_0:$glc, SLC_0:$slc, DLC_0:$dlc))),
-  " $vdst, "#!if(EnableSaddr, "off", "$vaddr")#!if(EnableSaddr, ", $saddr", ", off")#"$offset$glc$slc$dlc"> {
+  " $vdst, "#!if(EnableVaddr, "$vaddr, ", "off, ")#!if(EnableSaddr, "$saddr", "off")#"$offset$glc$slc$dlc"> {
   let has_data = 0;
   let mayLoad = 1;
   let has_saddr = 1;
   let enabled_saddr = EnableSaddr;
-  let has_vaddr = !if(EnableSaddr, 0, 1);
-  let PseudoInstr = opName#!if(EnableSaddr, "_SADDR", "");
+  let has_vaddr = EnableVaddr;
+  let PseudoInstr = opName#!if(EnableSaddr, "_SADDR", !if(EnableVaddr, "", "_ST"));
   let maybeAtomic = 1;
 
   let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
   let DisableEncoding = !if(HasTiedOutput, "$vdst_in", "");
 }
 
-class FLAT_Scratch_Store_Pseudo <string opName, RegisterClass vdataClass, bit EnableSaddr = 0> : FLAT_Pseudo<
+class FLAT_Scratch_Store_Pseudo <string opName, RegisterClass vdataClass, bit EnableSaddr = 0,
+  bit EnableVaddr = !not(EnableSaddr)> : FLAT_Pseudo<
   opName,
   (outs),
   !if(EnableSaddr,
     (ins vdataClass:$vdata, SReg_32_XEXEC_HI:$saddr, flat_offset:$offset, GLC_0:$glc, SLC_0:$slc, DLC_0:$dlc),
-    (ins vdataClass:$vdata, VGPR_32:$vaddr, flat_offset:$offset, GLC_0:$glc, SLC_0:$slc, DLC_0:$dlc)),
-  " "#!if(EnableSaddr, "off", "$vaddr")#", $vdata, "#!if(EnableSaddr, "$saddr", "off")#"$offset$glc$slc$dlc"> {
+    !if(EnableVaddr,
+      (ins vdataClass:$vdata, VGPR_32:$vaddr, flat_offset:$offset, GLC_0:$glc, SLC_0:$slc, DLC_0:$dlc),
+      (ins vdataClass:$vdata, flat_offset:$offset, GLC_0:$glc, SLC_0:$slc, DLC_0:$dlc))),
+  " "#!if(EnableVaddr, "$vaddr", "off")#", $vdata, "#!if(EnableSaddr, "$saddr", "off")#"$offset$glc$slc$dlc"> {
   let mayLoad  = 0;
   let mayStore = 1;
   let has_vdst = 0;
   let has_saddr = 1;
   let enabled_saddr = EnableSaddr;
-  let has_vaddr = !if(EnableSaddr, 0, 1);
-  let PseudoInstr = opName#!if(EnableSaddr, "_SADDR", "");
+  let has_vaddr = EnableVaddr;
+  let PseudoInstr = opName#!if(EnableSaddr, "_SADDR", !if(EnableVaddr, "", "_ST"));
   let maybeAtomic = 1;
 }
 
 multiclass FLAT_Scratch_Load_Pseudo<string opName, RegisterClass regClass, bit HasTiedOutput = 0> {
   let is_flat_scratch = 1 in {
     def "" : FLAT_Scratch_Load_Pseudo<opName, regClass, HasTiedOutput>;
     def _SADDR : FLAT_Scratch_Load_Pseudo<opName, regClass, HasTiedOutput, 1>;
+
+    let SubtargetPredicate = HasFlatScratchSTMode in
+    def _ST  : FLAT_Scratch_Load_Pseudo<opName, regClass, HasTiedOutput, 0, 0>;
   }
 }
 
 multiclass FLAT_Scratch_Store_Pseudo<string opName, RegisterClass regClass> {
   let is_flat_scratch = 1 in {
     def "" : FLAT_Scratch_Store_Pseudo<opName, regClass>;
     def _SADDR : FLAT_Scratch_Store_Pseudo<opName, regClass, 1>;
+
+    let SubtargetPredicate = HasFlatScratchSTMode in
+    def _ST  : FLAT_Scratch_Store_Pseudo<opName, regClass, 0, 0>;
   }
 }
 
 class FLAT_AtomicNoRet_Pseudo<string opName, dag outs, dag ins,
                                string asm, list<dag> pattern = []> :
   FLAT_Pseudo<opName, outs, ins, asm, pattern> {
     let mayLoad = 1;
     let mayStore = 1;
def _SADDR_gfx10 :
     FLAT_Real_gfx10<op, !cast<FLAT_Pseudo>(NAME#"_SADDR")>;
 }
 
 multiclass FLAT_Real_SADDR_RTN_gfx10<bits<7> op> {
   def _SADDR_RTN_gfx10 :
     FLAT_Real_gfx10<op, !cast<FLAT_Pseudo>(NAME#"_SADDR_RTN")>;
 }
 
+multiclass FLAT_Real_ST_gfx10<bits<7> op> {
+  def _ST_gfx10 :
+    FLAT_Real_gfx10<op, !cast<FLAT_Pseudo>(NAME#"_ST")> {
+      let Inst{54-48} = !cast<int>(EXEC_HI.HWEncoding);
+      let OtherPredicates = [HasFlatScratchSTMode];
+    }
+}
 
 multiclass FLAT_Real_AllAddr_gfx10<bits<7> op> :
   FLAT_Real_Base_gfx10<op>,
   FLAT_Real_SADDR_gfx10<op>;
 
 multiclass FLAT_Real_Atomics_gfx10<bits<7> op> :
   FLAT_Real_Base_gfx10<op>,
   FLAT_Real_RTN_gfx10<op>;
 
 multiclass FLAT_Real_GlblAtomics_gfx10<bits<7> op> :
   FLAT_Real_AllAddr_gfx10<op>,
   FLAT_Real_RTN_gfx10<op>,
   FLAT_Real_SADDR_RTN_gfx10<op>;
 
 multiclass FLAT_Real_GlblAtomics_RTN_gfx10<bits<7> op> :
   FLAT_Real_RTN_gfx10<op>,
   FLAT_Real_SADDR_RTN_gfx10<op>;
 
+multiclass FLAT_Real_ScratchAllAddr_gfx10<bits<7> op> :
+  FLAT_Real_Base_gfx10<op>,
+  FLAT_Real_SADDR_gfx10<op>,
+  FLAT_Real_ST_gfx10<op>;
+
 // ENC_FLAT.
 defm FLAT_LOAD_UBYTE            : FLAT_Real_Base_gfx10<0x008>;
 defm FLAT_LOAD_SBYTE            : FLAT_Real_Base_gfx10<0x009>;
 defm FLAT_LOAD_USHORT           : FLAT_Real_Base_gfx10<0x00a>;
 defm FLAT_LOAD_SSHORT           : FLAT_Real_Base_gfx10<0x00b>;
 defm FLAT_LOAD_DWORD            : FLAT_Real_Base_gfx10<0x00c>;
 defm FLAT_LOAD_DWORDX2          : FLAT_Real_Base_gfx10<0x00d>;
 defm FLAT_LOAD_DWORDX4          : FLAT_Real_Base_gfx10<0x00e>;

 defm GLOBAL_ATOMIC_DEC_X2       : FLAT_Real_GlblAtomics_gfx10<0x05d>;
 defm GLOBAL_ATOMIC_FCMPSWAP_X2  : FLAT_Real_GlblAtomics_gfx10<0x05e>;
 defm GLOBAL_ATOMIC_FMIN_X2      : FLAT_Real_GlblAtomics_gfx10<0x05f>;
 defm GLOBAL_ATOMIC_FMAX_X2      : FLAT_Real_GlblAtomics_gfx10<0x060>;
 defm GLOBAL_LOAD_DWORD_ADDTID   : FLAT_Real_Base_gfx10<0x016>;
 defm GLOBAL_STORE_DWORD_ADDTID  : FLAT_Real_Base_gfx10<0x017>;
 
 // ENC_FLAT_SCRATCH.
-defm SCRATCH_LOAD_UBYTE         : FLAT_Real_AllAddr_gfx10<0x008>;
-defm SCRATCH_LOAD_SBYTE         : FLAT_Real_AllAddr_gfx10<0x009>;
-defm SCRATCH_LOAD_USHORT        : FLAT_Real_AllAddr_gfx10<0x00a>;
-defm SCRATCH_LOAD_SSHORT        : FLAT_Real_AllAddr_gfx10<0x00b>;
-defm SCRATCH_LOAD_DWORD         : FLAT_Real_AllAddr_gfx10<0x00c>;
-defm SCRATCH_LOAD_DWORDX2       : FLAT_Real_AllAddr_gfx10<0x00d>;
-defm SCRATCH_LOAD_DWORDX4       : FLAT_Real_AllAddr_gfx10<0x00e>;
-defm SCRATCH_LOAD_DWORDX3       : FLAT_Real_AllAddr_gfx10<0x00f>;
-defm SCRATCH_STORE_BYTE         : FLAT_Real_AllAddr_gfx10<0x018>;
-defm SCRATCH_STORE_BYTE_D16_HI  : FLAT_Real_AllAddr_gfx10<0x019>;
-defm SCRATCH_STORE_SHORT        : FLAT_Real_AllAddr_gfx10<0x01a>;
-defm SCRATCH_STORE_SHORT_D16_HI : FLAT_Real_AllAddr_gfx10<0x01b>;
-defm SCRATCH_STORE_DWORD        : FLAT_Real_AllAddr_gfx10<0x01c>;
-defm SCRATCH_STORE_DWORDX2      : FLAT_Real_AllAddr_gfx10<0x01d>;
-defm SCRATCH_STORE_DWORDX4      : FLAT_Real_AllAddr_gfx10<0x01e>;
-defm SCRATCH_STORE_DWORDX3      : FLAT_Real_AllAddr_gfx10<0x01f>;
-defm SCRATCH_LOAD_UBYTE_D16     : FLAT_Real_AllAddr_gfx10<0x020>;
-defm SCRATCH_LOAD_UBYTE_D16_HI  : FLAT_Real_AllAddr_gfx10<0x021>;
-defm SCRATCH_LOAD_SBYTE_D16     : FLAT_Real_AllAddr_gfx10<0x022>;
-defm SCRATCH_LOAD_SBYTE_D16_HI  : FLAT_Real_AllAddr_gfx10<0x023>;
-defm SCRATCH_LOAD_SHORT_D16     : FLAT_Real_AllAddr_gfx10<0x024>;
-defm SCRATCH_LOAD_SHORT_D16_HI  : FLAT_Real_AllAddr_gfx10<0x025>;
+defm SCRATCH_LOAD_UBYTE         : FLAT_Real_ScratchAllAddr_gfx10<0x008>;
+defm SCRATCH_LOAD_SBYTE         : FLAT_Real_ScratchAllAddr_gfx10<0x009>;
+defm SCRATCH_LOAD_USHORT        : FLAT_Real_ScratchAllAddr_gfx10<0x00a>;
+defm SCRATCH_LOAD_SSHORT        : FLAT_Real_ScratchAllAddr_gfx10<0x00b>;
+defm SCRATCH_LOAD_DWORD         : FLAT_Real_ScratchAllAddr_gfx10<0x00c>;
+defm SCRATCH_LOAD_DWORDX2       : FLAT_Real_ScratchAllAddr_gfx10<0x00d>;
+defm SCRATCH_LOAD_DWORDX4       : FLAT_Real_ScratchAllAddr_gfx10<0x00e>;
+defm SCRATCH_LOAD_DWORDX3       : FLAT_Real_ScratchAllAddr_gfx10<0x00f>;
+defm SCRATCH_STORE_BYTE         : FLAT_Real_ScratchAllAddr_gfx10<0x018>;
+defm SCRATCH_STORE_BYTE_D16_HI  : FLAT_Real_ScratchAllAddr_gfx10<0x019>;
+defm SCRATCH_STORE_SHORT        : FLAT_Real_ScratchAllAddr_gfx10<0x01a>;
+defm SCRATCH_STORE_SHORT_D16_HI : FLAT_Real_ScratchAllAddr_gfx10<0x01b>;
+defm SCRATCH_STORE_DWORD        : FLAT_Real_ScratchAllAddr_gfx10<0x01c>;
+defm SCRATCH_STORE_DWORDX2      : FLAT_Real_ScratchAllAddr_gfx10<0x01d>;
+defm SCRATCH_STORE_DWORDX4      : FLAT_Real_ScratchAllAddr_gfx10<0x01e>;
+defm SCRATCH_STORE_DWORDX3      : FLAT_Real_ScratchAllAddr_gfx10<0x01f>;
+defm SCRATCH_LOAD_UBYTE_D16     : FLAT_Real_ScratchAllAddr_gfx10<0x020>;
+defm SCRATCH_LOAD_UBYTE_D16_HI  : FLAT_Real_ScratchAllAddr_gfx10<0x021>;
+defm SCRATCH_LOAD_SBYTE_D16     : FLAT_Real_ScratchAllAddr_gfx10<0x022>;
+defm SCRATCH_LOAD_SBYTE_D16_HI  : FLAT_Real_ScratchAllAddr_gfx10<0x023>;
+defm SCRATCH_LOAD_SHORT_D16     : FLAT_Real_ScratchAllAddr_gfx10<0x024>;
+defm SCRATCH_LOAD_SHORT_D16_HI  : FLAT_Real_ScratchAllAddr_gfx10<0x025>;
 
 let SubtargetPredicate = HasAtomicFaddInsts in {
 
 defm GLOBAL_ATOMIC_ADD_F32    : FLAT_Real_AllAddr_vi <0x04d>;
 defm GLOBAL_ATOMIC_PK_ADD_F16 : FLAT_Real_AllAddr_vi <0x04e>;
 
 } // End SubtargetPredicate = HasAtomicFaddInsts

llvm/test/MC/AMDGPU/flat-scratch-st-mode.s

+// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga 2>&1 %s | FileCheck -check-prefix=VI-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 2>&1 %s | FileCheck -check-prefix=GFX9_10-ERR --implicit-check-not=error: %s
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 2>&1 %s | FileCheck --check-prefixes=GFX9_10-ERR --implicit-check-not=error: %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1030 -show-encoding %s | FileCheck --check-prefixes=GFX1030 %s
+
+scratch_load_ubyte v1, off, off
+// GFX1030: encoding: [0x00,0x40,0x20,0xdc,0x00,0x00,0x7f,0x01]
+// GFX9_10-ERR: error: operands are not valid for this GPU or mode
+// VI-ERR: error: instruction not supported on this GPU
+
+scratch_load_sbyte v1, off, off
+// GFX1030: encoding: [0x00,0x40,0x24,0xdc,0x00,0x00,0x7f,0x01]
+// GFX9_10-ERR: error: operands are not valid for this GPU or mode
+// VI-ERR: error: instruction not supported on this GPU
+
+scratch_load_ushort v1, off, off
+// GFX1030: encoding: [0x00,0x40,0x28,0xdc,0x00,0x00,0x7f,0x01]
+// GFX9_10-ERR: error: operands are not valid for this GPU or mode
+// VI-ERR: error: instruction not supported on this GPU
+
+scratch_load_sshort v1, off, off
+// GFX1030: encoding: [0x00,0x40,0x2c,0xdc,0x00,0x00,0x7f,0x01]
+// GFX9_10-ERR: error: operands are not valid for this GPU or mode
+// VI-ERR: error: instruction not supported on this GPU
+
+scratch_load_dword v1, off, off
+// GFX1030: encoding: [0x00,0x40,0x30,0xdc,0x00,0x00,0x7f,0x01]
+// GFX9_10-ERR: error: operands are not valid for this GPU or mode
+// VI-ERR: error: instruction not supported on this GPU
+
+scratch_load_dwordx2 v[1:2], off, off
+// GFX1030: encoding: [0x00,0x40,0x34,0xdc,0x00,0x00,0x7f,0x01]
+// GFX9_10-ERR: error: operands are not valid for this GPU or mode
+// VI-ERR: error: instruction not supported on this GPU
+
+scratch_load_dwordx3 v[1:3], off, off
+// GFX1030: encoding: [0x00,0x40,0x3c,0xdc,0x00,0x00,0x7f,0x01]
+// GFX9_10-ERR: error: operands are not valid for this GPU or mode
+// VI-ERR: error: instruction not supported on this GPU
+
+scratch_load_dwordx4 v[1:4], off, off
+// GFX1030: encoding: [0x00,0x40,0x38,0xdc,0x00,0x00,0x7f,0x01]
+// GFX9_10-ERR: error: operands are not valid for this GPU or mode
+// VI-ERR: error: instruction not supported on this GPU
+
+scratch_load_dword v1, off, off offset:2047
+// GFX1030: scratch_load_dword v1, off, off offset:2047 ; encoding: [0xff,0x47,0x30,0xdc,0x00,0x00,0x7f,0x01]
+// GFX9_10-ERR: error: operands are not valid for this GPU or mode
+// VI-ERR: error: instruction not supported on this GPU
+
+scratch_store_byte off, v2, off
+// GFX1030: encoding: [0x00,0x40,0x60,0xdc,0x00,0x02,0x7f,0x00]
+// GFX9_10-ERR: error: operands are not valid for this GPU or mode
+// VI-ERR: error: instruction not supported on this GPU
+
+scratch_store_short off, v2, off
+// GFX1030: encoding: [0x00,0x40,0x68,0xdc,0x00,0x02,0x7f,0x00]
+// GFX9_10-ERR: error: operands are not valid for this GPU or mode
+// VI-ERR: error: instruction not supported on this GPU
+
+scratch_store_dword off, v2, off
+// GFX1030: encoding: [0x00,0x40,0x70,0xdc,0x00,0x02,0x7f,0x00]
+// GFX9_10-ERR: error: operands are not valid for this GPU or mode
+// VI-ERR: error: instruction not supported on this GPU
+
+scratch_store_dwordx2 off, v[2:3], off
+// GFX1030: encoding: [0x00,0x40,0x74,0xdc,0x00,0x02,0x7f,0x00]
+// GFX9_10-ERR: error: operands are not valid for this GPU or mode
+// VI-ERR: error: instruction not supported on this GPU
+
+scratch_store_dwordx3 off, v[2:4], off
+// GFX1030: encoding: [0x00,0x40,0x7c,0xdc,0x00,0x02,0x7f,0x00]
+// GFX9_10-ERR: error: operands are not valid for this GPU or mode
+// VI-ERR: error: instruction not supported on this GPU
+
+scratch_store_dwordx4 off, v[2:5], off
+// GFX1030: encoding: [0x00,0x40,0x78,0xdc,0x00,0x02,0x7f,0x00]
+// GFX9_10-ERR: error: operands are not valid for this GPU or mode
+// VI-ERR: error: instruction not supported on this GPU
+
+scratch_store_dword off, v2, off offset:2047
+// GFX1030: scratch_store_dword off, v2, off offset:2047 ; encoding: [0xff,0x47,0x70,0xdc,0x00,0x02,0x7f,0x00]
+// GFX9_10-ERR: error: operands are not valid for this GPU or mode
+// VI-ERR: error: instruction not supported on this GPU
+
+scratch_load_ubyte_d16 v1, off, off
+// GFX1030: encoding: [0x00,0x40,0x80,0xdc,0x00,0x00,0x7f,0x01]
+// GFX9_10-ERR: error: operands are not valid for this GPU or mode
+// VI-ERR: error: instruction not supported on this GPU
+
+scratch_load_ubyte_d16_hi v1, off, off
+// GFX1030: encoding: [0x00,0x40,0x84,0xdc,0x00,0x00,0x7f,0x01]
+// GFX9_10-ERR: error: operands are not valid for this GPU or mode
+// VI-ERR: error: instruction not supported on this GPU
+
+scratch_load_sbyte_d16 v1, off, off
+// GFX1030: encoding: [0x00,0x40,0x88,0xdc,0x00,0x00,0x7f,0x01]
+// GFX9_10-ERR: error: operands are not valid for this GPU or mode
+// VI-ERR: error: instruction not supported on this GPU
+
+scratch_load_sbyte_d16_hi v1, off, off
+// GFX1030: encoding: [0x00,0x40,0x8c,0xdc,0x00,0x00,0x7f,0x01]
+// GFX9_10-ERR: error: operands are not valid for this GPU or mode
+// VI-ERR: error: instruction not supported on this GPU
+
+scratch_load_short_d16 v1, off, off
+// GFX1030: encoding: [0x00,0x40,0x90,0xdc,0x00,0x00,0x7f,0x01]
+// GFX9_10-ERR: error: operands are not valid for this GPU or mode
+// VI-ERR: error: instruction not supported on this GPU
+
+scratch_load_short_d16_hi v1, off, off
+// GFX1030: encoding: [0x00,0x40,0x94,0xdc,0x00,0x00,0x7f,0x01]
+// GFX9_10-ERR: error: operands are not valid for this GPU or mode
+// VI-ERR: error: instruction not supported on this GPU
+
+scratch_store_byte_d16_hi off, v2, off
+// GFX1030: encoding: [0x00,0x40,0x64,0xdc,0x00,0x02,0x7f,0x00]
+// GFX9_10-ERR: error: operands are not valid for this GPU or mode
+// VI-ERR: error: instruction not supported on this GPU
+
+
+scratch_store_short_d16_hi off, v2, off
+// GFX1030: encoding: [0x00,0x40,0x6c,0xdc,0x00,0x02,0x7f,0x00]
+// GFX9_10-ERR: error: operands are not valid for this GPU or mode
+// VI-ERR: error: instruction not supported on this GPU

llvm/test/MC/Disassembler/AMDGPU/gfx1030_dasm_new.txt

 # GFX10: image_msaa_load v5, v[1:2], s[8:15] dmask:0x1 dim:SQ_RSRC_IMG_2D d16
 0x09,0x01,0x00,0xf0,0x01,0x05,0x02,0x80
 
 # GFX10: image_msaa_load v[1:4], v5, s[8:15] dmask:0xf dim:SQ_RSRC_IMG_1D
 0x01,0x0f,0x00,0xf0,0x05,0x01,0x02,0x00
 
 # GFX10: image_msaa_load v14, [v204, v11, v14, v19], s[40:47] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
 0x3b,0x01,0x00,0xf0,0xcc,0x0e,0x0a,0x00,0x0b,0x0e,0x13,0x00
+
+# GFX10: scratch_load_ubyte v1, off, off ; encoding: [0x00,0x40,0x20,0xdc,0x00,0x00,0x7f,0x01]
+0x00,0x40,0x20,0xdc,0x00,0x00,0x7f,0x01
+
+# GFX10: scratch_load_sbyte v1, off, off ; encoding: [0x00,0x40,0x24,0xdc,0x00,0x00,0x7f,0x01]
+0x00,0x40,0x24,0xdc,0x00,0x00,0x7f,0x01
+
+# GFX10: scratch_load_ushort v1, off, off ; encoding: [0x00,0x40,0x28,0xdc,0x00,0x00,0x7f,0x01]
+0x00,0x40,0x28,0xdc,0x00,0x00,0x7f,0x01
+
+# GFX10: scratch_load_sshort v1, off, off ; encoding: [0x00,0x40,0x2c,0xdc,0x00,0x00,0x7f,0x01]
+0x00,0x40,0x2c,0xdc,0x00,0x00,0x7f,0x01
+
+# GFX10: scratch_load_dword v1, off, off ; encoding: [0x00,0x40,0x30,0xdc,0x00,0x00,0x7f,0x01]
+0x00,0x40,0x30,0xdc,0x00,0x00,0x7f,0x01
+
+# GFX10: scratch_load_dwordx2 v[1:2], off, off ; encoding: [0x00,0x40,0x34,0xdc,0x00,0x00,0x7f,0x01]
+0x00,0x40,0x34,0xdc,0x00,0x00,0x7f,0x01
+
+# GFX10: scratch_load_dwordx3 v[1:3], off, off ; encoding: [0x00,0x40,0x3c,0xdc,0x00,0x00,0x7f,0x01]
+0x00,0x40,0x3c,0xdc,0x00,0x00,0x7f,0x01
+
+# GFX10: scratch_load_dwordx4 v[1:4], off, off ; encoding: [0x00,0x40,0x38,0xdc,0x00,0x00,0x7f,0x01]
+0x00,0x40,0x38,0xdc,0x00,0x00,0x7f,0x01
+
+# GFX10: scratch_load_dword v1, off, off offset:2047 ; encoding: [0xff,0x47,0x30,0xdc,0x00,0x00,0x7f,0x01]
+0xff,0x47,0x30,0xdc,0x00,0x00,0x7f,0x01
+
+# GFX10: scratch_store_byte off, v2, off ; encoding: [0x00,0x40,0x60,0xdc,0x00,0x02,0x7f,0x00]
+0x00,0x40,0x60,0xdc,0x00,0x02,0x7f,0x00
+
+# GFX10: scratch_store_short off, v2, off ; encoding: [0x00,0x40,0x68,0xdc,0x00,0x02,0x7f,0x00]
+0x00,0x40,0x68,0xdc,0x00,0x02,0x7f,0x00
+
+# GFX10: scratch_store_dword off, v2, off ; encoding: [0x00,0x40,0x70,0xdc,0x00,0x02,0x7f,0x00]
+0x00,0x40,0x70,0xdc,0x00,0x02,0x7f,0x00
+
+# GFX10: scratch_store_dwordx2 off, v[2:3], off ; encoding: [0x00,0x40,0x74,0xdc,0x00,0x02,0x7f,0x00]
+0x00,0x40,0x74,0xdc,0x00,0x02,0x7f,0x00
+
+# GFX10: scratch_store_dwordx3 off, v[2:4], off ; encoding: [0x00,0x40,0x7c,0xdc,0x00,0x02,0x7f,0x00]
+0x00,0x40,0x7c,0xdc,0x00,0x02,0x7f,0x00
+
+# GFX10: scratch_store_dwordx4 off, v[2:5], off ; encoding: [0x00,0x40,0x78,0xdc,0x00,0x02,0x7f,0x00]
+0x00,0x40,0x78,0xdc,0x00,0x02,0x7f,0x00
+
+# GFX10: scratch_store_dword off, v2, off offset:2047 ; encoding: [0xff,0x47,0x70,0xdc,0x00,0x02,0x7f,0x00]
+0xff,0x47,0x70,0xdc,0x00,0x02,0x7f,0x00
+
+# GFX10: scratch_load_ubyte_d16 v1, off, off ; encoding: [0x00,0x40,0x80,0xdc,0x00,0x00,0x7f,0x01]
+0x00,0x40,0x80,0xdc,0x00,0x00,0x7f,0x01
+
+# GFX10: scratch_load_ubyte_d16_hi v1, off, off ; encoding: [0x00,0x40,0x84,0xdc,0x00,0x00,0x7f,0x01]
+0x00,0x40,0x84,0xdc,0x00,0x00,0x7f,0x01
+
+# GFX10: scratch_load_sbyte_d16 v1, off, off ; encoding: [0x00,0x40,0x88,0xdc,0x00,0x00,0x7f,0x01]
+0x00,0x40,0x88,0xdc,0x00,0x00,0x7f,0x01
+
+# GFX10: scratch_load_sbyte_d16_hi v1, off, off ; encoding: [0x00,0x40,0x8c,0xdc,0x00,0x00,0x7f,0x01]
+0x00,0x40,0x8c,0xdc,0x00,0x00,0x7f,0x01
+
+# GFX10: scratch_load_short_d16 v1, off, off ; encoding: [0x00,0x40,0x90,0xdc,0x00,0x00,0x7f,0x01]
+0x00,0x40,0x90,0xdc,0x00,0x00,0x7f,0x01
+
+# GFX10: scratch_load_short_d16_hi v1, off, off ; encoding: [0x00,0x40,0x94,0xdc,0x00,0x00,0x7f,0x01]
+0x00,0x40,0x94,0xdc,0x00,0x00,0x7f,0x01
+
+# GFX10: scratch_store_byte_d16_hi off, v2, off ; encoding: [0x00,0x40,0x64,0xdc,0x00,0x02,0x7f,0x00]
+0x00,0x40,0x64,0xdc,0x00,0x02,0x7f,0x00
+
+# GFX10: scratch_store_short_d16_hi off, v2, off ; encoding: [0x00,0x40,0x6c,0xdc,0x00,0x02,0x7f,0x00]
+0x00,0x40,0x6c,0xdc,0x00,0x02,0x7f,0x00