Index: llvm/lib/Target/RISCV/RISCVSystemOperands.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -175,6 +175,7 @@
 //===-------------------------------------
 // Supervisor Protection and Translation
 //===-------------------------------------
+let AltName = "sptbr" in // Privileged spec v1.9.1 Name
 def : SysReg<"satp", 0x180>;
 
 //===-----------------------------
Index: llvm/test/MC/RISCV/supervisor-csr-names.s
===================================================================
--- llvm/test/MC/RISCV/supervisor-csr-names.s
+++ llvm/test/MC/RISCV/supervisor-csr-names.s
@@ -191,3 +191,17 @@
 csrrs t1, satp, zero
 # uimm12
 csrrs t2, 0x180, zero
+
+# sptbr
+# name
+# CHECK-INST: csrrs t1, satp, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x00,0x18]
+# CHECK-INST-ALIAS: csrr t1, satp
+# uimm12
+# CHECK-INST: csrrs t2, satp, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x18]
+# CHECK-INST-ALIAS: csrr t2, satp
+# name
+csrrs t1, sptbr, zero
+# uimm12
+csrrs t2, 0x180, zero