[NFC][regalloc] Use MCRegister instead of unsigned in InterferenceCache

[mtrofin]

Summary

Also changed users of APIs.

llvm/lib/CodeGen/InterferenceCache.h

struct BlockInterference {
 
     BlockInterference() {}
   };
 
   /// Entry - A cache entry containing interference information for all aliases
   /// of PhysReg in all basic blocks.
   class Entry {
     /// PhysReg - The register currently represented.
-    unsigned PhysReg = 0;
+    MCRegister PhysReg = 0;
 
     /// Tag - Cache tag is changed when any of the underlying LiveIntervalUnions
     /// change.
     unsigned Tag = 0;
 
     /// RefCount - The total number of Cursor instances referring to this Entry.
     unsigned RefCount = 0;
 
class Entry {
     /// update - Recompute Blocks[MBBNum]
     void update(unsigned MBBNum);
 
   public:
     Entry() = default;
 
     void clear(MachineFunction *mf, SlotIndexes *indexes, LiveIntervals *lis) {
       assert(!hasRefs() && "Cannot clear cache entry with references");
-      PhysReg = 0;
+      PhysReg = MCRegister::NoRegister;
       MF = mf;
       Indexes = indexes;
       LIS = lis;
     }
 
-    unsigned getPhysReg() const { return PhysReg; }
+    MCRegister getPhysReg() const { return PhysReg; }
 
     void addRef(int Delta) { RefCount += Delta; }
 
     bool hasRefs() const { return RefCount > 0; }
 
     void revalidate(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI);
 
     /// valid - Return true if this is a valid entry for physReg.
     bool valid(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI);
 
     /// reset - Initialize entry to represent physReg's aliases.
-    void reset(unsigned physReg,
-               LiveIntervalUnion *LIUArray,
-               const TargetRegisterInfo *TRI,
-               const MachineFunction *MF);
+    void reset(MCRegister physReg, LiveIntervalUnion *LIUArray,
+               const TargetRegisterInfo *TRI, const MachineFunction *MF);
 
     /// get - Return an up to date BlockInterference.
     BlockInterference *get(unsigned MBBNum) {
       if (Blocks[MBBNum].Tag != Tag)
         update(MBBNum);
       return &Blocks[MBBNum];
     }
   };
class LLVM_LIBRARY_VISIBILITY InterferenceCache {
 
   // Next round-robin entry to be picked.
   unsigned RoundRobin = 0;
 
   // The actual cache entries.
   Entry Entries[CacheEntries];
 
   // get - Get a valid entry for PhysReg.
-  Entry *get(unsigned PhysReg);
+  Entry *get(MCRegister PhysReg);
 
 public:
   InterferenceCache() = default;
 
   ~InterferenceCache() {
     free(PhysRegEntries);
   }
 
public:
     Cursor &operator=(const Cursor &O) {
       setEntry(O.CacheEntry);
       return *this;
     }
 
     ~Cursor() { setEntry(nullptr); }
 
     /// setPhysReg - Point this cursor to PhysReg's interference.
-    void setPhysReg(InterferenceCache &Cache, unsigned PhysReg) {
+    void setPhysReg(InterferenceCache &Cache, MCRegister PhysReg) {
       // Release reference before getting a new one. That guarantees we can
       // actually have CacheEntries live cursors.
       setEntry(nullptr);
-      if (PhysReg)
+      if (PhysReg.isValid())
         setEntry(Cache.get(PhysReg));
     }
 
     /// moveTo - Move cursor to basic block MBBNum.
     void moveToBlock(unsigned MBBNum) {
       Current = CacheEntry ? CacheEntry->get(MBBNum) : &NoInterference;
     }
 

llvm/lib/CodeGen/InterferenceCache.cpp

void InterferenceCache::init(MachineFunction *mf,
   MF = mf;
   LIUArray = liuarray;
   TRI = tri;
   reinitPhysRegEntries();
   for (unsigned i = 0; i != CacheEntries; ++i)
     Entries[i].clear(mf, indexes, lis);
 }
 
-InterferenceCache::Entry *InterferenceCache::get(unsigned PhysReg) {
-  unsigned E = PhysRegEntries[PhysReg];
+InterferenceCache::Entry *InterferenceCache::get(MCRegister PhysReg) {
+  unsigned char E = PhysRegEntries[PhysReg.id()];
   if (E < CacheEntries && Entries[E].getPhysReg() == PhysReg) {
     if (!Entries[E].valid(LIUArray, TRI))
       Entries[E].revalidate(LIUArray, TRI);
     return &Entries[E];
   }
   // No valid entry exists, pick the next round-robin entry.
   E = RoundRobin;
   if (++RoundRobin == CacheEntries)
void InterferenceCache::Entry::revalidate(LiveIntervalUnion *LIUArray,
   ++Tag;
   // Invalidate all iterators.
   PrevPos = SlotIndex();
   unsigned i = 0;
   for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i)
     RegUnits[i].VirtTag = LIUArray[*Units].getTag();
 }
 
-void InterferenceCache::Entry::reset(unsigned physReg,
+void InterferenceCache::Entry::reset(MCRegister physReg,
                                      LiveIntervalUnion *LIUArray,
                                      const TargetRegisterInfo *TRI,
                                      const MachineFunction *MF) {
   assert(!hasRefs() && "Cannot reset cache entry with references");
   // LIU's changed, invalidate cache.
   ++Tag;
   PhysReg = physReg;
   Blocks.resize(MF->getNumBlockIDs());

llvm/lib/CodeGen/RegAllocGreedy.cpp

struct GlobalSplitCandidate {
 
     // Interference for PhysReg.
     InterferenceCache::Cursor Intf;
 
     // Bundles where this candidate should be live.
     BitVector LiveBundles;
     SmallVector<unsigned, 8> ActiveBlocks;
 
-    void reset(InterferenceCache &Cache, unsigned Reg) {
+    void reset(InterferenceCache &Cache, MCRegister Reg) {
       PhysReg = Reg;
       IntvIdx = 0;
       Intf.setPhysReg(Cache, Reg);
       LiveBundles.clear();
       ActiveBlocks.clear();
     }
 
     // Set B[I] = C for every live bundle where B[I] was NoCand.

 /// Returns false if the current live range is already compact, or if the
 /// compact regions would form single block regions anyway.
 bool RAGreedy::calcCompactRegion(GlobalSplitCandidate &Cand) {
   // Without any through blocks, the live range is already compact.
   if (!SA->getNumThroughBlocks())
     return false;
 
   // Compact regions don't correspond to any physreg.
-  Cand.reset(IntfCache, 0);
+  Cand.reset(IntfCache, MCRegister::NoRegister);
 
   LLVM_DEBUG(dbgs() << "Compact region bundles");
 
   // Use the spill placer to determine the live bundles. GrowRegion pretends
   // that all the through blocks have interference when PhysReg is unset.
   SpillPlacer->prepare(Cand.LiveBundles);
 
   // The static split cost will be zero since Cand.Intf reports no interference.