Index: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -1353,6 +1353,13 @@
       break;
     }
 
+    case AMDGPU::S_MOV_B32:
+      if (FrameReg) {
+        MI->getOperand(FIOperandNum).ChangeToRegister(FrameReg, false);
+        break;
+      }
+      LLVM_FALLTHROUGH;
+
     default: {
       const DebugLoc &DL = MI->getDebugLoc();
       bool IsMUBUF = TII->isMUBUF(*MI);
Index: llvm/test/CodeGen/AMDGPU/scratch-store-sgpr-fp.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/scratch-store-sgpr-fp.mir
@@ -0,0 +1,25 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefix=GCN %s
+
+---
+name:            s_mov_from_fi
+tracksRegLiveness: true
+stack:
+  - { id: 0, type: default, offset: 0, size: 40, alignment: 4,
+      stack-id: default }
+machineFunctionInfo:
+  stackPtrOffsetReg: '$sgpr32'
+body:             |
+  bb.0.entry:
+    liveins: $sgpr30_sgpr31
+
+    ; GCN-LABEL: name: s_mov_from_fi
+    ; GCN: liveins: $sgpr30_sgpr31
+    ; GCN: renamable $sgpr4 = S_MOV_B32 $sgpr32
+    ; GCN: SCRATCH_STORE_DWORD_SADDR killed undef $vgpr1, killed renamable $sgpr4, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
+    ; GCN: S_SETPC_B64_return killed renamable $sgpr30_sgpr31
+    renamable $sgpr4 = S_MOV_B32 %stack.0
+    SCRATCH_STORE_DWORD_SADDR killed undef $vgpr1, killed renamable $sgpr4, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
+    S_SETPC_B64_return killed renamable $sgpr30_sgpr31
+
+...