diff --git a/llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td b/llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td
new file mode 100644
--- /dev/null
+++ b/llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td
@@ -0,0 +1,39 @@
+// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
+
+include "llvm/Target/Target.td"
+include "GlobalISelEmitterCommon.td"
+
+let Namespace = "MyTarget" in {
+
+def lo8  : SubRegIndex<8>;
+def hi8  : SubRegIndex<8, 8>;
+def lo16 : SubRegIndex<16>;
+def hi16 : SubRegIndex<16, 16>;
+
+def a0bl : Register<"a0bl">;
+def a0bh : Register<"a0bh">;
+def a0wh : Register<"a0wh">;
+
+} // Namespace = "MyTarget"
+
+def a0wl: RegisterWithSubRegs<"a0", [a0bh, a0bl]> {
+  let SubRegIndices = [hi8, lo8];
+  let CoveredBySubRegs = 1;
+}
+
+def a0: RegisterWithSubRegs<"a0", [a0wh, a0wl]> {
+  let SubRegIndices = [hi16, lo16];
+  let CoveredBySubRegs = 1;
+}
+
+def A0b : RegisterClass<"MyTarget",  [i8],  8, (add a0bl)>;
+def A0w : RegisterClass<"MyTarget", [i16], 16, (add a0wl)>;
+def A0  : RegisterClass<"MyTarget", [i32], 32, (add a0)>;
+
+def : Pat<(i16 (anyext i8:$src)),
+          (i16 (EXTRACT_SUBREG
+                 (i32 (INSERT_SUBREG
+                        (i32 (IMPLICIT_DEF)),
+                        A0b:$src,
+                        lo8)),
+                 lo16))>;
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -4951,6 +4951,17 @@
       return None;
     return getRegClassFromLeaf(RCChild);
   }
+  else if (InstName == "INSERT_SUBREG") {
+    TreePatternNode *Child0 = N->getChild(0);
+    assert(Child0->getNumTypes() == 1 && "Unexpected number of types!");
+    const TypeSetByHwMode &VTy = Child0->getExtType(0);
+    return inferSuperRegisterClassForNode(VTy, Child0, N->getChild(2));
+  }
+  else if (InstName == "EXTRACT_SUBREG") {
+    assert(N->getNumTypes() == 1 && "Unexpected number of types!");
+    const TypeSetByHwMode &VTy = N->getExtType(0);
+    return inferSuperRegisterClass(VTy, N->getChild(1));
+  }
 
   // Handle destination record types that we can safely infer a register class
   // from.