Index: llvm/cmake/config-ix.cmake =================================================================== --- llvm/cmake/config-ix.cmake +++ llvm/cmake/config-ix.cmake @@ -405,6 +405,8 @@ if (LLVM_NATIVE_ARCH MATCHES "i[2-6]86") set(LLVM_NATIVE_ARCH X86) +elseif (LLVM_NATIVE_ARCH STREQUAL "m68k") + set(LLVM_NATIVE_ARCH M680x0) elseif (LLVM_NATIVE_ARCH STREQUAL "x86") set(LLVM_NATIVE_ARCH X86) elseif (LLVM_NATIVE_ARCH STREQUAL "amd64") Index: llvm/cmake/modules/HandleLLVMOptions.cmake =================================================================== --- llvm/cmake/modules/HandleLLVMOptions.cmake +++ llvm/cmake/modules/HandleLLVMOptions.cmake @@ -323,6 +323,12 @@ add_definitions( -D_FILE_OFFSET_BITS=64 ) endif() +# GCC m68k on Linux by default aligns on 16bit, we want 32 +if(LLVM_INFERRED_HOST_TRIPLE STREQUAL "m68k-unknown-linux-gnu") + set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -malign-int") + set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -malign-int") +endif() + if( CMAKE_SIZEOF_VOID_P EQUAL 8 AND NOT WIN32 ) # TODO: support other platforms and toolchains. if( LLVM_BUILD_32_BITS ) Index: llvm/include/llvm/ADT/Triple.h =================================================================== --- llvm/include/llvm/ADT/Triple.h +++ llvm/include/llvm/ADT/Triple.h @@ -78,6 +78,7 @@ tcele, // TCE little endian (http://tce.cs.tut.fi/): tcele thumb, // Thumb (little endian): thumb, thumbv.* thumbeb, // Thumb (big endian): thumbeb + m680x0, // M680x0: Motorola 680x0 family x86, // X86: i[3-9]86 x86_64, // X86-64: amd64, x86_64 xcore, // XCore: xcore Index: llvm/include/llvm/BinaryFormat/ELF.h =================================================================== --- llvm/include/llvm/BinaryFormat/ELF.h +++ llvm/include/llvm/BinaryFormat/ELF.h @@ -736,6 +736,11 @@ #include "ELFRelocs/BPF.def" }; +// ELF Relocation types for M680x0 +enum { +#include "ELFRelocs/m680x0.def" +}; + // MSP430 specific e_flags enum : unsigned { EF_MSP430_MACH_MSP430x11 = 11, Index: llvm/include/llvm/BinaryFormat/ELFRelocs/m680x0.def =================================================================== --- /dev/null +++ llvm/include/llvm/BinaryFormat/ELFRelocs/m680x0.def @@ -0,0 +1,50 @@ + +#ifndef ELF_RELOC +#error "ELF_RELOC must be defined" +#endif + +ELF_RELOC (R_M680x0_NONE, 0) /* No reloc */ +ELF_RELOC (R_M680x0_32, 1) /* Direct 32 bit */ +ELF_RELOC (R_M680x0_16, 2) /* Direct 16 bit */ +ELF_RELOC (R_M680x0_8, 3) /* Direct 8 bit */ +ELF_RELOC (R_M680x0_PC32, 4) /* PC relative 32 bit */ +ELF_RELOC (R_M680x0_PC16, 5) /* PC relative 16 bit */ +ELF_RELOC (R_M680x0_PC8, 6) /* PC relative 8 bit */ +ELF_RELOC (R_M680x0_GOTPCREL32, 7) /* 32 bit PC relative GOT entry */ +ELF_RELOC (R_M680x0_GOTPCREL16, 8) /* 16 bit PC relative GOT entry */ +ELF_RELOC (R_M680x0_GOTPCREL8, 9) /* 8 bit PC relative GOT entry */ +ELF_RELOC (R_M680x0_GOTOFF32, 10) /* 32 bit GOT offset */ +ELF_RELOC (R_M680x0_GOTOFF16, 11) /* 16 bit GOT offset */ +ELF_RELOC (R_M680x0_GOTOFF8, 12) /* 8 bit GOT offset */ +ELF_RELOC (R_M680x0_PLT32, 13) /* 32 bit PC relative PLT address */ +ELF_RELOC (R_M680x0_PLT16, 14) /* 16 bit PC relative PLT address */ +ELF_RELOC (R_M680x0_PLT8, 15) /* 8 bit PC relative PLT address */ +ELF_RELOC (R_M680x0_PLTOFF32, 16) /* 32 bit PLT offset */ +ELF_RELOC (R_M680x0_PLTOFF16, 17) /* 16 bit PLT offset */ +ELF_RELOC (R_M680x0_PLTOFF8, 18) /* 8 bit PLT offset */ +ELF_RELOC (R_M680x0_COPY, 19) /* Copy symbol at runtime */ +ELF_RELOC (R_M680x0_GLOB_DAT, 20) /* Create GOT entry */ +ELF_RELOC (R_M680x0_JMP_SLOT, 21) /* Create PLT entry */ +ELF_RELOC (R_M680x0_RELATIVE, 22) /* Adjust by program base */ +/* These are GNU extensions to enable C++ vtable garbage collection. */ +ELF_RELOC (R_M680x0_GNU_VTINHERIT, 23) +ELF_RELOC (R_M680x0_GNU_VTENTRY, 24) +/* TLS static relocations. */ +ELF_RELOC (R_M680x0_TLS_GD32, 25) +ELF_RELOC (R_M680x0_TLS_GD16, 26) +ELF_RELOC (R_M680x0_TLS_GD8, 27) +ELF_RELOC (R_M680x0_TLS_LDM32, 28) +ELF_RELOC (R_M680x0_TLS_LDM16, 29) +ELF_RELOC (R_M680x0_TLS_LDM8, 30) +ELF_RELOC (R_M680x0_TLS_LDO32, 31) +ELF_RELOC (R_M680x0_TLS_LDO16, 32) +ELF_RELOC (R_M680x0_TLS_LDO8, 33) +ELF_RELOC (R_M680x0_TLS_IE32, 34) +ELF_RELOC (R_M680x0_TLS_IE16, 35) +ELF_RELOC (R_M680x0_TLS_IE8, 36) +ELF_RELOC (R_M680x0_TLS_LE32, 37) +ELF_RELOC (R_M680x0_TLS_LE16, 38) +ELF_RELOC (R_M680x0_TLS_LE8, 39) +ELF_RELOC (R_M680x0_TLS_DTPMOD32, 40) +ELF_RELOC (R_M680x0_TLS_DTPREL32, 41) +ELF_RELOC (R_M680x0_TLS_TPREL32, 42) Index: llvm/include/llvm/IR/CallingConv.h =================================================================== --- llvm/include/llvm/IR/CallingConv.h +++ llvm/include/llvm/IR/CallingConv.h @@ -241,6 +241,9 @@ /// The remainder matches the regular calling convention. WASM_EmscriptenInvoke = 99, + /// M680x0_INTR - Calling convention used for M680x0 interrupt routines. + M680x0_INTR = 1000, + /// The highest possible calling convention ID. Must be some 2^k - 1. MaxID = 1023 }; Index: llvm/include/llvm/MC/MCExpr.h =================================================================== --- llvm/include/llvm/MC/MCExpr.h +++ llvm/include/llvm/MC/MCExpr.h @@ -199,6 +199,7 @@ VK_GOTOFF, VK_GOTREL, VK_PCREL, + VK_GOTPC, VK_GOTPCREL, VK_GOTTPOFF, VK_INDNTPOFF, Index: llvm/include/llvm/Object/ELFObjectFile.h =================================================================== --- llvm/include/llvm/Object/ELFObjectFile.h +++ llvm/include/llvm/Object/ELFObjectFile.h @@ -1090,6 +1090,8 @@ switch (EF.getHeader()->e_ident[ELF::EI_CLASS]) { case ELF::ELFCLASS32: switch (EF.getHeader()->e_machine) { + case ELF::EM_68K: + return "ELF32-M680x0"; case ELF::EM_386: return "elf32-i386"; case ELF::EM_IAMCU: @@ -1158,6 +1160,8 @@ template Triple::ArchType ELFObjectFile::getArch() const { bool IsLittleEndian = ELFT::TargetEndianness == support::little; switch (EF.getHeader()->e_machine) { + case ELF::EM_68K: + return Triple::m680x0; case ELF::EM_386: case ELF::EM_IAMCU: return Triple::x86; Index: llvm/include/llvm/module.modulemap =================================================================== --- llvm/include/llvm/module.modulemap +++ llvm/include/llvm/module.modulemap @@ -80,6 +80,7 @@ textual header "BinaryFormat/ELFRelocs/x86_64.def" textual header "BinaryFormat/WasmRelocs.def" textual header "BinaryFormat/MsgPack.def" + textual header "BinaryFormat/ELFRelocs/m680x0.def" } module LLVM_Config { Index: llvm/lib/MC/MCExpr.cpp =================================================================== --- llvm/lib/MC/MCExpr.cpp +++ llvm/lib/MC/MCExpr.cpp @@ -225,6 +225,7 @@ case VK_GOTOFF: return "GOTOFF"; case VK_GOTREL: return "GOTREL"; case VK_PCREL: return "PCREL"; + case VK_GOTPC: return "GOTPC"; case VK_GOTPCREL: return "GOTPCREL"; case VK_GOTTPOFF: return "GOTTPOFF"; case VK_INDNTPOFF: return "INDNTPOFF"; @@ -379,6 +380,7 @@ .Case("gotoff", VK_GOTOFF) .Case("gotrel", VK_GOTREL) .Case("pcrel", VK_PCREL) + .Case("gotpc", VK_GOTPC) .Case("gotpcrel", VK_GOTPCREL) .Case("gottpoff", VK_GOTTPOFF) .Case("indntpoff", VK_INDNTPOFF) Index: llvm/lib/Object/ELF.cpp =================================================================== --- llvm/lib/Object/ELF.cpp +++ llvm/lib/Object/ELF.cpp @@ -22,6 +22,13 @@ StringRef llvm::object::getELFRelocationTypeName(uint32_t Machine, uint32_t Type) { switch (Machine) { + case ELF::EM_68K: + switch (Type) { +#include "llvm/BinaryFormat/ELFRelocs/m680x0.def" + default: + break; + } + break; case ELF::EM_X86_64: switch (Type) { #include "llvm/BinaryFormat/ELFRelocs/x86_64.def" Index: llvm/lib/ObjectYAML/ELFYAML.cpp =================================================================== --- llvm/lib/ObjectYAML/ELFYAML.cpp +++ llvm/lib/ObjectYAML/ELFYAML.cpp @@ -681,6 +681,9 @@ case ELF::EM_PPC64: #include "llvm/BinaryFormat/ELFRelocs/PowerPC64.def" break; + case ELF::EM_68K: +#include "llvm/BinaryFormat/ELFRelocs/m680x0.def" + break; default: // Nothing to do. break; Index: llvm/lib/Support/Triple.cpp =================================================================== --- llvm/lib/Support/Triple.cpp +++ llvm/lib/Support/Triple.cpp @@ -73,6 +73,7 @@ case ve: return "ve"; case wasm32: return "wasm32"; case wasm64: return "wasm64"; + case m680x0: return "m680x0"; case x86: return "i386"; case x86_64: return "x86_64"; case xcore: return "xcore"; @@ -153,6 +154,7 @@ case ve: return "ve"; case csky: return "csky"; + case m680x0: return "m68k"; } } @@ -322,6 +324,7 @@ .Case("renderscript64", renderscript64) .Case("ve", ve) .Case("csky", csky) + .Case("m680x0", m680x0) .Default(UnknownArch); } @@ -421,6 +424,7 @@ "mips64r6", "mipsn32r6", Triple::mips64) .Cases("mips64el", "mipsn32el", "mipsisa64r6el", "mips64r6el", "mipsn32r6el", Triple::mips64el) + .Cases("m680x0", "m68k", Triple::m680x0) .Case("r600", Triple::r600) .Case("amdgcn", Triple::amdgcn) .Case("riscv32", Triple::riscv32) @@ -690,6 +694,7 @@ case Triple::lanai: case Triple::le32: case Triple::le64: + case Triple::m680x0: case Triple::mips64: case Triple::mips64el: case Triple::mips: @@ -1264,6 +1269,7 @@ case llvm::Triple::le32: case llvm::Triple::mips: case llvm::Triple::mipsel: + case llvm::Triple::m680x0: case llvm::Triple::nvptx: case llvm::Triple::ppc: case llvm::Triple::r600: @@ -1348,6 +1354,7 @@ case Triple::le32: case Triple::mips: case Triple::mipsel: + case Triple::m680x0: case Triple::nvptx: case Triple::ppc: case Triple::r600: @@ -1397,6 +1404,7 @@ case Triple::kalimba: case Triple::lanai: case Triple::msp430: + case Triple::m680x0: case Triple::r600: case Triple::shave: case Triple::sparcel: @@ -1519,6 +1527,7 @@ case Triple::ppc: case Triple::sparcv9: case Triple::systemz: + case Triple::m680x0: // ARM is intentionally unsupported here, changing the architecture would // drop any arch suffixes. Index: llvm/lib/Target/LLVMBuild.txt =================================================================== --- llvm/lib/Target/LLVMBuild.txt +++ llvm/lib/Target/LLVMBuild.txt @@ -35,6 +35,7 @@ SystemZ VE WebAssembly + M680x0 X86 XCore Index: llvm/lib/Target/M680x0/CMakeLists.txt =================================================================== --- /dev/null +++ llvm/lib/Target/M680x0/CMakeLists.txt @@ -0,0 +1,34 @@ +set(LLVM_TARGET_DEFINITIONS M680x0.td) + +tablegen(LLVM M680x0GenRegisterInfo.inc -gen-register-info) +tablegen(LLVM M680x0GenInstrInfo.inc -gen-instr-info) +tablegen(LLVM M680x0GenSubtargetInfo.inc -gen-subtarget) +tablegen(LLVM M680x0GenMCCodeBeads.inc -gen-code-beads) +tablegen(LLVM M680x0GenMCPseudoLowering.inc -gen-pseudo-lowering) +tablegen(LLVM M680x0GenDAGISel.inc -gen-dag-isel) +tablegen(LLVM M680x0GenCallingConv.inc -gen-callingconv) +tablegen(LLVM M680x0GenAsmWriter.inc -gen-asm-writer) + +# M680x0CommonTableGen must be defined +add_public_tablegen_target(M680x0CommonTableGen) + +# M680x0CodeGen should match with LLVMBuild.txt M680x0CodeGen +add_llvm_target(M680x0CodeGen + M680x0AsmPrinter.cpp + M680x0MCInstLower.cpp + M680x0FrameLowering.cpp + M680x0InstrInfo.cpp + M680x0ISelLowering.cpp + M680x0ISelDAGToDAG.cpp + M680x0ExpandPseudo.cpp + M680x0CollapseMOVEMPass.cpp + M680x0MachineFunction.cpp + M680x0RegisterInfo.cpp + M680x0Subtarget.cpp + M680x0TargetObjectFile.cpp + M680x0TargetMachine.cpp +) + +# Should match with "subdirectories = MCTargetDesc TargetInfo" in LLVMBuild.txt +add_subdirectory(TargetInfo) +add_subdirectory(MCTargetDesc) Index: llvm/lib/Target/M680x0/LLVMBuild.txt =================================================================== --- /dev/null +++ llvm/lib/Target/M680x0/LLVMBuild.txt @@ -0,0 +1,39 @@ +;===-- M680x0/LLVMBuild.txt ------------------------------------*- Conf -*--===; +; +; The LLVM Compiler Infrastructure +; +; This file is distributed under the University of Illinois Open Source +; License. See LICENSE.TXT for details. +; +;===------------------------------------------------------------------------===; +; +; This is an LLVMBuild description file for the components in this subdirectory. +; +; For more information on the LLVMBuild system, please see: +; +; http://llvm.org/docs/LLVMBuild.html +; +;===------------------------------------------------------------------------===; + +[common] +subdirectories = MCTargetDesc TargetInfo + +[component_0] +type = TargetGroup +name = M680x0 +parent = Target + +[component_1] +type = Library +name = M680x0CodeGen +parent = M680x0 +required_libraries = + CodeGen Core MC AsmPrinter + M680x0Desc + M680x0Info + SelectionDAG + Support + Analysis + Target + +add_to_library_groups = M680x0 Index: llvm/lib/Target/M680x0/M680x0TargetObjectFile.h =================================================================== --- /dev/null +++ llvm/lib/Target/M680x0/M680x0TargetObjectFile.h @@ -0,0 +1,34 @@ +//===-- M680x0ELFTargetObjectFile.h - M680x0 Object Info ---------*- C++ -====// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file contains declarations for M680x0 ELF object file lowering. +/// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_M680X0_M680X0TARGETOBJECTFILE_H +#define LLVM_LIB_TARGET_M680X0_M680X0TARGETOBJECTFILE_H + +#include "M680x0TargetMachine.h" + +#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" + +namespace llvm { +class M680x0TargetMachine; +class M680x0ELFTargetObjectFile : public TargetLoweringObjectFileELF { + const M680x0TargetMachine *TM; + MCSection *SmallDataSection; + MCSection *SmallBSSSection; + +public: + void Initialize(MCContext &Ctx, const TargetMachine &TM) override; +}; +} // end namespace llvm + +#endif Index: llvm/lib/Target/M680x0/M680x0TargetObjectFile.cpp =================================================================== --- /dev/null +++ llvm/lib/Target/M680x0/M680x0TargetObjectFile.cpp @@ -0,0 +1,49 @@ +//===-- M680x0ELFTargetObjectFile.cpp - M680x0 Object Files -----*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file contains definitions for M680x0 ELF object file lowering. +/// +//===----------------------------------------------------------------------===// + +#include "M680x0TargetObjectFile.h" + +#include "M680x0Subtarget.h" +#include "M680x0TargetMachine.h" + +#include "llvm/BinaryFormat/ELF.h" +#include "llvm/IR/DataLayout.h" +#include "llvm/IR/DerivedTypes.h" +#include "llvm/IR/GlobalVariable.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCSectionELF.h" +#include "llvm/Support/CommandLine.h" +#include "llvm/Target/TargetMachine.h" + +using namespace llvm; + +static cl::opt SSThreshold( + "m680x0-ssection-threshold", cl::Hidden, + cl::desc("Small data and bss section threshold size (default=8)"), + cl::init(8)); + +void M680x0ELFTargetObjectFile::Initialize(MCContext &Ctx, + const TargetMachine &TM) { + TargetLoweringObjectFileELF::Initialize(Ctx, TM); + InitializeELF(TM.Options.UseInitArray); + + this->TM = &static_cast(TM); + + // FIXME #32 do i need them explicitly? + SmallDataSection = getContext().getELFSection( + ".sdata", ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC); + + SmallBSSSection = getContext().getELFSection(".sbss", ELF::SHT_NOBITS, + ELF::SHF_WRITE | ELF::SHF_ALLOC); +} Index: llvm/lib/Target/M680x0/MCTargetDesc/CMakeLists.txt =================================================================== --- /dev/null +++ llvm/lib/Target/M680x0/MCTargetDesc/CMakeLists.txt @@ -0,0 +1,8 @@ +add_llvm_component_library(LLVMM680x0Desc + M680x0AsmBackend.cpp + M680x0MCTargetDesc.cpp + M680x0MCAsmInfo.cpp + M680x0MCCodeEmitter.cpp + M680x0ELFObjectWriter.cpp + M680x0InstPrinter.cpp +) Index: llvm/lib/Target/M680x0/MCTargetDesc/LLVMBuild.txt =================================================================== --- /dev/null +++ llvm/lib/Target/M680x0/MCTargetDesc/LLVMBuild.txt @@ -0,0 +1,23 @@ +;===- ./lib/Target/M680x0/MCTargetDesc/LLVMBuild.txt -------------*- Conf -*--===; +; +; The LLVM Compiler Infrastructure +; +; This file is distributed under the University of Illinois Open Source +; License. See LICENSE.TXT for details. +; +;===------------------------------------------------------------------------===; +; +; This is an LLVMBuild description file for the components in this subdirectory. +; +; For more information on the LLVMBuild system, please see: +; +; http://llvm.org/docs/LLVMBuild.html +; +;===------------------------------------------------------------------------===; + +[component_0] +type = Library +name = M680x0Desc +parent = M680x0 +required_libraries = MC MCDisassembler Support M680x0Info +add_to_library_groups = M680x0 Index: llvm/lib/Target/M680x0/MCTargetDesc/M680x0AsmBackend.cpp =================================================================== --- /dev/null +++ llvm/lib/Target/M680x0/MCTargetDesc/M680x0AsmBackend.cpp @@ -0,0 +1,246 @@ +//===-- M680x0AsmBackend.cpp - M680x0 Assembler Backend ---------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file contains definitions for M680x0 assembler backend. +/// +//===----------------------------------------------------------------------===// + +#include "MCTargetDesc/M680x0BaseInfo.h" +#include "MCTargetDesc/M680x0FixupKinds.h" + +#include "llvm/ADT/StringSwitch.h" +#include "llvm/BinaryFormat/ELF.h" +#include "llvm/BinaryFormat/MachO.h" +#include "llvm/MC/MCAsmBackend.h" +#include "llvm/MC/MCELFObjectWriter.h" +#include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCFixupKindInfo.h" +#include "llvm/MC/MCInst.h" +#include "llvm/MC/MCMachObjectWriter.h" +#include "llvm/MC/MCObjectWriter.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSectionCOFF.h" +#include "llvm/MC/MCSectionELF.h" +#include "llvm/MC/MCSectionMachO.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/TargetRegistry.h" +#include "llvm/Support/raw_ostream.h" + +using namespace llvm; + +namespace { + +class M680x0AsmBackend : public MCAsmBackend { + +public: + M680x0AsmBackend(const Target &T) : MCAsmBackend(support::big) {} + + unsigned getNumFixupKinds() const override { + return llvm::M680x0::NumTargetFixupKinds; + } + + void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, + const MCValue &Target, MutableArrayRef Data, + uint64_t Value, bool IsResolved, + const MCSubtargetInfo *STI) const override { + unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind()); + + assert(Fixup.getOffset() + Size <= Data.size() && "Invalid fixup offset!"); + + // Check that uppper bits are either all zeros or all ones. + // Specifically ignore overflow/underflow as long as the leakage is + // limited to the lower bits. This is to remain compatible with + // other assemblers. + assert(isIntN(Size * 8 + 1, Value) && + "Value does not fit in the Fixup field"); + + // Write in Big Endian + for (unsigned i = 0; i != Size; ++i) + Data[Fixup.getOffset() + i] = uint8_t(Value >> ((Size - i - 1) * 8)); + } + + bool mayNeedRelaxation(const MCInst &Inst, + const MCSubtargetInfo &STI) const override; + + bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, + const MCRelaxableFragment *DF, + const MCAsmLayout &Layout) const override; + + void relaxInstruction(MCInst &Inst, + const MCSubtargetInfo &STI) const override; + + /// Returns the minimum size of a nop in bytes on this target. The assembler + /// will use this to emit excess padding in situations where the padding + /// required for simple alignment would be less than the minimum nop size. + unsigned getMinimumNopSize() const override { return 2; } + + /// Write a sequence of optimal nops to the output, covering \p Count bytes. + /// \return - true on success, false on failure + bool writeNopData(raw_ostream &OS, uint64_t Count) const override; +}; +} // end anonymous namespace + +/// cc—Carry clear GE—Greater than or equal +/// LS—Lower or same PL—Plus +/// CS—Carry set GT—Greater than +/// LT—Less than +/// EQ—Equal HI—Higher +/// MI—Minus VC—Overflow clear +/// LE—Less than or equal +/// NE—Not equal VS—Overflow set +static unsigned getRelaxedOpcodeBranch(const MCInst &Inst) { + unsigned Op = Inst.getOpcode(); + switch (Op) { + default: + return Op; + case M680x0::BRA8: + return M680x0::BRA16; + case M680x0::Bcc8: + return M680x0::Bcc16; + case M680x0::Bls8: + return M680x0::Bls16; + case M680x0::Blt8: + return M680x0::Blt16; + case M680x0::Beq8: + return M680x0::Beq16; + case M680x0::Bmi8: + return M680x0::Bmi16; + case M680x0::Bne8: + return M680x0::Bne16; + case M680x0::Bge8: + return M680x0::Bge16; + case M680x0::Bcs8: + return M680x0::Bcs16; + case M680x0::Bpl8: + return M680x0::Bpl16; + case M680x0::Bgt8: + return M680x0::Bgt16; + case M680x0::Bhi8: + return M680x0::Bhi16; + case M680x0::Bvc8: + return M680x0::Bvc16; + case M680x0::Ble8: + return M680x0::Ble16; + case M680x0::Bvs8: + return M680x0::Bvs16; + } +} + +static unsigned getRelaxedOpcodeArith(const MCInst &Inst) { + unsigned Op = Inst.getOpcode(); + switch (Op) { + default: + return Op; + // NOTE there will be some relaxations for PCD and ARD mem for x20 + } +} + +static unsigned getRelaxedOpcode(const MCInst &Inst) { + unsigned R = getRelaxedOpcodeArith(Inst); + if (R != Inst.getOpcode()) + return R; + return getRelaxedOpcodeBranch(Inst); +} + +bool M680x0AsmBackend::mayNeedRelaxation(const MCInst &Inst, + const MCSubtargetInfo &STI) const { + // Branches can always be relaxed in either mode. + if (getRelaxedOpcodeBranch(Inst) != Inst.getOpcode()) + return true; + + // Check if this instruction is ever relaxable. + if (getRelaxedOpcodeArith(Inst) == Inst.getOpcode()) + return false; + + // Check if the relaxable operand has an expression. For the current set of + // relaxable instructions, the relaxable operand is always the last operand. + // NOTE will change for x20 mem + unsigned RelaxableOp = Inst.getNumOperands() - 1; + if (Inst.getOperand(RelaxableOp).isExpr()) + return true; + + return false; +} + +bool M680x0AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, + uint64_t Value, + const MCRelaxableFragment *DF, + const MCAsmLayout &Layout) const { + // TODO Newer CPU can use 32 bit offsets, so check for this when ready + if (int64_t(Value) != int64_t(int16_t(Value))) { + llvm_unreachable("Cannot relax the instruction, value does not fit"); + } + // Relax if the value is too big for a (signed) i8. This means that byte-wide + // instructions have to matched by default + // + // NOTE + // A branch to the immediately following instruction automatically + // uses the 16-bit displacement format because the 8-bit + // displacement field contains $00 (zero offset). + return Value == 0 || int64_t(Value) != int64_t(int8_t(Value)); +} + +// NOTE Can tblgen help at all here to verify there aren't other instructions +// we can relax? +void M680x0AsmBackend::relaxInstruction(MCInst &Inst, + const MCSubtargetInfo &STI) const { + // The only relaxations M680x0 does is from a 1byte pcrel to a 2byte PCRel. + unsigned RelaxedOp = getRelaxedOpcode(Inst); + + if (RelaxedOp == Inst.getOpcode()) { + SmallString<256> Tmp; + raw_svector_ostream OS(Tmp); + Inst.dump_pretty(OS); + OS << "\n"; + report_fatal_error("unexpected instruction to relax: " + OS.str()); + } + + Inst.setOpcode(RelaxedOp); +} + +bool M680x0AsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const { + // Cannot emit NOP with size being not multiple of 16 bits. + if (Count % 2 != 0) + return false; + + uint64_t NumNops = Count / 2; + for (uint64_t i = 0; i != NumNops; ++i) { + OS << "\x4E\x71"; + } + + return true; +} + +namespace { + +class M680x0ELFAsmBackend : public M680x0AsmBackend { +public: + uint8_t OSABI; + M680x0ELFAsmBackend(const Target &T, uint8_t OSABI) + : M680x0AsmBackend(T), OSABI(OSABI) {} + + std::unique_ptr + createObjectTargetWriter() const override { + return createM680x0ELFObjectWriter(OSABI); + } +}; + +} // end anonymous namespace + +MCAsmBackend *llvm::createM680x0AsmBackend(const Target &T, + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI, + const MCTargetOptions &Options) { + // assert (TheTriple.getEnvironment() == Triple::GNU); + const Triple &TheTriple = STI.getTargetTriple(); + uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); + return new M680x0ELFAsmBackend(T, OSABI); +} Index: llvm/lib/Target/M680x0/MCTargetDesc/M680x0BaseInfo.h =================================================================== --- /dev/null +++ llvm/lib/Target/M680x0/MCTargetDesc/M680x0BaseInfo.h @@ -0,0 +1,349 @@ +//===-- M680x0BaseInfo.h - Top level definitions for M680X0 MC --*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file contains small standalone helper functions and enum definitions +/// for the M680x0 target useful for the compiler back-end and the MC +/// libraries. As such, it deliberately does not include references to LLVM +/// core code gen types, passes, etc.. +/// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_M680X0_MCTARGETDESC_M680X0BASEINFO_H +#define LLVM_LIB_TARGET_M680X0_MCTARGETDESC_M680X0BASEINFO_H + +#include "M680x0MCTargetDesc.h" + +#include "llvm/MC/MCExpr.h" +#include "llvm/Support/DataTypes.h" +#include "llvm/Support/ErrorHandling.h" + +#define GET_INSTRINFO_MI_OPS_INFO +#define GET_INSTRINFO_OPERAND_TYPES_ENUM +#define GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP +#include "M680x0GenInstrInfo.inc" + +namespace llvm { + +namespace M680x0 { + +/// Enums for memory operand decoding. Supports these forms: +/// (d,An) +/// (d,An,Xn) +/// ([bd,An],Xn,od) +/// ([bd,An,Xn],od) +enum { + MemDisp = 0, + MemBase = 1, + MemIndex = 2, // FIXME #3 assumes Scale 1 for now + + MemOuter = 3 +}; + +/// Enums for pc-relative memory operand decoding. Supports these forms: +/// (d,PC) +/// (d,PC,Xn) +/// ([bd,PC],Xn,od) +/// ([bd,PC,Xn],od) +enum { PCRelDisp = 0, PCRelIndex = 1, PCRelOuter = 2 }; +} // namespace M680x0 + +namespace M680x0Beads { +enum { + Ctrl = 0x0, + Bits1 = 0x1, + Bits2 = 0x2, + Bits3 = 0x3, + Bits4 = 0x4, + DAReg = 0x5, + DA = 0x6, + Reg = 0x7, + Disp8 = 0x8, + Imm8 = 0x9, + Imm16 = 0xA, + Imm32 = 0xB, + Imm3 = 0xC, +}; + +// Ctrl payload +enum { + Term = 0x0, + Ignore = 0x1, +}; +} // namespace M680x0Beads + +/// This namespace holds all of the target specific flags that instruction info +/// tracks. +namespace M680x0II { +/// Target Operand Flag enum. +enum TOF { + + MO_NO_FLAG, + + /// On a symbol operand this indicates that the immediate is the absolute + /// address of the symbol. + MO_ABSOLUTE_ADDRESS, + + /// On a symbol operand this indicates that the immediate is the pc-relative + /// address of the symbol. + MO_PC_RELATIVE_ADDRESS, + + /// On a symbol operand this indicates that the immediate is the offset to + /// the GOT entry for the symbol name from the base of the GOT. + /// + /// name@GOT + MO_GOT, + + /// On a symbol operand this indicates that the immediate is the offset to + /// the location of the symbol name from the base of the GOT. + /// + /// name@GOTOFF + MO_GOTOFF, + + /// On a symbol operand this indicates that the immediate is offset to the + /// GOT entry for the symbol name from the current code location. + /// + /// name@GOTPCREL + MO_GOTPCREL, + + /// On a symbol operand this indicates that the immediate is offset to the + /// PLT entry of symbol name from the current code location. + /// + /// name@PLT + MO_PLT, +}; // enum TOF + +// enum { +// //===------------------------------------------------------------------===// +// // Instruction encodings. These are the standard/most common forms for +// // M680x0 instructions. +// // +// +// // Pseudo - This represents an instruction that is a pseudo instruction +// // or one that has not been implemented yet. It is illegal to code +// generate +// // it, but tolerated for intermediate implementation stages. +// Pseudo = 0, +// FormMask = 15 +// }; + +/// Return true if the specified TargetFlag operand is a reference to a stub +/// for a global, not the global itself. +inline static bool isGlobalStubReference(unsigned char TargetFlag) { + switch (TargetFlag) { + default: + return false; + case M680x0II::MO_GOTPCREL: // pc-relative GOT reference. + case M680x0II::MO_GOT: // normal GOT reference. + return true; + } +} + +/// Return True if the specified GlobalValue is a direct reference for a +/// symbol. +inline static bool isDirectGlobalReference(unsigned char Flag) { + switch (Flag) { + default: + return false; + case M680x0II::MO_NO_FLAG: + case M680x0II::MO_ABSOLUTE_ADDRESS: + case M680x0II::MO_PC_RELATIVE_ADDRESS: + return true; + } +} + +/// Return true if the specified global value reference is relative to a 32-bit +/// PIC base (M680x0ISD::GlobalBaseReg). If this is true, the addressing mode +/// has the PIC base register added in. +inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) { + switch (TargetFlag) { + default: + return false; + case M680x0II::MO_GOTOFF: // isPICStyleGOT: local global. + case M680x0II::MO_GOT: // isPICStyleGOT: other global. + return true; + } +} + +/// Return True if the specified GlobalValue requires PC addressing mode. +inline static bool isPCRelGlobalReference(unsigned char Flag) { + switch (Flag) { + default: + return false; + case M680x0II::MO_GOTPCREL: + case M680x0II::MO_PC_RELATIVE_ADDRESS: + return true; + } +} + +/// Return True if the Block is referenced using PC +inline static bool isPCRelBlockReference(unsigned char Flag) { + switch (Flag) { + default: + return false; + case M680x0II::MO_PC_RELATIVE_ADDRESS: + return true; + } +} + +static inline bool isAddressRegister(unsigned RegNo) { + switch (RegNo) { + case M680x0::CCR: + case M680x0::PC: + case M680x0::SR: + default: + llvm_unreachable("Not an Address nor Data register"); + case M680x0::WA0: + case M680x0::WA1: + case M680x0::WA2: + case M680x0::WA3: + case M680x0::WA4: + case M680x0::WA5: + case M680x0::WA6: + case M680x0::WA7: + case M680x0::A0: + case M680x0::A1: + case M680x0::A2: + case M680x0::A3: + case M680x0::A4: + case M680x0::A5: + case M680x0::A6: + // case M680x0::A7: + case M680x0::SP: + return true; + case M680x0::BD0: + case M680x0::BD1: + case M680x0::BD2: + case M680x0::BD3: + case M680x0::BD4: + case M680x0::BD5: + case M680x0::BD6: + case M680x0::BD7: + case M680x0::WD0: + case M680x0::WD1: + case M680x0::WD2: + case M680x0::WD3: + case M680x0::WD4: + case M680x0::WD5: + case M680x0::WD6: + case M680x0::WD7: + case M680x0::D0: + case M680x0::D1: + case M680x0::D2: + case M680x0::D3: + case M680x0::D4: + case M680x0::D5: + case M680x0::D6: + case M680x0::D7: + return false; + } +} + +static inline +bool hasMultiMIOperands(unsigned Op, unsigned LogicalOpIdx) { + return M680x0::getLogicalOperandSize(Op, LogicalOpIdx) > 1; +} + +#if 0 +static inline bool isPCRelOpd(unsigned Opd) { + switch (Opd) { + default: + return false; + case M680x0::MIOpTypes::MxPCD32: + case M680x0::MIOpTypes::MxPCD16: + case M680x0::MIOpTypes::MxPCD8: + case M680x0::MIOpTypes::MxPCI32: + case M680x0::MIOpTypes::MxPCI16: + case M680x0::MIOpTypes::MxPCI8: + case MCOI::OPERAND_PCREL: + return true; + } + return false; +} + +static inline unsigned getDispSize(unsigned Opd) { + switch (Opd) { + default: + return 0; + case M680x0::MIOpTypes::MxAL16: + case M680x0::MIOpTypes::MxAL32: + case M680x0::MIOpTypes::MxAL8: + return 32; + case M680x0::MIOpTypes::MxARID16: + case M680x0::MIOpTypes::MxARID16_TC: + case M680x0::MIOpTypes::MxARID32: + case M680x0::MIOpTypes::MxARID32_TC: + case M680x0::MIOpTypes::MxARID8: + case M680x0::MIOpTypes::MxARID8_TC: + case M680x0::MIOpTypes::MxPCD16: + case M680x0::MIOpTypes::MxPCD32: + case M680x0::MIOpTypes::MxPCD8: + case M680x0::MIOpTypes::MxAS16: + case M680x0::MIOpTypes::MxAS32: + case M680x0::MIOpTypes::MxAS8: + return 16; + case M680x0::MIOpTypes::MxARII16: + case M680x0::MIOpTypes::MxARII16_TC: + case M680x0::MIOpTypes::MxARII32: + case M680x0::MIOpTypes::MxARII32_TC: + case M680x0::MIOpTypes::MxARII8: + case M680x0::MIOpTypes::MxARII8_TC: + case M680x0::MIOpTypes::MxPCI16: + case M680x0::MIOpTypes::MxPCI32: + case M680x0::MIOpTypes::MxPCI8: + return 8; + } + return 8; +} +#endif + +static inline unsigned getMaskedSpillRegister(unsigned order) { + switch (order) { + default: + return 0; + case 0: + return M680x0::D0; + case 1: + return M680x0::D1; + case 2: + return M680x0::D2; + case 3: + return M680x0::D3; + case 4: + return M680x0::D4; + case 5: + return M680x0::D5; + case 6: + return M680x0::D6; + case 7: + return M680x0::D7; + case 8: + return M680x0::A0; + case 9: + return M680x0::A1; + case 10: + return M680x0::A2; + case 11: + return M680x0::A3; + case 12: + return M680x0::A4; + case 13: + return M680x0::A5; + case 14: + return M680x0::A6; + case 15: + return M680x0::A7; + } +} + +} // namespace M680x0II + +} // namespace llvm + +#endif Index: llvm/lib/Target/M680x0/MCTargetDesc/M680x0ELFObjectWriter.cpp =================================================================== --- /dev/null +++ llvm/lib/Target/M680x0/MCTargetDesc/M680x0ELFObjectWriter.cpp @@ -0,0 +1,128 @@ +//===---------- M680x0ELFObjectWriter.cpp - M680x0 ELF Writer ---*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file contains definitions for M680x0 ELF Writers +/// +//===----------------------------------------------------------------------===// + +#include "MCTargetDesc/M680x0FixupKinds.h" +#include "MCTargetDesc/M680x0MCTargetDesc.h" + +#include "llvm/BinaryFormat/ELF.h" +#include "llvm/MC/MCAsmInfo.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCELFObjectWriter.h" +#include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCValue.h" +#include "llvm/Support/ErrorHandling.h" + +using namespace llvm; + +namespace { +class M680x0ELFObjectWriter : public MCELFObjectTargetWriter { +public: + M680x0ELFObjectWriter(uint8_t OSABI); + + ~M680x0ELFObjectWriter() override; + +protected: + unsigned getRelocType(MCContext &Ctx, const MCValue &Target, + const MCFixup &Fixup, bool IsPCRel) const override; +}; +} // namespace + +M680x0ELFObjectWriter::M680x0ELFObjectWriter(uint8_t OSABI) + : MCELFObjectTargetWriter(false, OSABI, ELF::EM_68K, /* RELA */ true) {} + +M680x0ELFObjectWriter::~M680x0ELFObjectWriter() {} + +enum M680x0RelType { RT_32, RT_16, RT_8 }; + +static M680x0RelType +getType(unsigned Kind, MCSymbolRefExpr::VariantKind &Modifier, bool &IsPCRel) { + switch (Kind) { + default: + llvm_unreachable("Unimplemented"); + case FK_Data_4: + case FK_PCRel_4: + return RT_32; + case FK_PCRel_2: + case FK_Data_2: + return RT_16; + case FK_PCRel_1: + case FK_Data_1: + return RT_8; + } +} + +// FIXME #4 Should i split reloc types between pre x20 and the rest? +unsigned M680x0ELFObjectWriter::getRelocType(MCContext &Ctx, + const MCValue &Target, + const MCFixup &Fixup, + bool IsPCRel) const { + MCSymbolRefExpr::VariantKind Modifier = Target.getAccessVariant(); + unsigned Kind = Fixup.getKind(); + M680x0RelType Type = getType(Kind, Modifier, IsPCRel); + switch (Modifier) { + default: + llvm_unreachable("Unimplemented"); + case MCSymbolRefExpr::VK_None: + switch (Type) { + case RT_32: + return IsPCRel ? ELF::R_M680x0_PC32 : ELF::R_M680x0_32; + case RT_16: + return IsPCRel ? ELF::R_M680x0_PC16 : ELF::R_M680x0_16; + case RT_8: + return IsPCRel ? ELF::R_M680x0_PC8 : ELF::R_M680x0_8; + } + // case MCSymbolRefExpr::VK_GOT: + // switch (Type) { + // case RT_32: + // return IsPCRel ? ELF::R_M680x0_GOTPC32 : ELF::R_M680x0_GOT32; + // case RT_16: + // return IsPCRel ? ELF::R_M680x0_GOTPC16 : ELF::R_M680x0_GOT16; + // case RT_8: + // llvm_unreachable("Unimplemented"); + // } + case MCSymbolRefExpr::VK_GOTPCREL: + switch (Type) { + case RT_32: + return ELF::R_M680x0_GOTPCREL32; + case RT_16: + return ELF::R_M680x0_GOTPCREL16; + case RT_8: + return ELF::R_M680x0_GOTPCREL8; + } + case MCSymbolRefExpr::VK_GOTOFF: + assert(!IsPCRel); + switch (Type) { + case RT_32: + return ELF::R_M680x0_GOTOFF32; + case RT_16: + return ELF::R_M680x0_GOTOFF16; + case RT_8: + return ELF::R_M680x0_GOTOFF8; + } + case MCSymbolRefExpr::VK_PLT: + switch (Type) { + case RT_32: + return ELF::R_M680x0_PLT32; + case RT_16: + return ELF::R_M680x0_PLT16; + case RT_8: + return ELF::R_M680x0_PLT8; + } + } +} + +std::unique_ptr +llvm::createM680x0ELFObjectWriter(uint8_t OSABI) { + return std::make_unique(OSABI); +} Index: llvm/lib/Target/M680x0/MCTargetDesc/M680x0FixupKinds.h =================================================================== --- /dev/null +++ llvm/lib/Target/M680x0/MCTargetDesc/M680x0FixupKinds.h @@ -0,0 +1,65 @@ +//===-- M680x0FixupKinds.h - M680x0 Specific Fixup Entries ------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file contains M680x0 specific fixup entries. +/// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_M680x0_MCTARGETDESC_M680x0FIXUPKINDS_H +#define LLVM_LIB_TARGET_M680x0_MCTARGETDESC_M680x0FIXUPKINDS_H + +#include "llvm/MC/MCFixup.h" + +namespace llvm { +namespace M680x0 { +enum Fixups { + // Marker + LastTargetFixupKind, + NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind +}; +} + +static inline unsigned getFixupKindLog2Size(unsigned Kind) { + switch (Kind) { + default: + llvm_unreachable("invalid fixup kind!"); + case FK_PCRel_1: + case FK_SecRel_1: + case FK_Data_1: + return 0; + case FK_PCRel_2: + case FK_SecRel_2: + case FK_Data_2: + return 1; + case FK_PCRel_4: + case FK_SecRel_4: + case FK_Data_4: + return 2; + } +} + +static inline MCFixupKind getFixupForSize(unsigned Size, bool isPCRel) { + switch (Size) { + default: + llvm_unreachable("Invalid generic fixup size!"); + case 8: + return isPCRel ? FK_PCRel_1 : FK_Data_1; + case 16: + return isPCRel ? FK_PCRel_2 : FK_Data_2; + case 32: + return isPCRel ? FK_PCRel_4 : FK_Data_4; + case 64: + return isPCRel ? FK_PCRel_8 : FK_Data_8; + } +} + +} // namespace llvm + +#endif Index: llvm/lib/Target/M680x0/MCTargetDesc/M680x0InstPrinter.h =================================================================== --- /dev/null +++ llvm/lib/Target/M680x0/MCTargetDesc/M680x0InstPrinter.h @@ -0,0 +1,168 @@ +//===-- M680x0InstPrinter.h - Convert M680x0 MCInst to asm ------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file contains declarations for an M680x0 MCInst printer. +/// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_M680X0_INSTPRINTER_M680X0INSTPRINTER_H +#define LLVM_LIB_TARGET_M680X0_INSTPRINTER_M680X0INSTPRINTER_H + +#include "llvm/MC/MCInstPrinter.h" + +namespace llvm { + +class TargetMachine; + +class M680x0InstPrinter : public MCInstPrinter { +public: + M680x0InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, + const MCRegisterInfo &MRI) + : MCInstPrinter(MAI, MII, MRI) {} + + // Autogenerated by tblgen. + void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O); + static const char *getRegisterName(unsigned RegNo); + + void printRegName(raw_ostream &OS, unsigned RegNo) const override; + void printInst(const MCInst *MI, uint64_t Address, StringRef Annot, + const MCSubtargetInfo &STI, raw_ostream &O) override; + + bool printAliasInstr(const MCInst *MI, uint64_t Address, raw_ostream &OS); + void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, + unsigned PrintMethodIdx, raw_ostream &O); + +private: + void printOperand(const MCInst *MI, unsigned opNum, raw_ostream &O); + void printImmediate(const MCInst *MI, int opNum, raw_ostream &O); + /// Print register mask for MOVEM instruction in order D0-D7,A0-A7 + void printMoveMask(const MCInst *MI, int opNum, raw_ostream &O); + /// Print register mask for MOVEM instruction in order A7-A0,D7-D0 + void printMoveMaskR(const MCInst *MI, int opNum, raw_ostream &O); + void printDisp(const MCInst *MI, int opNum, raw_ostream &O); + void printARIMem(const MCInst *MI, int opNum, raw_ostream &O); + void printARIPIMem(const MCInst *MI, int opNum, raw_ostream &O); + void printARIPDMem(const MCInst *MI, int opNum, raw_ostream &O); + void printARIDMem(const MCInst *MI, int opNum, raw_ostream &O); + void printARIIMem(const MCInst *MI, int opNum, raw_ostream &O); + void printAbsMem(const MCInst *MI, int opNum, raw_ostream &O); + void printPCDMem(const MCInst *MI, uint64_t Address, + int opNum, raw_ostream &O); + void printPCIMem(const MCInst *MI, uint64_t Address, + int opNum, raw_ostream &O); + + //===----------------------------------------------------------------------===// + // Specializations + //===----------------------------------------------------------------------===// + // + void printPCRelImm(const MCInst *MI, uint64_t Address, + int opNum, raw_ostream &O) { + printOperand(MI, opNum, O); + } + + void printARI8Mem(const MCInst *MI, int opNum, raw_ostream &O) { + printARIMem(MI, opNum, O); + } + void printARI16Mem(const MCInst *MI, int opNum, raw_ostream &O) { + printARIMem(MI, opNum, O); + } + void printARI32Mem(const MCInst *MI, int opNum, raw_ostream &O) { + printARIMem(MI, opNum, O); + } + + void printARIPI8Mem(const MCInst *MI, int opNum, raw_ostream &O) { + printARIPIMem(MI, opNum, O); + } + void printARIPI16Mem(const MCInst *MI, int opNum, raw_ostream &O) { + printARIPIMem(MI, opNum, O); + } + void printARIPI32Mem(const MCInst *MI, int opNum, raw_ostream &O) { + printARIPIMem(MI, opNum, O); + } + + void printARIPD8Mem(const MCInst *MI, int opNum, raw_ostream &O) { + printARIPDMem(MI, opNum, O); + } + void printARIPD16Mem(const MCInst *MI, int opNum, raw_ostream &O) { + printARIPDMem(MI, opNum, O); + } + void printARIPD32Mem(const MCInst *MI, int opNum, raw_ostream &O) { + printARIPDMem(MI, opNum, O); + } + + void printARID8Mem(const MCInst *MI, int opNum, raw_ostream &O) { + printARIDMem(MI, opNum, O); + } + void printARID16Mem(const MCInst *MI, int opNum, raw_ostream &O) { + printARIDMem(MI, opNum, O); + } + void printARID32Mem(const MCInst *MI, int opNum, raw_ostream &O) { + printARIDMem(MI, opNum, O); + } + + void printARII8Mem(const MCInst *MI, int opNum, raw_ostream &O) { + printARIIMem(MI, opNum, O); + } + void printARII16Mem(const MCInst *MI, int opNum, raw_ostream &O) { + printARIIMem(MI, opNum, O); + } + void printARII32Mem(const MCInst *MI, int opNum, raw_ostream &O) { + printARIIMem(MI, opNum, O); + } + + void printAS8Mem(const MCInst *MI, int opNum, raw_ostream &O) { + printAbsMem(MI, opNum, O); + } + void printAS16Mem(const MCInst *MI, int opNum, raw_ostream &O) { + printAbsMem(MI, opNum, O); + } + void printAS32Mem(const MCInst *MI, int opNum, raw_ostream &O) { + printAbsMem(MI, opNum, O); + } + + void printAL8Mem(const MCInst *MI, int opNum, raw_ostream &O) { + printAbsMem(MI, opNum, O); + } + void printAL16Mem(const MCInst *MI, int opNum, raw_ostream &O) { + printAbsMem(MI, opNum, O); + } + void printAL32Mem(const MCInst *MI, int opNum, raw_ostream &O) { + printAbsMem(MI, opNum, O); + } + + void printPCD8Mem(const MCInst *MI, uint64_t Address, + int opNum, raw_ostream &O) { + printPCDMem(MI, Address, opNum, O); + } + void printPCD16Mem(const MCInst *MI, uint64_t Address, + int opNum, raw_ostream &O) { + printPCDMem(MI, Address, opNum, O); + } + void printPCD32Mem(const MCInst *MI, uint64_t Address, + int opNum, raw_ostream &O) { + printPCDMem(MI, Address, opNum, O); + } + + void printPCI8Mem(const MCInst *MI, uint64_t Address, + int opNum, raw_ostream &O) { + printPCIMem(MI, Address, opNum, O); + } + void printPCI16Mem(const MCInst *MI, uint64_t Address, + int opNum, raw_ostream &O) { + printPCIMem(MI, Address, opNum, O); + } + void printPCI32Mem(const MCInst *MI, uint64_t Address, + int opNum, raw_ostream &O) { + printPCIMem(MI, Address, opNum, O); + } +}; +} // end namespace llvm + +#endif Index: llvm/lib/Target/M680x0/MCTargetDesc/M680x0InstPrinter.cpp =================================================================== --- /dev/null +++ llvm/lib/Target/M680x0/MCTargetDesc/M680x0InstPrinter.cpp @@ -0,0 +1,197 @@ +//===-- M680x0InstPrinter.cpp - Convert M680x0 MCInst to asm ----*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file contains definitions for an M680x0 MCInst printer. +/// +//===----------------------------------------------------------------------===// + +// TODO #33 finish printer, it does not conform to Motorola asm at all + +#include "M680x0InstPrinter.h" + +#include "M680x0InstrInfo.h" + +#include "llvm/ADT/StringExtras.h" +#include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCInst.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCSymbol.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/raw_ostream.h" + +using namespace llvm; + +#define DEBUG_TYPE "asm-printer" + +#define PRINT_ALIAS_INSTR +#include "M680x0GenAsmWriter.inc" + +void M680x0InstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { + OS << "%" << StringRef(getRegisterName(RegNo)); +} + +void M680x0InstPrinter::printInst(const MCInst *MI, uint64_t Address, + StringRef Annot, const MCSubtargetInfo &STI, + raw_ostream &O) { + if (!printAliasInstr(MI, Address, O)) { + printInstruction(MI, Address, O); + } + printAnnotation(O, Annot); +} + +void M680x0InstPrinter::printOperand(const MCInst *MI, unsigned OpNo, + raw_ostream &O) { + const MCOperand &MO = MI->getOperand(OpNo); + if (MO.isReg()) { + printRegName(O, MO.getReg()); + return; + } + + if (MO.isImm()) { + printImmediate(MI, OpNo, O); + return; + } + + assert(MO.isExpr() && "Unknown operand kind in printOperand"); + MO.getExpr()->print(O, &MAI); +} + +void M680x0InstPrinter::printImmediate(const MCInst *MI, int opNum, + raw_ostream &O) { + const MCOperand &MO = MI->getOperand(opNum); + if (MO.isImm()) { + O << '#' << MO.getImm(); + } else if (MO.isExpr()) { + O << '#'; + MO.getExpr()->print(O, &MAI); + } else { + llvm_unreachable("Unknown immediate kind"); + } +} + +// +void M680x0InstPrinter::printMoveMask(const MCInst *MI, int opNum, + raw_ostream &O) { + unsigned Mask = MI->getOperand(opNum).getImm(); + assert((Mask & 0xFFFF) == Mask); + + unsigned HalfMask, Reg; + for (int s = 0; s < 8; s += 8) { + HalfMask = Mask >> s; + if (HalfMask && s != 0) { + O << ','; + } + + for (int i = 0; HalfMask; ++i) { + if ((HalfMask >> i) & 0x01) { + HalfMask ^= 1 << i; + Reg = M680x0II::getMaskedSpillRegister(i + s); + printRegName(O, Reg); + + int j = i; + while ((HalfMask >> (j + 1)) & 0x01) { + HalfMask ^= 1 << ++j; + } + + if (j != i) { + O << '-'; + Reg = M680x0II::getMaskedSpillRegister(j + s); + printRegName(O, Reg); + } + + i = j; + + if (HalfMask) { + O << ','; + } + } else { + } + } + } +} + +void M680x0InstPrinter::printDisp(const MCInst *MI, int opNum, raw_ostream &O) { + const MCOperand &Op = MI->getOperand(opNum); + if (Op.isImm()) { + O << Op.getImm(); + return; + } + assert(Op.isExpr() && "Unknown operand kind in printOperand"); + Op.getExpr()->print(O, &MAI); +} + +void M680x0InstPrinter::printARIMem(const MCInst *MI, int opNum, + raw_ostream &O) { + O << '('; + printOperand(MI, opNum, O); + O << ')'; +} + +void M680x0InstPrinter::printARIPIMem(const MCInst *MI, int opNum, + raw_ostream &O) { + O << "("; + printOperand(MI, opNum, O); + O << ")+"; +} + +void M680x0InstPrinter::printARIPDMem(const MCInst *MI, int opNum, + raw_ostream &O) { + O << "-("; + printOperand(MI, opNum, O); + O << ")"; +} + +void M680x0InstPrinter::printARIDMem(const MCInst *MI, int opNum, + raw_ostream &O) { + O << '('; + printDisp(MI, opNum + M680x0::MemDisp, O); + O << ','; + printOperand(MI, opNum + M680x0::MemBase, O); + O << ')'; +} + +void M680x0InstPrinter::printARIIMem(const MCInst *MI, int opNum, + raw_ostream &O) { + O << '('; + printDisp(MI, opNum + M680x0::MemDisp, O); + O << ','; + printOperand(MI, opNum + M680x0::MemBase, O); + O << ','; + printOperand(MI, opNum + M680x0::MemIndex, O); + O << ')'; +} + +// NOTE forcing (W,L) size available since M68020 only +void M680x0InstPrinter::printAbsMem(const MCInst *MI, int opNum, + raw_ostream &O) { + const MCOperand &MO = MI->getOperand(opNum); + if (MO.isImm()) { + // ??? Print it in hex? + O << (unsigned int)MO.getImm(); + } else { + printOperand(MI, opNum, O); + } +} + +void M680x0InstPrinter::printPCDMem(const MCInst *MI, uint64_t Address, + int opNum, raw_ostream &O) { + O << '('; + printDisp(MI, opNum + M680x0::PCRelDisp, O); + O << ",%pc)"; +} + +void M680x0InstPrinter::printPCIMem(const MCInst *MI, uint64_t Address, + int opNum, raw_ostream &O) { + O << '('; + printDisp(MI, opNum + M680x0::PCRelDisp, O); + O << ",%pc,"; + printOperand(MI, opNum + M680x0::PCRelIndex, O); + O << ')'; +} Index: llvm/lib/Target/M680x0/MCTargetDesc/M680x0MCAsmInfo.h =================================================================== --- /dev/null +++ llvm/lib/Target/M680x0/MCTargetDesc/M680x0MCAsmInfo.h @@ -0,0 +1,32 @@ +//===-- M680x0MCAsmInfo.h - M680x0 Asm Info --------------------*- C++ -*--===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file contains the declarations of the M680x0 MCAsmInfo properties. +/// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_M680X0_MCTARGETDESC_M680X0MCASMINFO_H +#define LLVM_LIB_TARGET_M680X0_MCTARGETDESC_M680X0MCASMINFO_H + +#include "llvm/MC/MCAsmInfoELF.h" + +namespace llvm { + class Triple; + + class M680x0ELFMCAsmInfo : public MCAsmInfoELF { + void anchor() override; + + public: + explicit M680x0ELFMCAsmInfo(const Triple &Triple); + }; + +} // namespace llvm + +#endif Index: llvm/lib/Target/M680x0/MCTargetDesc/M680x0MCAsmInfo.cpp =================================================================== --- /dev/null +++ llvm/lib/Target/M680x0/MCTargetDesc/M680x0MCAsmInfo.cpp @@ -0,0 +1,43 @@ +//===-- M680x0MCAsmInfo.cpp - M680x0 Asm Properties -------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file contains the definitions of the M680x0 MCAsmInfo properties. +/// +//===----------------------------------------------------------------------===// + +#include "M680x0MCAsmInfo.h" + +#include "llvm/ADT/Triple.h" + +using namespace llvm; + +void M680x0ELFMCAsmInfo::anchor() {} + +// TODO get back to it when it comes to printing +M680x0ELFMCAsmInfo::M680x0ELFMCAsmInfo(const Triple &T) { + CodePointerSize = 4; + CalleeSaveStackSlotSize = 4; + + IsLittleEndian = false; + + TextAlignFillValue = 0x90; + + // Debug Information + SupportsDebugInformation = true; + + // Exceptions handling + ExceptionsType = ExceptionHandling::DwarfCFI; + + // Always enable the integrated assembler by default. + // Clang also enabled it when the OS is Solaris but that is redundant here. + UseIntegratedAssembler = true; + + CommentString = ";"; +} Index: llvm/lib/Target/M680x0/MCTargetDesc/M680x0MCCodeEmitter.cpp =================================================================== --- /dev/null +++ llvm/lib/Target/M680x0/MCTargetDesc/M680x0MCCodeEmitter.cpp @@ -0,0 +1,418 @@ +//===-- M680x0MCCodeEmitter.cpp - Convert M680x0 code emitter ---*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file contains defintions for M680x0 code emitter. +/// +//===----------------------------------------------------------------------===// + +#include "M680x0RegisterInfo.h" + +#include "MCTargetDesc/M680x0BaseInfo.h" +#include "MCTargetDesc/M680x0FixupKinds.h" +#include "MCTargetDesc/M680x0MCTargetDesc.h" + +#include "llvm/MC/MCCodeEmitter.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCInst.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCSymbol.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/raw_ostream.h" + +using namespace llvm; + +#define DEBUG_TYPE "m680x0-mccodeemitter" + +namespace { +class M680x0MCCodeEmitter : public MCCodeEmitter { + M680x0MCCodeEmitter(const M680x0MCCodeEmitter &) = delete; + void operator=(const M680x0MCCodeEmitter &) = delete; + const MCInstrInfo &MCII; + MCContext &Ctx; + +public: + M680x0MCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx) + : MCII(mcii), Ctx(ctx) {} + + ~M680x0MCCodeEmitter() override {} + + // TableGen'erated function + const uint8_t *getGenInstrBeads(const MCInst &MI) const; + + unsigned EncodeBits(unsigned ThisByte, uint8_t Bead, const MCInst &MI, + const MCInstrDesc &Desc, uint64_t &Buffer, + unsigned Offset, SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + + unsigned EncodeReg(unsigned ThisByte, uint8_t Bead, const MCInst &MI, + const MCInstrDesc &Desc, uint64_t &Buffer, unsigned Offset, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + + unsigned EncodeImm(unsigned ThisByte, uint8_t Bead, const MCInst &MI, + const MCInstrDesc &Desc, uint64_t &Buffer, unsigned Offset, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + + void encodeInstruction(const MCInst &MI, raw_ostream &OS, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const override; +}; + +} // end anonymous namespace + +unsigned M680x0MCCodeEmitter::EncodeBits(unsigned ThisByte, uint8_t Bead, + const MCInst &MI, + const MCInstrDesc &Desc, + uint64_t &Buffer, unsigned Offset, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + unsigned Num = 0; + switch (Bead & 0xF) { + case M680x0Beads::Bits1: + Num = 1; + break; + case M680x0Beads::Bits2: + Num = 2; + break; + case M680x0Beads::Bits3: + Num = 3; + break; + case M680x0Beads::Bits4: + Num = 4; + break; + } + unsigned char Val = (Bead & 0xF0) >> 4; + + LLVM_DEBUG(dbgs() << "\tEncodeBits" + << " Num: " << Num << " Val: 0x"); + LLVM_DEBUG(dbgs().write_hex(Val) << "\n"); + + Buffer |= (Val << Offset); + + return Num; +} + +unsigned M680x0MCCodeEmitter::EncodeReg(unsigned ThisByte, uint8_t Bead, + const MCInst &MI, + const MCInstrDesc &Desc, + uint64_t &Buffer, unsigned Offset, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + bool DA, Reg; + switch (Bead & 0xF) { + case M680x0Beads::DAReg: + Reg = true; + DA = true; + break; + case M680x0Beads::DA: + Reg = false; + DA = true; + break; + case M680x0Beads::Reg: + Reg = true; + DA = false; + break; + } + + unsigned Op = (Bead & 0x70) >> 4; + bool Alt = (Bead & 0x80); + LLVM_DEBUG(dbgs() << "\tEncodeReg" + << " Op: " << Op << ", DA: " << DA << ", Reg: " << Reg + << ", Alt: " << Alt << "\n"); + + auto MIOpIdx = M680x0::getLogicalOperandIdx(MI.getOpcode(), Op); + bool isPCRel = Desc.OpInfo[MIOpIdx].OperandType == MCOI::OPERAND_PCREL; + + MCOperand MCO; + if (M680x0II::hasMultiMIOperands(MI.getOpcode(), Op)) { + if (isPCRel) { + assert(Alt && + "PCRel addresses use Alt bead register encoding by default"); + MCO = MI.getOperand(MIOpIdx + M680x0::PCRelIndex); + } else { + MCO = + MI.getOperand(MIOpIdx + (Alt ? M680x0::MemIndex : M680x0::MemBase)); + } + } else { + assert(!Alt && "You cannot use Alt register with a simple operand"); + MCO = MI.getOperand(MIOpIdx); + } + + unsigned RegNum = MCO.getReg(); + auto RI = Ctx.getRegisterInfo(); + + unsigned Written = 0; + if (Reg) { + uint32_t Val = RI->getEncodingValue(RegNum); + Buffer |= Val << Offset; + Offset += 3; + Written += 3; + } + + if (DA) { + Buffer |= (char)M680x0II::isAddressRegister(RegNum) << Offset; + Written++; + } + + return Written; +} +/// Checks if an unsigned integer fits into the given bit width. non-templated +/// version +constexpr static inline bool uintDoesFit(unsigned N, uint64_t x) { + return N >= 64 || x <= (UINT64_MAX >> (64 - N)); +} + +/// Checks if an integer fits into the given bit width. non-templated version +constexpr static inline bool intDoesFit(unsigned N, int64_t x) { + return N >= 64 || + (-(INT64_C(1) << (N - 1)) <= x && x < (INT64_C(1) << (N - 1))); +} + +static unsigned EmitConstant(uint64_t Val, unsigned Size, unsigned Pad, + uint64_t &Buffer, unsigned Offset) { + // assert (Size && (Size == 8 || Size == 16 || Size == 32)); + assert(Size + Offset <= 64 && "Value does not fit"); + assert(uintDoesFit(Size, Val)); + + // Pad the instruction with zeros if any + // FIXME #5 Actually emit zeros, since there might be trash in the buffer. + Size += Pad; + + // Writing Value in host's endianness + Buffer |= Val << Offset; + return Size; +} + +unsigned M680x0MCCodeEmitter::EncodeImm(unsigned ThisByte, uint8_t Bead, + const MCInst &MI, + const MCInstrDesc &Desc, + uint64_t &Buffer, unsigned Offset, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + unsigned ThisWord = ThisByte / 2; + unsigned Size = 0; + unsigned Pad = 0; + unsigned FixOffset = 0; + int64_t Addendum = 0; + bool NoExpr = false; + + unsigned Type = Bead & 0xF; + unsigned Op = (Bead & 0x70) >> 4; + bool Alt = (Bead & 0x80); + + auto MIOpIdx = M680x0::getLogicalOperandIdx(MI.getOpcode(), Op); + bool isPCRel = Desc.OpInfo[MIOpIdx].OperandType == MCOI::OPERAND_PCREL; + + // The PC value upon instruction reading of a short jump will point to the + // next instruction, thus we need to compensate 2 bytes, which is the diff + // between the patch point and the PC. + if (isPCRel && ThisWord == 0) { + Addendum -= 2; + } + + switch (Type) { + // ??? what happens if it is not byte aligned + // ??? is it even possible + case M680x0Beads::Disp8: + Size = 8; + Pad = 0; + FixOffset = ThisByte + 1; + Addendum += 1; + break; + case M680x0Beads::Imm8: + Size = 8; + Pad = 8; + FixOffset = ThisByte; + break; + case M680x0Beads::Imm16: + Size = 16; + Pad = 0; + FixOffset = ThisByte; + break; + case M680x0Beads::Imm32: + Size = 32; + Pad = 0; + FixOffset = ThisByte; + break; + case M680x0Beads::Imm3: + Size = 3; + Pad = 0; + NoExpr = true; + break; + } + + LLVM_DEBUG(dbgs() << "\tEncodeImm" + << " Op: " << Op << ", Size: " << Size << ", Alt: " << Alt + << "\n"); + + MCOperand MCO; + if (M680x0II::hasMultiMIOperands(MI.getOpcode(), Op)) { + + if (isPCRel) { + assert(!Alt && "You cannot use ALT operand with PCRel"); + MCO = MI.getOperand(MIOpIdx + M680x0::PCRelDisp); + } else { + MCO = + MI.getOperand(MIOpIdx + (Alt ? M680x0::MemOuter : M680x0::MemDisp)); + } + + if (MCO.isExpr()) { + assert(!NoExpr && "Cannot use expression here"); + const MCExpr *Expr = MCO.getExpr(); + + // This only makes sense for PCRel instructions since PC points to the + // extension word and Disp8 for example is right justified and requires + // correction. E.g. R_M680x0_PC32 is calculated as S + A - P, P for Disp8 + // will be EXTENSION_WORD + 1 thus we need to have A equal to 1 to + // compensate. + // TODO count extension words + if (isPCRel && Addendum != 0) { + Expr = MCBinaryExpr::createAdd( + Expr, MCConstantExpr::create(Addendum, Ctx), Ctx); + } + + Fixups.push_back(MCFixup::create( + FixOffset, Expr, getFixupForSize(Size, isPCRel), MI.getLoc())); + // Write zeros + return EmitConstant(0, Size, Pad, Buffer, Offset); + } + + } else { + // assert (!Alt && "You cannot use Alt immediate with a simple operand"); + MCO = MI.getOperand(MIOpIdx); + if (MCO.isExpr()) { + assert(!NoExpr && "Cannot use expression here"); + const MCExpr *Expr = MCO.getExpr(); + + if (Addendum != 0) { + Expr = MCBinaryExpr::createAdd( + Expr, MCConstantExpr::create(Addendum, Ctx), Ctx); + } + + Fixups.push_back(MCFixup::create( + FixOffset, Expr, getFixupForSize(Size, isPCRel), MI.getLoc())); + // Write zeros + return EmitConstant(0, Size, Pad, Buffer, Offset); + } + } + + int64_t I = MCO.getImm(); + + // Store 8 as 0, thus making range 1-8 + if (Type == M680x0Beads::Imm3 && Alt) { + assert(I && "Cannot encode Alt Imm3 zero value"); + I %= 8; + } else { + assert(intDoesFit(Size, I)); + } + + uint64_t Imm = I; + + // 32 bit Imm requires HI16 first then LO16 + if (Size == 32) { + Offset += EmitConstant((Imm >> 16) & 0xFFFF, 16, Pad, Buffer, Offset); + EmitConstant(Imm & 0xFFFF, 16, Pad, Buffer, Offset); + return Size; + } + + return EmitConstant(Imm & (UINT64_MAX >> (64 - Size)), Size, Pad, Buffer, + Offset); +} + +#include "M680x0GenMCCodeBeads.inc" + +void M680x0MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + unsigned Opcode = MI.getOpcode(); + const MCInstrDesc &Desc = MCII.get(Opcode); + // uint64_t TSFlags = Desc.TSFlags; + + LLVM_DEBUG(dbgs() << "EncodeInstruction: " << MCII.getName(Opcode) << "(" + << Opcode << ")\n"); + + const uint8_t *Beads = getGenInstrBeads(MI); + if (!*Beads) { + llvm_unreachable("*** Instruction does not have Beads defined"); + } + + uint64_t Buffer = 0; + unsigned Offset = 0; + unsigned ThisByte = 0; + + while (*Beads) { + uint8_t Bead = *Beads; + Beads++; + + // Check for control beads + if (!(Bead & 0xF)) { + switch (Bead >> 4) { + case M680x0Beads::Ignore: + continue; + } + } + + switch (Bead & 0xF) { + default: + llvm_unreachable("Unknown Bead code"); + break; + case M680x0Beads::Bits1: + case M680x0Beads::Bits2: + case M680x0Beads::Bits3: + case M680x0Beads::Bits4: + Offset += + EncodeBits(ThisByte, Bead, MI, Desc, Buffer, Offset, Fixups, STI); + break; + case M680x0Beads::DAReg: + case M680x0Beads::DA: + case M680x0Beads::Reg: + Offset += + EncodeReg(ThisByte, Bead, MI, Desc, Buffer, Offset, Fixups, STI); + break; + case M680x0Beads::Disp8: + case M680x0Beads::Imm8: + case M680x0Beads::Imm16: + case M680x0Beads::Imm32: + case M680x0Beads::Imm3: + Offset += + EncodeImm(ThisByte, Bead, MI, Desc, Buffer, Offset, Fixups, STI); + break; + } + + // Since M680x0 is Big Endian we need to rotate each instruction word + while (Offset / 16) { + OS.write((char)((Buffer >> 8) & 0xFF)); + OS.write((char)((Buffer >> 0) & 0xFF)); + Buffer >>= 16; + Offset -= 16; + ThisByte += 2; + } + } + + // while (Offset >= 8) { + // OS.write((char)(Buffer & 0xFF)); + // Buffer >>= 8; + // Offset -= 8; + // ThisByte++; + // } + + assert(Offset == 0 && "M680x0 Instructions are % 2 bytes"); + assert((ThisByte && !(ThisByte % 2)) && "M680x0 Instructions are % 2 bytes"); +} + +MCCodeEmitter *llvm::createM680x0MCCodeEmitter(const MCInstrInfo &MCII, + const MCRegisterInfo &MRI, + MCContext &Ctx) { + return new M680x0MCCodeEmitter(MCII, Ctx); +} Index: llvm/lib/Target/M680x0/MCTargetDesc/M680x0MCTargetDesc.h =================================================================== --- /dev/null +++ llvm/lib/Target/M680x0/MCTargetDesc/M680x0MCTargetDesc.h @@ -0,0 +1,66 @@ +//===-- M680x0MCTargetDesc.h - M680x0 Target Descriptions -------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file provides M680x0 specific target descriptions. +/// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_M680X0_MCTARGETDESC_M680X0MCTARGETDESC_H +#define LLVM_LIB_TARGET_M680X0_MCTARGETDESC_M680X0MCTARGETDESC_H + +#include "llvm/MC/MCInstrDesc.h" +#include "llvm/MC/MCObjectWriter.h" +#include "llvm/Support/DataTypes.h" + +namespace llvm { +class MCAsmBackend; +class MCCodeEmitter; +class MCContext; +class MCInstrInfo; +class MCRegisterInfo; +class MCSubtargetInfo; +class MCRelocationInfo; +class MCTargetOptions; +class Target; +class Triple; +class StringRef; +class raw_ostream; +class raw_pwrite_stream; + +extern Target TheM680x0Target; + +MCAsmBackend *createM680x0AsmBackend(const Target &T, + const MCSubtargetInfo &STI, + const MCRegisterInfo &MRI, + const MCTargetOptions &Options); + +MCCodeEmitter *createM680x0MCCodeEmitter(const MCInstrInfo &MCII, + const MCRegisterInfo &MRI, + MCContext &Ctx); + +/// Construct an M680x0 ELF object writer. +std::unique_ptr +createM680x0ELFObjectWriter(uint8_t OSABI); + +} // namespace llvm + +// Defines symbolic names for M680x0 registers. This defines a mapping from +// register name to register number. +#define GET_REGINFO_ENUM +#include "M680x0GenRegisterInfo.inc" + +// Defines symbolic names for the M680x0 instructions. +#define GET_INSTRINFO_ENUM +#include "M680x0GenInstrInfo.inc" + +#define GET_SUBTARGETINFO_ENUM +#include "M680x0GenSubtargetInfo.inc" + +#endif Index: llvm/lib/Target/M680x0/MCTargetDesc/M680x0MCTargetDesc.cpp =================================================================== --- /dev/null +++ llvm/lib/Target/M680x0/MCTargetDesc/M680x0MCTargetDesc.cpp @@ -0,0 +1,137 @@ +//===-- M680x0MCTargetDesc.cpp - M680x0 Target Descriptions -----*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file provides M680x0 target specific descriptions. +/// +//===----------------------------------------------------------------------===// + +#include "M680x0MCTargetDesc.h" + +#include "M680x0MCAsmInfo.h" + +#include "M680x0InstPrinter.h" + +#include "llvm/MC/MCELFStreamer.h" +#include "llvm/MC/MCInstPrinter.h" +#include "llvm/MC/MCInstrInfo.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCSymbol.h" +#include "llvm/MC/MachineLocation.h" +#include "llvm/Support/CommandLine.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/FormattedStream.h" +#include "llvm/Support/TargetRegistry.h" + +using namespace llvm; + +#define GET_INSTRINFO_MC_DESC +#include "M680x0GenInstrInfo.inc" + +#define GET_SUBTARGETINFO_MC_DESC +#include "M680x0GenSubtargetInfo.inc" + +#define GET_REGINFO_MC_DESC +#include "M680x0GenRegisterInfo.inc" + +static StringRef ParseM680x0Triple(const Triple &TT, StringRef CPU) { + std::string FS = ""; + return FS; +} + +static MCInstrInfo *createM680x0MCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitM680x0MCInstrInfo(X); // defined in M680x0GenInstrInfo.inc + return X; +} + +static MCRegisterInfo *createM680x0MCRegisterInfo(const Triple &TT) { + MCRegisterInfo *X = new MCRegisterInfo(); + InitM680x0MCRegisterInfo(X, llvm::M680x0::A0, 0, 0, llvm::M680x0::PC); + return X; +} + +static MCSubtargetInfo * +createM680x0MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { + auto ArchFS = ParseM680x0Triple(TT, CPU); + if (!FS.empty()) { + if (!ArchFS.empty()) { + ArchFS = (ArchFS + "," + FS).getSingleStringRef(); + } else { + ArchFS = FS; + } + } + return createM680x0MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/CPU, ArchFS); +} + +static MCAsmInfo *createM680x0MCAsmInfo(const MCRegisterInfo &MRI, + const Triple &TT, + const MCTargetOptions& TO) { + MCAsmInfo *MAI = new M680x0ELFMCAsmInfo(TT); + + // Initialize initial frame state. + // Calculate amount of bytes used for return address storing + int stackGrowth = -4; + + // Initial state of the frame pointer is SP+stackGrowth. + MCCFIInstruction Inst = MCCFIInstruction::cfiDefCfa( + nullptr, MRI.getDwarfRegNum(llvm::M680x0::SP, true), -stackGrowth); + MAI->addInitialFrameState(Inst); + + //??? Do i need this? + // // Add return address to move list + // MCCFIInstruction Inst2 = MCCFIInstruction::createOffset( + // nullptr, MRI.getDwarfRegNum(M680x0::PC, true), stackGrowth); + // MAI->addInitialFrameState(Inst2); + + return MAI; +} + +static MCRelocationInfo *createM680x0MCRelocationInfo(const Triple &TheTriple, + MCContext &Ctx) { + // Default to the stock relocation info. + return llvm::createMCRelocationInfo(TheTriple, Ctx); +} + +static MCInstPrinter *createM680x0MCInstPrinter(const Triple &T, + unsigned SyntaxVariant, + const MCAsmInfo &MAI, + const MCInstrInfo &MII, + const MCRegisterInfo &MRI) { + return new M680x0InstPrinter(MAI, MII, MRI); +} + +extern "C" void LLVMInitializeM680x0TargetMC() { + Target &T = TheM680x0Target; + + // Register the MC asm info. + RegisterMCAsmInfoFn X(T, createM680x0MCAsmInfo); + + // Register the MC instruction info. + TargetRegistry::RegisterMCInstrInfo(T, createM680x0MCInstrInfo); + + // Register the MC register info. + TargetRegistry::RegisterMCRegInfo(T, createM680x0MCRegisterInfo); + + // Register the MC subtarget info. + TargetRegistry::RegisterMCSubtargetInfo(T, createM680x0MCSubtargetInfo); + + // Register the code emitter. + TargetRegistry::RegisterMCCodeEmitter(T, createM680x0MCCodeEmitter); + + // Register the MCInstPrinter. + TargetRegistry::RegisterMCInstPrinter(T, createM680x0MCInstPrinter); + + // Register the MC relocation info. + TargetRegistry::RegisterMCRelocationInfo(T, createM680x0MCRelocationInfo); + + // Register the asm backend. + TargetRegistry::RegisterMCAsmBackend(T, createM680x0AsmBackend); +} Index: llvm/lib/Target/M680x0/README.md =================================================================== --- /dev/null +++ llvm/lib/Target/M680x0/README.md @@ -0,0 +1,4 @@ +Motorola 680x0 LLVM Target +========================== + +To build follow the usual LLVM/Clang workflow. Index: llvm/lib/Target/M680x0/TODO.md =================================================================== --- /dev/null +++ llvm/lib/Target/M680x0/TODO.md @@ -0,0 +1,24 @@ +# TODO + +## Global +### TLS + - All of it + +### Assembler/Disassembler + - All of it + +### Dynamic Stack Allocation + - Part related to stack-split and tls + +### ISA x10, x20, x30, x40, x50, x60 and all in between + +## Instructions + +### Floats + +### JSR + - can be relaxed to use shorter BSR + +### GOT + - is random GOT register is fine? + - does PLT really do no require GOT ref? or is it platform depended Index: llvm/test/CodeGen/M680x0/OBJ/Arith/Classes/MxBiArOp_FMI.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Arith/Classes/MxBiArOp_FMI.mir @@ -0,0 +1,88 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=ADD8fi,ADD32fi,ADD8pi,ADD32pi,ADD8ji,ADD32ji + +#------------------------------------------------------------------------------ +# MxBiArOp_FMI class used for binary arithmetic operations and operates on +# memory and immediate data. It uses MxArithImmEncoding class. +#------------------------------------------------------------------------------ + + +--- # ARII +# -------------------------------+-------+-----------+----------- +# F E D C B A 9 8 | 7 6 | 5 4 3 | 2 1 0 +# -------------------------------+-------+-----------+----------- +# OPWORD x x x x x x x x | SIZE | MODE | REG +# -------------------------------+-------+-----------+----------- +# ADD8fi: 0 0 0 0 0 1 1 0 . 0 0 1 1 0 0 0 0 +# ADD8fi-SAME: 0 0 0 0 0 0 0 0 . 1 1 1 1 1 1 1 1 +# ADD8fi-SAME: 0 0 0 0 1 0 0 0 . 0 0 0 0 0 0 0 0 +# -------------------------------+------------------------------- +# ADD8fi-SAME: 0 0 0 0 0 1 1 0 . 0 0 1 1 0 0 1 1 +# ADD8fi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# ADD8fi-SAME: 1 0 0 1 1 0 0 0 . 1 1 1 1 1 1 1 1 +# -------------------------------+------------------------------- +# ADD32fi-SAME: 0 0 0 0 0 1 1 0 . 1 0 1 1 0 0 1 0 +# ADD32fi-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# ADD32fi-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# ADD32fi-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 1 1 0 1 +# ---+-----------+---+-------+---+------------------------------- +# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT +# ---+-----------+---+-------+---+------------------------------- +name: MxBiArOp_FMI_ARII +body: | + bb.0: + ADD8fi 0, $a0, $d0, -1, implicit-def $ccr + ADD8fi -1, $a3, $a1, 0, implicit-def $ccr + ADD32fi 13, $a2, $d1, -1, implicit-def $ccr + +... +--- # ARID +# -------------------------------+-------+-----------+----------- +# F E D C B A 9 8 | 7 6 | 5 4 3 | 2 1 0 +# -------------------------------+-------+-----------+----------- +# OPWORD x x x x x x x x | SIZE | MODE | REG +# -------------------------------+-------+-----------+----------- +# ADD8pi-SAME: 0 0 0 0 0 1 1 0 . 0 0 1 0 1 0 0 0 +# ADD8pi-SAME: 0 0 0 0 0 0 0 0 . 1 1 1 1 1 1 1 1 +# ADD8pi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# -------------------------------+------------------------------- +# ADD8pi-SAME: 0 0 0 0 0 1 1 0 . 0 0 1 0 1 0 1 1 +# ADD8pi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# ADD8pi-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# -------------------------------+------------------------------- +# ADD32pi-SAME: 0 0 0 0 0 1 1 0 . 1 0 1 0 1 0 1 0 +# ADD32pi-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# ADD32pi-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# ADD32pi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 1 1 0 1 +name: MxBiArOp_FMI_ARID +body: | + bb.0: + ADD8pi 0, $a0, -1, implicit-def $ccr + ADD8pi -1, $a3, 0, implicit-def $ccr + ADD32pi 13, $a2, -1, implicit-def $ccr + +... +--- # ARI +# -------------------------------+-------+-----------+----------- +# F E D C B A 9 8 | 7 6 | 5 4 3 | 2 1 0 +# -------------------------------+-------+-----------+----------- +# OPWORD x x x x x x x x | SIZE | MODE | REG +# -------------------------------+-------+-----------+----------- +# ADD8ji-SAME: 0 0 0 0 0 1 1 0 . 0 0 0 1 0 0 0 0 +# ADD8ji-SAME: 0 0 0 0 0 0 0 0 . 1 1 1 1 1 1 1 1 +# -------------------------------+------------------------------- +# ADD8ji-SAME: 0 0 0 0 0 1 1 0 . 0 0 0 1 0 0 1 1 +# ADD8ji-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# -------------------------------+------------------------------- +# ADD32ji-SAME: 0 0 0 0 0 1 1 0 . 1 0 0 1 0 0 1 0 +# ADD32ji-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# ADD32ji-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +name: MxBiArOp_FMI_ARI +body: | + bb.0: + ADD8ji $a0, -1, implicit-def $ccr + ADD8ji $a3, 0, implicit-def $ccr + ADD32ji $a2, -1, implicit-def $ccr + +... Index: llvm/test/CodeGen/M680x0/OBJ/Arith/Classes/MxBiArOp_FMR.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Arith/Classes/MxBiArOp_FMR.mir @@ -0,0 +1,73 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=ADD8fd,ADD32fd,ADD8pd,ADD32pd,ADD8jd,ADD32jd + +#------------------------------------------------------------------------------ +# MxBiArOp_FMR class used for binary arithmetic operations and operates on +# register and memory; the result is store to memory. It uses MxArithEncoding +# encoding class and MxOpModeEAd opmode class. +#------------------------------------------------------------------------------ + +--- # ARII +# ---------------+-----------+-----------+-----------+----------- +# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# ---------------+-----------+-----------+-----------+----------- +# OPWORD x x x x | REG | OPMODE | MODE | REG +# ---------------+-----------+-----------+-----------+----------- +# ADD8fd: 1 1 0 1 0 0 0 1 . 0 0 1 1 0 0 0 0 +# ADD8fd-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# ADD8fd-SAME: 1 1 0 1 0 0 0 1 . 0 0 1 1 0 0 0 0 +# ADD8fd-SAME: 0 0 0 1 1 0 0 0 . 1 1 1 1 1 1 1 1 +# --------------------------------------------------------------- +# ADD32fd-SAME: 1 1 0 1 0 0 0 1 . 1 0 1 1 0 0 0 1 +# ADD32fd-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# ADD32fd-SAME: 1 1 0 1 0 0 1 1 . 1 0 1 1 0 0 1 0 +# ADD32fd-SAME: 1 0 1 0 1 0 0 0 . 0 0 0 0 0 0 0 0 +# ---+-----------+---+-------+---+------------------------------- +# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT +# ---+-----------+---+-------+---+------------------------------- +name: MxBiArOp_FMR_ARII +body: | + bb.0: + ADD8fd 0, $a0, $d1, $bd0, implicit-def $ccr + ADD8fd -1, $a0, $d1, $bd0, implicit-def $ccr + ADD32fd 0, $a1, $d1, $d0, implicit-def $ccr + ADD32fd 0, $a2, $a2, $d1, implicit-def $ccr + +... +--- # ARID +# ---------------+-----------+-----------+-----------+----------- +# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# ---------------+-----------+-----------+-----------+----------- +# OPWORD x x x x | REG | OPMODE | MODE | REG +# ---------------+-----------+-----------+-----------+----------- +# ADD8pd-SAME: 1 1 0 1 0 0 0 1 . 0 0 1 0 1 0 0 0 +# ADD8pd-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# ADD32pd-SAME: 1 1 0 1 0 0 0 1 . 1 0 1 0 1 0 0 1 +# ADD32pd-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +name: MxBiArOp_FMR_ARID +body: | + bb.0: + ADD8pd 0, $a0, $bd0, implicit-def $ccr + ADD32pd -1, $a1, $d0, implicit-def $ccr + +... +--- # ARI +# ---------------+-----------+-----------+-----------+----------- +# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# ---------------+-----------+-----------+-----------+----------- +# OPWORD x x x x | REG | OPMODE | MODE | REG +# ---------------+-----------+-----------+-----------+----------- +# ADD8jd-SAME: 1 1 0 1 0 0 0 1 . 0 0 0 1 0 0 0 0 +# --------------------------------------------------------------- +# ADD32jd-SAME: 1 1 0 1 0 1 1 1 . 1 0 0 1 0 0 0 1 +name: MxBiArOp_FMR_ARI +body: | + bb.0: + ADD8jd $a0, $bd0, implicit-def $ccr + ADD32jd $a1, $d3, implicit-def $ccr + +... Index: llvm/test/CodeGen/M680x0/OBJ/Arith/Classes/MxBiArOp_RFRI.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Arith/Classes/MxBiArOp_RFRI.mir @@ -0,0 +1,41 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=XOR16di,XOR32di + +#------------------------------------------------------------------------------ +# MxBiArOp_RFRI class used for binary arithmetic operations and operates on +# register and immediate data. It uses MxArithImmEncoding class. This is special +# case for XOR. +#------------------------------------------------------------------------------ + + +# -------------------------------+-------+-----------+----------- +# F E D C B A 9 8 | 7 6 | 5 4 3 | 2 1 0 +# -------------------------------+-------+-----------+----------- +# x x x x x x x x | SIZE | MODE | REG +# -------------------------------+-------+-----------+----------- +# XOR16di: 0 0 0 0 1 0 1 0 . 0 1 0 0 0 0 0 0 +# XOR16di-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# -------------------------------+------------------------------- +# XOR16di-SAME: 0 0 0 0 1 0 1 0 . 0 1 0 0 0 0 1 1 +# XOR16di-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# -------------------------------+------------------------------- +# XOR32di-SAME: 0 0 0 0 1 0 1 0 . 1 0 0 0 0 0 0 0 +# XOR32di-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# XOR32di-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# -------------------------------+------------------------------- +# XOR32di-SAME: 0 0 0 0 1 0 1 0 . 1 0 0 0 0 0 0 0 +# XOR32di-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 1 +# XOR32di-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# -------------------------------+------------------------------- +# XOR32di-SAME: 0 0 0 0 1 0 1 0 . 1 0 0 0 0 1 1 1 +# XOR32di-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 1 1 1 +# XOR32di-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +name: MxBiArOp_RFRI +body: | + bb.0: + $wd0 = XOR16di $wd0, 0, implicit-def $ccr + $wd3 = XOR16di $wd3, -1, implicit-def $ccr + $d0 = XOR32di $d0, -1, implicit-def $ccr + $d0 = XOR32di $d0, 131071, implicit-def $ccr + $d7 = XOR32di $d7, 458752, implicit-def $ccr Index: llvm/test/CodeGen/M680x0/OBJ/Arith/Classes/MxBiArOp_RFRI_xEA.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Arith/Classes/MxBiArOp_RFRI_xEA.mir @@ -0,0 +1,45 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=ADD16di,ADD32ri + +#------------------------------------------------------------------------------ +# MxBiArOp_RFRI_xEA class used for binary arithmetic operations and operates on +# register and immediate data. It uses MxArithEncoding(yes for immediates) class +# and either MxOpModeNdEA or MxOpmodeNrEA opmode classes. +#------------------------------------------------------------------------------ + + +# ---------------+-----------+-----------+-----------+----------- +# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# ---------------+-----------+-----------+-----------+----------- +# x x x x | REG | OPMODE | MODE | REG +# ADD16di: 1 1 0 1 0 0 0 0 . 0 1 1 1 1 1 0 0 +# ADD16di: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# ---------------+-----------+-----------+-----------+----------- +# ADD16di-SAME: 1 1 0 1 0 1 1 0 . 0 1 1 1 1 1 0 0 +# ADD16di-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# ---------------+-----------+-----------+-----------+----------- +# ADD32ri-SAME: 1 1 0 1 0 0 0 0 . 1 0 1 1 1 1 0 0 +# ADD32ri-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# ADD32ri-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# ---------------+-----------+-----------+-----------+----------- +# ADD32ri-SAME: 1 1 0 1 0 0 0 0 . 1 0 1 1 1 1 0 0 +# ADD32ri-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 1 +# ADD32ri-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# ---------------+-----------+-----------+-----------+----------- +# ADD32ri-SAME: 1 1 0 1 1 1 1 0 . 1 0 1 1 1 1 0 0 +# ADD32ri-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 1 1 1 +# ADD32ri-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# ---------------+-----------+-----------+-----------+----------- +# ADD32ri-SAME: 1 1 0 1 0 0 0 1 . 1 1 1 1 1 1 0 0 +# ADD32ri-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# ADD32ri-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +name: MxBiArOp_RFRI_xEA +body: | + bb.0: + $wd0 = ADD16di $wd0, 0, implicit-def $ccr + $wd3 = ADD16di $wd3, -1, implicit-def $ccr + $d0 = ADD32ri $d0, -1, implicit-def $ccr + $d0 = ADD32ri $d0, 131071, implicit-def $ccr + $d7 = ADD32ri $d7, 458752, implicit-def $ccr + $a0 = ADD32ri $a0, 0, implicit-def $ccr Index: llvm/test/CodeGen/M680x0/OBJ/Arith/Classes/MxBiArOp_RFRM.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Arith/Classes/MxBiArOp_RFRM.mir @@ -0,0 +1,121 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=ADD8dk,ADD32rk,ADD8dq,ADD32rq,\ +# RUN:ADD8df,ADD32rf,ADD8dp,ADD32rp,ADD8dj,ADD32rj + +#------------------------------------------------------------------------------ +# MxBiArOp_RFRM class used for binary arithmetic operations and operates on +# register and memory. It uses MxArithEncoding encoding class and either +# MxOpModeNdEA or MxOpModeNrEA opmode classes. +#------------------------------------------------------------------------------ + +--- # PCI +# ---------------+-----------+-----------+-----------+----------- +# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# ---------------+-----------+-----------+-----------+----------- +# OPWORD x x x x | REG | OPMODE | MODE | REG +# ---------------+-----------+-----------+-----------+----------- +# ADD8dk: 1 1 0 1 0 0 0 0 . 0 0 1 1 1 0 1 1 +# ADD8dk-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# ADD8dk-SAME: 1 1 0 1 0 0 0 0 . 0 0 1 1 1 0 1 1 +# ADD8dk-SAME: 0 0 0 1 1 0 0 0 . 1 1 1 1 1 1 1 1 +# --------------------------------------------------------------- +# ADD32rk-SAME: 1 1 0 1 0 0 0 0 . 1 0 1 1 1 0 1 1 +# ADD32rk-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# ADD32rk-SAME: 1 1 0 1 0 0 1 1 . 1 1 1 1 1 0 1 1 +# ADD32rk-SAME: 1 0 1 0 1 0 0 0 . 0 0 0 0 0 0 0 0 +# ---+-----------+---+-------+---+------------------------------- +# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT +# ---+-----------+---+-------+---+------------------------------- +name: MxBiArOp_RFRM_PCI +body: | + bb.0: + $bd0 = ADD8dk $bd0, 0, $d1, implicit-def $ccr + $bd0 = ADD8dk $bd0, -1, $d1, implicit-def $ccr + $d0 = ADD32rk $d0, 0, $d1, implicit-def $ccr + $a1 = ADD32rk $a1, 0, $a2, implicit-def $ccr + +... +--- # PCD +# ---------------+-----------+-----------+-----------+----------- +# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# ---------------+-----------+-----------+-----------+----------- +# OPWORD x x x x | REG | OPMODE | MODE | REG +# ---------------+-----------+-----------+-----------+----------- +# ADD8dq-SAME: 1 1 0 1 0 0 0 0 . 0 0 1 1 1 0 1 0 +# ADD8dq-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# ADD32rq-SAME: 1 1 0 1 0 0 0 0 . 1 0 1 1 1 0 1 0 +# ADD32rq-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +name: MxBiArOp_RFRM_PCD +body: | + bb.0: + $bd0 = ADD8dq $bd0, 0, implicit-def $ccr + $d0 = ADD32rq $d0, -1, implicit-def $ccr + +... +--- # ARII +# ---------------+-----------+-----------+-----------+----------- +# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# ---------------+-----------+-----------+-----------+----------- +# OPWORD x x x x | REG | OPMODE | MODE | REG +# ---------------+-----------+-----------+-----------+----------- +# ADD8df-SAME: 1 1 0 1 0 0 0 0 . 0 0 1 1 0 0 0 0 +# ADD8df-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# ADD8df-SAME: 1 1 0 1 0 0 0 0 . 0 0 1 1 0 0 0 0 +# ADD8df-SAME: 0 0 0 1 1 0 0 0 . 1 1 1 1 1 1 1 1 +# --------------------------------------------------------------- +# ADD32rf-SAME: 1 1 0 1 0 0 0 0 . 1 0 1 1 0 0 0 1 +# ADD32rf-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# ADD32rf-SAME: 1 1 0 1 0 0 1 1 . 1 1 1 1 0 0 1 0 +# ADD32rf-SAME: 1 0 1 0 1 0 0 0 . 0 0 0 0 0 0 0 0 +# ---+-----------+---+-------+---+------------------------------- +# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT +# ---+-----------+---+-------+---+------------------------------- +name: MxBiArOp_RFRM_ARII +body: | + bb.0: + $bd0 = ADD8df $bd0, 0, $a0, $d1, implicit-def $ccr + $bd0 = ADD8df $bd0, -1, $a0, $d1, implicit-def $ccr + $d0 = ADD32rf $d0, 0, $a1, $d1, implicit-def $ccr + $a1 = ADD32rf $a1, 0, $a2, $a2, implicit-def $ccr + +... +--- # ARID +# ---------------+-----------+-----------+-----------+----------- +# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# ---------------+-----------+-----------+-----------+----------- +# OPWORD x x x x | REG | OPMODE | MODE | REG +# ---------------+-----------+-----------+-----------+----------- +# ADD8dp-SAME: 1 1 0 1 0 0 0 0 . 0 0 1 0 1 0 0 0 +# ADD8dp-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# ADD32rp-SAME: 1 1 0 1 0 0 0 0 . 1 0 1 0 1 0 0 1 +# ADD32rp-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +name: MxBiArOp_RFRM_ARID +body: | + bb.0: + $bd0 = ADD8dp $bd0, 0, $a0, implicit-def $ccr + $d0 = ADD32rp $d0, -1, $a1, implicit-def $ccr + +... +--- # ARI +# ---------------+-----------+-----------+-----------+----------- +# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# ---------------+-----------+-----------+-----------+----------- +# OPWORD x x x x | REG | OPMODE | MODE | REG +# ---------------+-----------+-----------+-----------+----------- +# ADD8dj-SAME: 1 1 0 1 0 0 0 0 . 0 0 0 1 0 0 0 0 +# --------------------------------------------------------------- +# ADD32rj-SAME: 1 1 0 1 0 1 1 1 . 1 1 0 1 0 0 0 1 +name: MxBiArOp_RFRM_ARI +body: | + bb.0: + $bd0 = ADD8dj $bd0, $a0, implicit-def $ccr + $a3 = ADD32rj $a3, $a1, implicit-def $ccr + +... Index: llvm/test/CodeGen/M680x0/OBJ/Arith/Classes/MxBiArOp_RFRRF.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Arith/Classes/MxBiArOp_RFRRF.mir @@ -0,0 +1,27 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=ADDX16dd,ADDX32dd + +#------------------------------------------------------------------------------ +# MxBiArOp_RFRRF class used for carry-aware binary arithmetic operations and +# operates on both data and address registers only. It uses MxArithXEncoding +# encoding class and either MxOpModeNdEA or MxOpModeNrEA opmode classes. +#------------------------------------------------------------------------------ + + +# --------------------------------------------------------------- +# F E D C | B A 9 | 8 | 7 6 | 5 4 | 3 | 2 1 0 +# ---------------+-----------+---+-------+-------+---+----------- +# x x x x | REG Rx | 1 | SIZE | 0 0 | M | REG Ry +# ---------------+-----------+---+-------+-------+---+----------- +# ADDX16dd: 1 1 0 1 0 0 0 1 . 0 1 0 0 0 0 0 1 +# ADDX16dd-SAME: 1 1 0 1 0 1 1 1 . 0 1 0 0 0 0 1 0 +# ADDX32dd-SAME: 1 1 0 1 0 0 0 1 . 1 0 0 0 0 0 0 1 +# ADDX32dd-SAME: 1 1 0 1 1 1 1 1 . 1 0 0 0 0 0 0 1 +name: MxBiArOp_RFRRF +body: | + bb.0: + $wd0 = ADDX16dd $wd0, $wd1, implicit $ccr, implicit-def $ccr + $wd3 = ADDX16dd $wd3, $wd2, implicit $ccr, implicit-def $ccr + $d0 = ADDX32dd $d0, $d1, implicit $ccr, implicit-def $ccr + $d7 = ADDX32dd $d7, $d1, implicit $ccr, implicit-def $ccr Index: llvm/test/CodeGen/M680x0/OBJ/Arith/Classes/MxBiArOp_RFRR_EAd.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Arith/Classes/MxBiArOp_RFRR_EAd.mir @@ -0,0 +1,26 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=XOR16dd,XOR32dd + +#------------------------------------------------------------------------------ +# MxBiArOp_RFRR_EAd class used for binary arithmetic operations and operates on +# both data and address registers only. It uses MxArithEncoding encoding class +# and MxOpModeEAd opmode class. This is a special case for XOR(EOR). +#------------------------------------------------------------------------------ + + +# ---------------+-----------+-----------+-----------+----------- +# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# ---------------+-----------+-----------+-----------+----------- +# x x x x | REG | OPMODE | MODE | REG +# XOR16dd: 1 0 1 1 0 0 1 1 . 0 1 0 0 0 0 0 0 +# XOR16dd-SAME: 1 0 1 1 0 1 0 1 . 0 1 0 0 0 0 1 1 +# XOR32dd-SAME: 1 0 1 1 0 0 1 1 . 1 0 0 0 0 0 0 0 +# XOR32dd-SAME: 1 0 1 1 0 0 1 1 . 1 0 0 0 0 1 1 1 +name: MxBiArOp_RFRR_EAd +body: | + bb.0: + $wd0 = XOR16dd $wd0, $wd1, implicit-def $ccr + $wd3 = XOR16dd $wd3, $wd2, implicit-def $ccr + $d0 = XOR32dd $d0, $d1, implicit-def $ccr + $d7 = XOR32dd $d7, $d1, implicit-def $ccr Index: llvm/test/CodeGen/M680x0/OBJ/Arith/Classes/MxBiArOp_RFRR_xEA.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Arith/Classes/MxBiArOp_RFRR_xEA.mir @@ -0,0 +1,30 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=ADD16dd,ADD32rr + +#------------------------------------------------------------------------------ +# MxBiArOp_RFRR_xEA class used for binary arithmetic operations and operates on +# both data and address registers only. It uses MxArithEncoding encoding class +# and either MxOpModeNdEA or MxOpmodeNrEA opmode classes. +#------------------------------------------------------------------------------ + + +# ---------------+-----------+-----------+-----------+----------- +# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# ---------------+-----------+-----------+-----------+----------- +# x x x x | REG | OPMODE | MODE | REG +# ADD16dd: 1 1 0 1 0 0 0 0 . 0 1 0 0 0 0 0 1 +# ADD16dd-SAME: 1 1 0 1 0 1 1 0 . 0 1 0 0 0 0 1 0 +# ADD32rr-SAME: 1 1 0 1 0 0 0 0 . 1 0 0 0 0 0 0 1 +# ADD32rr-SAME: 1 1 0 1 0 0 0 0 . 1 0 0 0 1 0 0 1 +# ADD32rr-SAME: 1 1 0 1 1 1 1 0 . 1 0 0 0 1 0 0 1 +# ADD32rr-SAME: 1 1 0 1 0 0 0 1 . 1 1 0 0 0 0 0 1 +name: MxBiArOp_RFRR_xEA +body: | + bb.0: + $wd0 = ADD16dd $wd0, $wd1, implicit-def $ccr + $wd3 = ADD16dd $wd3, $wd2, implicit-def $ccr + $d0 = ADD32rr $d0, $d1, implicit-def $ccr + $d0 = ADD32rr $d0, $a1, implicit-def $ccr + $d7 = ADD32rr $d7, $a1, implicit-def $ccr + $a0 = ADD32rr $a0, $d1, implicit-def $ccr Index: llvm/test/CodeGen/M680x0/OBJ/Arith/Classes/MxCMP_BI.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Arith/Classes/MxCMP_BI.mir @@ -0,0 +1,44 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=CMP8bi,CMP32bi + +#------------------------------------------------------------------------------ +# MxCMP_BI class used for compare operations and operates on absolute memory +# locations and immediate data. It uses MxArithImmEncoding encoding class. +# NOTE: CMP is calculated by subtracting LHS(Imm) from RHS(ABS) +#------------------------------------------------------------------------------ + + +# -------------------------------+-------+-----------+----------- +# F E D C B A 9 8 | 7 6 | 5 4 3 | 2 1 0 +# -------------------------------+-------+-----------+----------- +# OPWORD 0 0 0 0 1 1 0 0 | SIZE | MODE | REG +# -------------------------------+-------+-----------+----------- +# CMP8bi: 0 0 0 0 1 1 0 0 . 0 0 1 1 1 0 0 1 +# CMP8bi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# CMP8bi-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# CMP8bi-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# -------------------------------+-------+-----------+----------- +# CMP8bi-SAME: 0 0 0 0 1 1 0 0 . 0 0 1 1 1 0 0 1 +# CMP8bi-SAME: 0 0 0 0 0 0 0 0 . 1 1 1 1 1 1 1 1 +# CMP8bi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# CMP8bi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# -------------------------------+-------+-----------+----------- +# CMP32bi-SAME: 0 0 0 0 1 1 0 0 . 1 0 1 1 1 0 0 1 +# CMP32bi-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# CMP32bi-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# CMP32bi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# CMP32bi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# -------------------------------+-------+-----------+----------- +# CMP32bi-SAME: 0 0 0 0 1 1 0 0 . 1 0 1 1 1 0 0 1 +# CMP32bi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# CMP32bi-SAME: 0 0 0 0 0 0 0 0 . 0 0 1 0 1 0 1 0 +# CMP32bi-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# CMP32bi-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +name: MxCMP_BI +body: | + bb.0: + CMP8bi 0, -1, implicit-def $ccr + CMP8bi -1, 0, implicit-def $ccr + CMP32bi -1, 0, implicit-def $ccr + CMP32bi 42, -1, implicit-def $ccr Index: llvm/test/CodeGen/M680x0/OBJ/Arith/Classes/MxCMP_MI.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Arith/Classes/MxCMP_MI.mir @@ -0,0 +1,172 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=CMP8ki,CMP32ki,CMP8qi,CMP32qi,CMP8fi,\ +# RUN:CMP32fi,CMP8pi,CMP32pi,CMP8ji,CMP32ji + +#------------------------------------------------------------------------------ +# MxCMP_MI class used for compare operations and operates on memory data and +# immediate data. It uses MxArithImmEncoding encoding class. +# NOTE: CMP is calculated by subtracting LHS(Imm) from RHS(Mem) +#------------------------------------------------------------------------------ + + +--- # PCI +# -------------------------------+-------+-----------+----------- +# F E D C B A 9 8 | 7 6 | 5 4 3 | 2 1 0 +# -------------------------------+-------+-----------+----------- +# OPWORD 0 0 0 0 1 1 0 0 | SIZE | MODE | REG +# -------------------------------+-------+-----------+----------- +# CMP8ki: 0 0 0 0 1 1 0 0 . 0 0 1 1 1 0 1 1 +# CMP8ki-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# CMP8ki-SAME: 0 0 0 1 1 0 0 0 . 1 1 1 1 1 1 1 1 +# -------------------------------+-------+-----------+----------- +# CMP8ki-SAME: 0 0 0 0 1 1 0 0 . 0 0 1 1 1 0 1 1 +# CMP8ki-SAME: 0 0 0 0 0 0 0 0 . 1 1 1 1 1 1 1 1 +# CMP8ki-SAME: 0 0 0 0 1 0 0 0 . 0 0 0 0 0 0 0 0 +# -------------------------------+-------+-----------+----------- +# CMP32ki-SAME: 0 0 0 0 1 1 0 0 . 1 0 1 1 1 0 1 1 +# CMP32ki-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# CMP32ki-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# CMP32ki-SAME: 0 1 1 1 1 0 0 0 . 0 0 0 0 0 0 0 0 +# -------------------------------+-------+-----------+----------- +# CMP32ki-SAME: 0 0 0 0 1 1 0 0 . 1 0 1 1 1 0 1 1 +# CMP32ki-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# CMP32ki-SAME: 0 0 0 0 0 0 0 0 . 0 0 1 0 1 0 1 0 +# CMP32ki-SAME: 0 0 0 1 1 0 0 0 . 1 1 1 1 1 1 1 1 +# ---+-----------+---+-------+---+------------------------------- +# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT +# ---+-----------+---+-------+---+------------------------------- +name: MxCMP_MI_PCI +body: | + bb.0: + CMP8ki 0, -1, $d1, implicit-def $ccr + CMP8ki -1, 0, $d0, implicit-def $ccr + CMP32ki -1, 0, $d7, implicit-def $ccr + CMP32ki 42, -1, $d1, implicit-def $ccr + +... +--- # PCD +# -------------------------------+-------+-----------+----------- +# F E D C B A 9 8 | 7 6 | 5 4 3 | 2 1 0 +# -------------------------------+-------+-----------+----------- +# OPWORD 0 0 0 0 1 1 0 0 | SIZE | MODE | REG +# -------------------------------+-------+-----------+----------- +# CMP8qi-SAME: 0 0 0 0 1 1 0 0 . 0 0 1 1 1 0 1 0 +# CMP8qi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# CMP8qi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# -------------------------------+-------+-----------+----------- +# CMP8qi-SAME: 0 0 0 0 1 1 0 0 . 0 0 1 1 1 0 1 0 +# CMP8qi-SAME: 0 0 0 0 0 0 0 0 . 1 1 1 1 1 1 1 1 +# CMP8qi-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# -------------------------------+-------+-----------+----------- +# CMP32qi-SAME: 0 0 0 0 1 1 0 0 . 1 0 1 1 1 0 1 0 +# CMP32qi-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# CMP32qi-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# CMP32qi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# -------------------------------+-------+-----------+----------- +# CMP32qi-SAME: 0 0 0 0 1 1 0 0 . 1 0 1 1 1 0 1 0 +# CMP32qi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# CMP32qi-SAME: 0 0 0 0 0 0 0 0 . 0 0 1 0 1 0 1 0 +# CMP32qi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +name: MxCMP_MI_PCD +body: | + bb.0: + CMP8qi 0, 0, implicit-def $ccr + CMP8qi -1, -1, implicit-def $ccr + CMP32qi -1, 0, implicit-def $ccr + CMP32qi 42, 0, implicit-def $ccr + +... +--- # ARII +# -------------------------------+-------+-----------+----------- +# F E D C B A 9 8 | 7 6 | 5 4 3 | 2 1 0 +# -------------------------------+-------+-----------+----------- +# OPWORD 0 0 0 0 1 1 0 0 | SIZE | MODE | REG +# -------------------------------+-------+-----------+----------- +# CMP8fi-SAME: 0 0 0 0 1 1 0 0 . 0 0 1 1 0 0 0 1 +# CMP8fi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# CMP8fi-SAME: 1 0 0 0 1 0 0 0 . 1 1 1 1 1 1 1 1 +# -------------------------------+-------+-----------+----------- +# CMP8fi-SAME: 0 0 0 0 1 1 0 0 . 0 0 1 1 0 0 0 0 +# CMP8fi-SAME: 0 0 0 0 0 0 0 0 . 1 1 1 1 1 1 1 1 +# CMP8fi-SAME: 1 0 0 0 1 0 0 0 . 0 0 0 0 0 0 0 0 +# -------------------------------+-------+-----------+----------- +# CMP32fi-SAME: 0 0 0 0 1 1 0 0 . 1 0 1 1 0 1 1 0 +# CMP32fi-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# CMP32fi-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# CMP32fi-SAME: 1 0 0 0 1 0 0 0 . 0 0 0 0 0 0 0 0 +# -------------------------------+-------+-----------+----------- +# CMP32fi-SAME: 0 0 0 0 1 1 0 0 . 1 0 1 1 0 0 0 1 +# CMP32fi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# CMP32fi-SAME: 0 0 0 0 0 0 0 0 . 0 0 1 0 1 0 1 0 +# CMP32fi-SAME: 1 0 0 0 1 0 0 0 . 1 1 1 1 1 1 1 1 +# ---+-----------+---+-------+---+------------------------------- +# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT +# ---+-----------+---+-------+---+------------------------------- +name: MxCMP_MI_ARII +body: | + bb.0: + CMP8fi 0, -1, $a1, $a0, implicit-def $ccr + CMP8fi -1, 0, $a0, $a0, implicit-def $ccr + CMP32fi -1, 0, $a6, $a0, implicit-def $ccr + CMP32fi 42, -1, $a1, $a0, implicit-def $ccr + +... +--- # ARID +# -------------------------------+-------+-----------+----------- +# F E D C B A 9 8 | 7 6 | 5 4 3 | 2 1 0 +# -------------------------------+-------+-----------+----------- +# OPWORD 0 0 0 0 1 1 0 0 | SIZE | MODE | REG +# -------------------------------+-------+-----------+----------- +# CMP8pi-SAME: 0 0 0 0 1 1 0 0 . 0 0 1 0 1 0 0 1 +# CMP8pi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# CMP8pi-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# -------------------------------+-------+-----------+----------- +# CMP8pi-SAME: 0 0 0 0 1 1 0 0 . 0 0 1 0 1 0 0 0 +# CMP8pi-SAME: 0 0 0 0 0 0 0 0 . 1 1 1 1 1 1 1 1 +# CMP8pi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# -------------------------------+-------+-----------+----------- +# CMP32pi-SAME: 0 0 0 0 1 1 0 0 . 1 0 1 0 1 1 1 0 +# CMP32pi-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# CMP32pi-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# CMP32pi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# -------------------------------+-------+-----------+----------- +# CMP32pi-SAME: 0 0 0 0 1 1 0 0 . 1 0 1 0 1 0 0 1 +# CMP32pi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# CMP32pi-SAME: 0 0 0 0 0 0 0 0 . 0 0 1 0 1 0 1 0 +# CMP32pi-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +name: MxCMP_MI_ARID +body: | + bb.0: + CMP8pi 0, -1, $a1, implicit-def $ccr + CMP8pi -1, 0, $a0, implicit-def $ccr + CMP32pi -1, 0, $a6, implicit-def $ccr + CMP32pi 42, -1, $a1, implicit-def $ccr + +... +--- # ARI +# -------------------------------+-------+-----------+----------- +# F E D C B A 9 8 | 7 6 | 5 4 3 | 2 1 0 +# -------------------------------+-------+-----------+----------- +# OPWORD 0 0 0 0 1 1 0 0 | SIZE | MODE | REG +# -------------------------------+-------+-----------+----------- +# CMP8ji-SAME: 0 0 0 0 1 1 0 0 . 0 0 0 1 0 0 0 1 +# CMP8ji-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# -------------------------------+-------+-----------+----------- +# CMP8ji-SAME: 0 0 0 0 1 1 0 0 . 0 0 0 1 0 0 0 0 +# CMP8ji-SAME: 0 0 0 0 0 0 0 0 . 1 1 1 1 1 1 1 1 +# -------------------------------+-------+-----------+----------- +# CMP32ji-SAME: 0 0 0 0 1 1 0 0 . 1 0 0 1 0 1 1 0 +# CMP32ji-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# -------------------------------+-------+-----------+----------- +# CMP32ji-SAME: 0 0 0 0 1 1 0 0 . 1 0 0 1 0 0 0 1 +# CMP32ji-SAME: 0 0 0 0 0 0 0 0 . 0 0 1 0 1 0 1 0 +name: MxCMP_MI_ARI +body: | + bb.0: + CMP8ji 0, $a1, implicit-def $ccr + CMP8ji -1, $a0, implicit-def $ccr + CMP32ji -1, $a6, implicit-def $ccr + CMP32ji 42, $a1, implicit-def $ccr + +... Index: llvm/test/CodeGen/M680x0/OBJ/Arith/Classes/MxCMP_RI.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Arith/Classes/MxCMP_RI.mir @@ -0,0 +1,36 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=CMP8di,CMP32di + +#------------------------------------------------------------------------------ +# MxCMP_RI class used for compare operations and operates on data registers and +# immediate data. It uses MxArithImmEncoding encoding class. +# NOTE: CMP is calculated by subtracting LHS(Imm) from RHS(Dn) +#------------------------------------------------------------------------------ + + +# -------------------------------+-------+-----------+----------- +# F E D C B A 9 8 | 7 6 | 5 4 3 | 2 1 0 +# -------------------------------+-------+-----------+----------- +# 0 0 0 0 1 1 0 0 | SIZE | MODE | REG +# -------------------------------+-------+-----------+----------- +# CMP8di: 0 0 0 0 1 1 0 0 . 0 0 0 0 0 0 0 1 +# CMP8di-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# -------------------------------+-------+-----------+----------- +# CMP8di-SAME: 0 0 0 0 1 1 0 0 . 0 0 0 0 0 0 0 0 +# CMP8di-SAME: 0 0 0 0 0 0 0 0 . 1 1 1 1 1 1 1 1 +# -------------------------------+-------+-----------+----------- +# CMP32di-SAME: 0 0 0 0 1 1 0 0 . 1 0 0 0 0 1 1 1 +# CMP32di-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# CMP32di-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 1 1 0 1 +# -------------------------------+-------+-----------+----------- +# CMP32di-SAME: 0 0 0 0 1 1 0 0 . 1 0 0 0 0 0 0 1 +# CMP32di-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# CMP32di-SAME: 0 0 0 0 0 0 0 0 . 0 0 1 0 1 0 1 0 +name: MxCMP_RI +body: | + bb.0: + CMP8di 0, $bd1, implicit-def $ccr + CMP8di -1, $bd0, implicit-def $ccr + CMP32di 13, $d7, implicit-def $ccr + CMP32di 42, $d1, implicit-def $ccr Index: llvm/test/CodeGen/M680x0/OBJ/Arith/Classes/MxCMP_RM.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Arith/Classes/MxCMP_RM.mir @@ -0,0 +1,123 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=CMP8kf,CMP32kf,CMP8qp,CMP32qp,CMP8df,CMP32df,\ +# RUN:CMP8dp,CMP32dp,CMP8dj,CMP32dj + +#------------------------------------------------------------------------------ +# MxCMP_RM class used for compare operations and operates on memory data and +# register. It uses MxArithEncoding encoding class. +# NOTE: CMP is calculated by subtracting LHS(Mem) from RHS(Reg) +#------------------------------------------------------------------------------ + +--- # PCI +# ---------------+-----------+-----------+-----------+----------- +# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# ---------------+-----------+-----------+-----------+----------- +# OPWORD x x x x | REG | OPMODE | MODE | REG +# ---------------+-----------+-----------+-----------+----------- +# CMP8dk: 1 0 1 1 0 0 0 0 . 0 0 1 1 1 0 1 1 +# CMP8dk-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# CMP8dk-SAME: 1 0 1 1 0 0 0 0 . 0 0 1 1 1 0 1 1 +# CMP8dk-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# CMP32dk-SAME: 1 0 1 1 0 0 0 0 . 1 0 1 1 1 0 1 1 +# CMP32dk-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0 +# ---+-----------+---+-------+---+------------------------------- +# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT +# ---+-----------+---+-------+---+------------------------------- +# +# NOTE Immediates for pc-rel instructions use relocations and addendum is encoded +# inside the relocation record thus there are 0s instead of the value. +name: MxBiArOp_RFRM_PCI +body: | + bb.0: + CMP8dk $bd0, 0, $d1, implicit-def $ccr + CMP8dk $bd0, -1, $d1, implicit-def $ccr + CMP32dk $d0, 0, $d1, implicit-def $ccr + +... +--- # PCD +# ---------------+-----------+-----------+-----------+----------- +# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# ---------------+-----------+-----------+-----------+----------- +# OPWORD x x x x | REG | OPMODE | MODE | REG +# ---------------+-----------+-----------+-----------+----------- +# CMP8dq-SAME: 1 0 1 1 0 0 0 0 . 0 0 1 1 1 0 1 0 +# CMP8dq-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# CMP32dq-SAME: 1 0 1 1 0 0 0 0 . 1 0 1 1 1 0 1 0 +# CMP32dq-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# +# NOTE Immediates for pc-rel instructions use relocations and addendum is encoded +# inside the relocation record thus there are 0s instead of the value. +name: MxBiArOp_RFRM_PCD +body: | + bb.0: + CMP8dq $bd0, 0, implicit-def $ccr + CMP32dq $d0, -1, implicit-def $ccr + +... +--- # ARII +# ---------------+-----------+-----------+-----------+----------- +# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# ---------------+-----------+-----------+-----------+----------- +# OPWORD x x x x | REG | OPMODE | MODE | REG +# ---------------+-----------+-----------+-----------+----------- +# CMP8df: 1 0 1 1 0 0 0 0 . 0 0 1 1 0 0 0 0 +# CMP8df-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# CMP8df-SAME: 1 0 1 1 0 0 0 0 . 0 0 1 1 0 0 0 0 +# CMP8df-SAME: 0 0 0 1 1 0 0 0 . 1 1 1 1 1 1 1 1 +# --------------------------------------------------------------- +# CMP32df-SAME: 1 0 1 1 0 0 0 0 . 1 0 1 1 0 0 0 1 +# CMP32df-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# CMP32df-SAME: 1 0 1 1 0 0 1 0 . 1 0 1 1 0 0 1 0 +# CMP32df-SAME: 1 0 1 0 1 0 0 0 . 0 0 0 0 0 0 0 0 +# ---+-----------+---+-------+---+------------------------------- +# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT +# ---+-----------+---+-------+---+------------------------------- +name: MxCMP_RM_ARII +body: | + bb.0: + CMP8df $bd0, 0, $a0, $d1, implicit-def $ccr + CMP8df $bd0, -1, $a0, $d1, implicit-def $ccr + CMP32df $d0, 0, $a1, $d1, implicit-def $ccr + CMP32df $d1, 0, $a2, $a2, implicit-def $ccr + +... +--- # ARID +# ---------------+-----------+-----------+-----------+----------- +# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# ---------------+-----------+-----------+-----------+----------- +# OPWORD x x x x | REG | OPMODE | MODE | REG +# ---------------+-----------+-----------+-----------+----------- +# CMP8dp-SAME: 1 0 1 1 0 0 0 0 . 0 0 1 0 1 0 0 0 +# CMP8dp-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# CMP32dp-SAME: 1 0 1 1 0 0 0 0 . 1 0 1 0 1 0 0 1 +# CMP32dp-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +name: MxCMP_RM_ARID +body: | + bb.0: + CMP8dp $bd0, 0, $a0, implicit-def $ccr + CMP32dp $d0, -1, $a1, implicit-def $ccr + +... +--- # ARI +# ---------------+-----------+-----------+-----------+----------- +# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# ---------------+-----------+-----------+-----------+----------- +# OPWORD x x x x | REG | OPMODE | MODE | REG +# ---------------+-----------+-----------+-----------+----------- +# CMP8dj-SAME: 1 0 1 1 0 0 0 0 . 0 0 0 1 0 0 0 0 +# --------------------------------------------------------------- +# CMP32dj-SAME: 1 0 1 1 0 1 1 0 . 1 0 0 1 0 0 0 1 +name: MxCMP_RM_ARI +body: | + bb.0: + CMP8dj $bd0, $a0, implicit-def $ccr + CMP32dj $d3, $a1, implicit-def $ccr + +... Index: llvm/test/CodeGen/M680x0/OBJ/Arith/Classes/MxCMP_RR.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Arith/Classes/MxCMP_RR.mir @@ -0,0 +1,27 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=CMP8dd,CMP32dd + +#------------------------------------------------------------------------------ +# MxCMP_RR class used for compare operations and operates on data registers only. +# It uses MxArithEncoding encoding class and MxOpModeNdEA opmode class. +# NOTE: CMP is calculated by subtracting LHS(EA) from RHS(Dn) +#------------------------------------------------------------------------------ + + +# ---------------+-----------+-----------+-----------+----------- +# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# ---------------+-----------+-----------+-----------+----------- +# x x x x | REG | OPMODE | MODE | REG +# ---------------+-----------+-----------+-----------+----------- +# CMP8dd: 1 0 1 1 0 0 1 0 . 0 0 0 0 0 0 0 0 +# CMP8dd-SAME: 1 0 1 1 0 1 0 0 . 0 0 0 0 0 0 1 1 +# CMP32dd-SAME: 1 0 1 1 0 0 1 0 . 1 0 0 0 0 0 0 0 +# CMP32dd-SAME: 1 0 1 1 0 0 1 0 . 1 0 0 0 0 1 1 1 +name: MxCMP_RR +body: | + bb.0: + CMP8dd $bd0, $bd1, implicit-def $ccr + CMP8dd $bd3, $bd2, implicit-def $ccr + CMP32dd $d0, $d1, implicit-def $ccr + CMP32dd $d7, $d1, implicit-def $ccr Index: llvm/test/CodeGen/M680x0/OBJ/Arith/Classes/MxDiMu.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Arith/Classes/MxDiMu.mir @@ -0,0 +1,46 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=SDIVd32d16,UDIVd32d16,SMULd32d16,UMULd32d16,\ +# RUN:SDIVd32i16,UDIVd32i16,SMULd32i16,UMULd32i16 + +#------------------------------------------------------------------------------ +# MxDiMu is used for sign/unsigned division/multiply of word size data +#------------------------------------------------------------------------------ + + +# --------------------------------------------------------------- +# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# --------------------------------------------------------------- +# x x x x | REG | OPMODE | MODE | REG +# --------------------------------------------------------------- +# SDIVd32d16: 1 0 0 0 0 0 0 1 . 1 1 0 0 0 0 0 1 +# --------------------------------------------------------------- +# UDIVd32d16-SAME: 1 0 0 0 0 0 0 0 . 1 1 0 0 0 0 0 1 +# --------------------------------------------------------------- +# SDIVd32i16-SAME: 1 0 0 0 0 0 0 1 . 1 1 1 1 1 1 0 0 +# SDIVd32i16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# UDIVd32i16-SAME: 1 0 0 0 0 0 0 0 . 1 1 1 1 1 1 0 0 +# UDIVd32i16-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# --------------------------------------------------------------- +# SMULd32d16-SAME: 1 1 0 0 0 0 0 1 . 1 1 0 0 0 0 0 1 +# --------------------------------------------------------------- +# UMULd32d16-SAME: 1 1 0 0 0 0 0 0 . 1 1 0 0 0 0 0 1 +# --------------------------------------------------------------- +# SMULd32i16-SAME: 1 1 0 0 0 0 0 1 . 1 1 1 1 1 1 0 0 +# SMULd32i16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# UMULd32i16-SAME: 1 1 0 0 0 0 0 0 . 1 1 1 1 1 1 0 0 +# UMULd32i16-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# --------------------------------------------------------------- +name: MxDiMu +body: | + bb.0: + $d0 = SDIVd32d16 $d0, $wd1, implicit-def $ccr + $d0 = UDIVd32d16 $d0, $wd1, implicit-def $ccr + $d0 = SDIVd32i16 $d0, 0, implicit-def $ccr + $d0 = UDIVd32i16 $d0, -1, implicit-def $ccr + $d0 = SMULd32d16 $d0, $wd1, implicit-def $ccr + $d0 = UMULd32d16 $d0, $wd1, implicit-def $ccr + $d0 = SMULd32i16 $d0, 0, implicit-def $ccr + $d0 = UMULd32i16 $d0, -1, implicit-def $ccr Index: llvm/test/CodeGen/M680x0/OBJ/Arith/Classes/MxExt.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Arith/Classes/MxExt.mir @@ -0,0 +1,25 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=EXT16,EXT32 + +#------------------------------------------------------------------------------ +# MxExt sign extends data inside a register +#------------------------------------------------------------------------------ + + +# --------------------------------------------------------------- +# F E D C B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# --------------------------------------------------------------- +# 0 1 0 0 1 0 0 | OPMODE | 0 0 0 | REG +# --------------------------------------------------------------- +# EXT16: 0 1 0 0 1 0 0 0 . 1 0 0 0 0 0 0 0 +# EXT16-SAME: 0 1 0 0 1 0 0 0 . 1 0 0 0 0 0 1 1 +# EXT32-SAME: 0 1 0 0 1 0 0 0 . 1 1 0 0 0 0 0 0 +# EXT32-SAME: 0 1 0 0 1 0 0 0 . 1 1 0 0 0 1 1 1 +name: MxEXT +body: | + bb.0: + $wd0 = EXT16 $wd0, implicit-def $ccr + $wd3 = EXT16 $wd3, implicit-def $ccr + $d0 = EXT32 $d0, implicit-def $ccr + $d7 = EXT32 $d7, implicit-def $ccr Index: llvm/test/CodeGen/M680x0/OBJ/Arith/Classes/MxNEG.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Arith/Classes/MxNEG.mir @@ -0,0 +1,39 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=NEG8d,NEG32d,NEGX8d,NEGX32d + +#------------------------------------------------------------------------------ +# MxNEG is used to negate a number +#------------------------------------------------------------------------------ + + +--- # NEG +# ---------------+---------------+-------+-----------+----------- +# F E D C | B A 9 8 | 7 6 | 5 4 3 | 2 1 0 +# ---------------+---------------+-------+----------------------- +# 0 1 0 0 | x x x x | SIZE | MODE | REG +# ---------------+---------------+-------+-----------+----------- +# NEG8d: 0 1 0 0 0 1 0 0 . 0 0 0 0 0 0 0 0 +# NEG32d-SAME: 0 1 0 0 0 1 0 0 . 1 0 0 0 0 0 0 0 +name: MxNEG +body: | + bb.0: + $bd0 = NEG8d $bd0, implicit-def $ccr + $d0 = NEG32d $d0, implicit-def $ccr + +... +--- # NEGX +# ---------------+---------------+-------+-----------+----------- +# F E D C | B A 9 8 | 7 6 | 5 4 3 | 2 1 0 +# ---------------+---------------+-------+----------------------- +# 0 1 0 0 | x x x x | SIZE | MODE | REG +# ---------------+---------------+-------+-----------+----------- +# NEGX8d-SAME: 0 1 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# NEGX32d-SAME: 0 1 0 0 0 0 0 0 . 1 0 0 0 0 0 0 0 +name: MxNEGX +body: | + bb.0: + $bd0 = NEGX8d $bd0, implicit $ccr, implicit-def $ccr + $d0 = NEGX32d $d0, implicit $ccr, implicit-def $ccr + +... Index: llvm/test/CodeGen/M680x0/OBJ/Bits/Classes/MxBTST_MI.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Bits/Classes/MxBTST_MI.mir @@ -0,0 +1,115 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=BTST8ki,BTST8qi,BTST8fi,BTST8pi,BTST8ji + +#------------------------------------------------------------------------------ +# MxBTST_MI class used for BTST operations, the source is locate in memory and +# the bit number is immediate value. This instruciton can only operate on 8 bits. +#------------------------------------------------------------------------------ + + +--- # PCI +# ---------------------------------------+-----------+----------- +# F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0 +# ---------------------------------------+-----------+----------- +# 0 0 0 0 1 0 0 0 0 0 | MODE | REG +# ---------------------------------------+-----------+----------- +# BTST8ki: 0 0 0 0 1 0 0 0 . 0 0 1 1 1 0 1 1 +# BTST8ki-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# BTST8ki-SAME: 0 0 0 1 1 0 0 0 . 1 1 1 1 1 1 1 1 +# -------------------------------+-------+-----------+----------- +# BTST8ki-SAME: 0 0 0 0 1 0 0 0 . 0 0 1 1 1 0 1 1 +# BTST8ki-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 1 +# BTST8ki-SAME: 0 0 0 0 1 0 0 0 . 0 0 0 0 0 0 0 0 +# ---+-----------+---+-------+---+------------------------------- +# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT +# ---+-----------+---+-------+---+------------------------------- +name: MxBTST_MI_PCI +body: | + bb.0: + BTST8ki -1, $d1, 0, implicit-def $ccr + BTST8ki 0, $d0, 1, implicit-def $ccr + +... +--- # PCD +# ---------------------------------------+-----------+----------- +# F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0 +# ---------------------------------------+-----------+----------- +# 0 0 0 0 1 0 0 0 0 0 | MODE | REG +# ---------------------------------------+-----------+----------- +# BTST8qi-SAME: 0 0 0 0 1 0 0 0 . 0 0 1 1 1 0 1 0 +# BTST8qi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# BTST8qi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# -------------------------------+-------+-----------+----------- +# BTST8qi-SAME: 0 0 0 0 1 0 0 0 . 0 0 1 1 1 0 1 0 +# BTST8qi-SAME: 0 0 0 0 0 0 0 0 . 1 1 1 1 1 1 1 1 +# BTST8qi-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# -------------------------------+-------+-----------+----------- +name: MxBTST_MI_PCD +body: | + bb.0: + BTST8qi 0, 0, implicit-def $ccr + BTST8qi -1, -1, implicit-def $ccr + +... +--- # ARII +# ---------------------------------------+-----------+----------- +# F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0 +# ---------------------------------------+-----------+----------- +# 0 0 0 0 1 0 0 0 0 0 | MODE | REG +# ---------------------------------------+-----------+----------- +# BTST8fi-SAME: 0 0 0 0 1 0 0 0 . 0 0 1 1 0 0 0 1 +# BTST8fi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# BTST8fi-SAME: 1 0 0 0 1 0 0 0 . 1 1 1 1 1 1 1 1 +# -------------------------------+-------+-----------+----------- +# BTST8fi-SAME: 0 0 0 0 1 0 0 0 . 0 0 1 1 0 0 0 0 +# BTST8fi-SAME: 0 0 0 0 0 0 0 0 . 1 1 1 1 1 1 1 1 +# BTST8fi-SAME: 1 0 0 0 1 0 0 0 . 0 0 0 0 0 0 0 0 +# ---+-----------+---+-------+---+------------------------------- +# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT +# ---+-----------+---+-------+---+------------------------------- +name: MxBTST_MI_ARII +body: | + bb.0: + BTST8fi -1, $a1, $a0, 0, implicit-def $ccr + BTST8fi 0, $a0, $a0, -1, implicit-def $ccr + +... +--- # ARID +# ---------------------------------------+-----------+----------- +# F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0 +# ---------------------------------------+-----------+----------- +# 0 0 0 0 1 0 0 0 0 0 | MODE | REG +# ---------------------------------------+-----------+----------- +# BTST8pi-SAME: 0 0 0 0 1 0 0 0 . 0 0 1 0 1 0 0 1 +# BTST8pi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# BTST8pi-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# -------------------------------+-------+-----------+----------- +# BTST8pi-SAME: 0 0 0 0 1 0 0 0 . 0 0 1 0 1 0 0 0 +# BTST8pi-SAME: 0 0 0 0 0 0 0 0 . 1 1 1 1 1 1 1 1 +# BTST8pi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +name: MxBTST_MI_ARID +body: | + bb.0: + BTST8pi -1, $a1, 0, implicit-def $ccr + BTST8pi 0, $a0, -1, implicit-def $ccr + +... +--- # ARI +# ---------------------------------------+-----------+----------- +# F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0 +# ---------------------------------------+-----------+----------- +# 0 0 0 0 1 0 0 0 0 0 | MODE | REG +# ---------------------------------------+-----------+----------- +# BTST8ji-SAME: 0 0 0 0 1 0 0 0 . 0 0 0 1 0 0 0 1 +# BTST8ji-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# -------------------------------+-------+-----------+----------- +# BTST8ji-SAME: 0 0 0 0 1 0 0 0 . 0 0 0 1 0 0 0 0 +# BTST8ji-SAME: 0 0 0 0 0 0 0 0 . 1 1 1 1 1 1 1 1 +name: MxBTST_MI_ARI +body: | + bb.0: + BTST8ji $a1, 0, implicit-def $ccr + BTST8ji $a0, -1, implicit-def $ccr + +... Index: llvm/test/CodeGen/M680x0/OBJ/Bits/Classes/MxBTST_MR.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Bits/Classes/MxBTST_MR.mir @@ -0,0 +1,104 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=BTST8kd,BTST8qd,BTST8fd,BTST8pd,BTST8jd + +#------------------------------------------------------------------------------ +# MxBTST_MR class used for BTST operations, the source is locate in memory and +# the bit number is in register. This instruciton can only operate on 8 bits. +#------------------------------------------------------------------------------ + + +--- # PCI +# ---------------+-----------+-----------+-----------+----------- +# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# ---------------+-----------+-----------+-----------+----------- +# 0 0 0 0 | REG | 1 0 0 | MODE | REG +# ---------------+-----------+-----------+-----------+----------- +# BTST8kd: 0 0 0 0 0 0 0 1 . 0 0 1 1 1 0 1 1 +# BTST8kd-SAME: 0 0 0 1 1 0 0 0 . 1 1 1 1 1 1 1 1 +# -------------------------------+-------+-----------+----------- +# BTST8kd-SAME: 0 0 0 0 0 0 1 1 . 0 0 1 1 1 0 1 1 +# BTST8kd-SAME: 0 0 0 0 1 0 0 0 . 0 0 0 0 0 0 0 0 +# ---+-----------+---+-------+---+------------------------------- +# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT +# ---+-----------+---+-------+---+------------------------------- +name: MxBTST_MR_PCI +body: | + bb.0: + BTST8kd -1, $d1, $bd0, implicit-def $ccr + BTST8kd 0, $d0, $bd1, implicit-def $ccr + +... +--- # PCD +# ---------------+-----------+-----------+-----------+----------- +# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# ---------------+-----------+-----------+-----------+----------- +# 0 0 0 0 | REG | 1 0 0 | MODE | REG +# ---------------+-----------+-----------+-----------+----------- +# BTST8qd-SAME: 0 0 0 0 0 0 0 1 . 0 0 1 1 1 0 1 0 +# BTST8qd-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# -------------------------------+-------+-----------+----------- +# BTST8qd-SAME: 0 0 0 0 0 0 1 1 . 0 0 1 1 1 0 1 0 +# BTST8qd-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# -------------------------------+-------+-----------+----------- +name: MxBTST_MR_PCD +body: | + bb.0: + BTST8qd 0, $bd0, implicit-def $ccr + BTST8qd -1, $bd1, implicit-def $ccr + +... +--- # ARII +# ---------------+-----------+-----------+-----------+----------- +# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# ---------------+-----------+-----------+-----------+----------- +# 0 0 0 0 | REG | 1 0 0 | MODE | REG +# ---------------+-----------+-----------+-----------+----------- +# BTST8fd-SAME: 0 0 0 0 0 0 0 1 . 0 0 1 1 0 0 0 1 +# BTST8fd-SAME: 1 0 0 0 1 0 0 0 . 1 1 1 1 1 1 1 1 +# -------------------------------+-------+-----------+----------- +# BTST8fd-SAME: 0 0 0 0 0 0 1 1 . 0 0 1 1 0 0 0 0 +# BTST8fd-SAME: 1 0 0 0 1 0 0 0 . 0 0 0 0 0 0 0 0 +# ---+-----------+---+-------+---+------------------------------- +# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT +# ---+-----------+---+-------+---+------------------------------- +name: MxBTST_MR_ARII +body: | + bb.0: + BTST8fd -1, $a1, $a0, $bd0, implicit-def $ccr + BTST8fd 0, $a0, $a0, $bd1, implicit-def $ccr + +... +--- # ARID +# ---------------+-----------+-----------+-----------+----------- +# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# ---------------+-----------+-----------+-----------+----------- +# 0 0 0 0 | REG | 1 0 0 | MODE | REG +# ---------------+-----------+-----------+-----------+----------- +# BTST8pd-SAME: 0 0 0 0 0 0 0 1 . 0 0 1 0 1 0 0 1 +# BTST8pd-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# -------------------------------+-------+-----------+----------- +# BTST8pd-SAME: 0 0 0 0 0 0 1 1 . 0 0 1 0 1 0 0 0 +# BTST8pd-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +name: MxBTST_MR_ARID +body: | + bb.0: + BTST8pd -1, $a1, $bd0, implicit-def $ccr + BTST8pd 0, $a0, $bd1, implicit-def $ccr + +... +--- # ARI +# ---------------+-----------+-----------+-----------+----------- +# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# ---------------+-----------+-----------+-----------+----------- +# 0 0 0 0 | REG | 1 0 0 | MODE | REG +# ---------------+-----------+-----------+-----------+----------- +# BTST8jd-SAME: 0 0 0 0 0 0 0 1 . 0 0 0 1 0 0 0 1 +# BTST8jd-SAME: 0 0 0 0 0 0 1 1 . 0 0 0 1 0 0 0 0 +name: MxBTST_MR_ARI +body: | + bb.0: + BTST8jd $a1, $bd0, implicit-def $ccr + BTST8jd $a0, $bd1, implicit-def $ccr + +... Index: llvm/test/CodeGen/M680x0/OBJ/Bits/Classes/MxBTST_RI.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Bits/Classes/MxBTST_RI.mir @@ -0,0 +1,25 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=BTST32di + +#------------------------------------------------------------------------------ +# MxBTST_RI class used for BTST operations, the source is in a data register and +# the bit number is a immediate. This instruction can only operate on 32 bits +#------------------------------------------------------------------------------ + + +# ---------------------------------------+-----------+----------- +# F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0 +# ---------------------------------------------------+----------- +# 0 0 0 0 1 0 0 0 0 0 | MODE | REG +# ---------------------------------------+-----------+----------- +# BTST32di: 0 0 0 0 1 0 0 0 . 0 0 0 0 0 0 0 0 +# BTST32di: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 1 +# --------------------------------------------------------------- +# BTST32di: 0 0 0 0 1 0 0 0 . 0 0 0 0 0 0 1 1 +# BTST32di: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +name: MxBTST_RI +body: | + bb.0: + BTST32di $d0, 1, implicit-def $ccr + BTST32di $d3, 0, implicit-def $ccr Index: llvm/test/CodeGen/M680x0/OBJ/Bits/Classes/MxBTST_RR.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Bits/Classes/MxBTST_RR.mir @@ -0,0 +1,22 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=BTST32dd + +#------------------------------------------------------------------------------ +# MxBTST_RR class used for BTST operations, where both the source and bit number +# are in registers. This instruction can only operate on 32 bits +#------------------------------------------------------------------------------ + + +# ---------------+-----------+-----------+-----------+----------- +# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# ---------------+-----------+-----------+-----------+----------- +# 0 0 0 0 | REG | 1 0 0 | MODE | REG +# ---------------+-----------+-----------+-----------+----------- +# BTST32dd: 0 0 0 0 0 0 1 1 . 0 0 0 0 0 0 0 0 +# BTST32dd: 0 0 0 0 0 0 0 1 . 0 0 0 0 0 0 1 1 +name: MxBTST_RR +body: | + bb.0: + BTST32dd $d0, $d1, implicit-def $ccr + BTST32dd $d3, $d0, implicit-def $ccr Index: llvm/test/CodeGen/M680x0/OBJ/Control/Classes/MxBRA.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Control/Classes/MxBRA.mir @@ -0,0 +1,49 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=BRA8,BRA16 + +#------------------------------------------------------------------------------ +# MxBRA unconditionally branches somewhere +#------------------------------------------------------------------------------ + +--- # MxBRA8 +# -------------------------------+------------------------------- +# F E D C B A 9 8 | 7 6 5 4 3 2 1 0 +# -------------------------------+------------------------------- +# 0 1 1 0 0 0 0 0 | 8-BIT DISPLACEMENT +# -------------------------------+------------------------------- +# BRA8: 0 1 1 0 0 0 0 0 . 0 0 0 0 0 0 0 1 +# BRA8-SAME: 0 1 1 0 0 0 0 0 . 0 0 1 0 1 0 1 0 +# +# NOTE MxBRA branches cannot encode 0 displacement, 0 in displacement instructs +# to use additional word. Also it cannot encode -1 since all 1s instruct to use +# two additional words to encode 32bit offset(since M68020). +name: MxBRA8 +body: | + bb.0: + BRA8 1, implicit $ccr + BRA8 42, implicit $ccr + +... +--- # MxBRA16 +# -------------------------------+------------------------------- +# F E D C B A 9 8 | 7 6 5 4 3 2 1 0 +# -------------------------------+------------------------------- +# 0 1 1 0 0 0 0 0 | 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# BRA16-SAME: 0 1 1 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# BRA16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# -------------------------------+------------------------------- +# BRA16-SAME: 0 1 1 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# BRA16-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# --------------------------------------------------------------- +# BRA16-SAME: 0 1 1 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# BRA16-SAME: 0 0 0 0 0 0 0 0 . 0 0 1 0 1 0 1 0 +name: MxBRA16 +body: | + bb.0: + BRA16 0, implicit $ccr + BRA16 -1, implicit $ccr + BRA16 42, implicit $ccr + +... Index: llvm/test/CodeGen/M680x0/OBJ/Control/Classes/MxBcc.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Control/Classes/MxBcc.mir @@ -0,0 +1,119 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=Bcc8,Bls8,Blt8,Beq8,Bmi8,Bne8,Bge8,Bcs8,\ +# RUN:Bpl8,Bgt8,Bhi8,Bvc8,Ble8,Bvs8,Bcc16,Bls16,Blt16,Beq16,Bmi16,Bne16,Bge16,\ +# RUN:Bcs16,Bpl16,Bgt16,Bhi16,Bvc16,Ble16,Bvs16 + +#------------------------------------------------------------------------------ +# MxScc branches if the condition is True +#------------------------------------------------------------------------------ + +--- # MxBcc8 +# ---------------+---------------+------------------------------- +# F E D C | B A 9 8 | 7 6 5 4 3 2 1 0 +# ---------------+---------------+------------------------------- +# 0 1 1 0 | CONDITION | 8-BIT DISPLACEMENT +# ---------------+---------------+------------------------------- +# Bhi8: 0 1 1 0 0 0 1 0 . 0 0 0 0 0 0 0 1 +# Bls8-SAME: 0 1 1 0 0 0 1 1 . 0 0 1 0 1 0 1 0 +# Bcc8-SAME: 0 1 1 0 0 1 0 0 . 0 0 0 0 0 0 0 1 +# Bcs8-SAME: 0 1 1 0 0 1 0 1 . 0 0 0 0 0 0 0 1 +# Bne8-SAME: 0 1 1 0 0 1 1 0 . 0 0 0 0 0 0 0 1 +# Beq8-SAME: 0 1 1 0 0 1 1 1 . 0 0 0 0 0 0 0 1 +# Bvc8-SAME: 0 1 1 0 1 0 0 0 . 0 0 0 0 0 0 0 1 +# Bvs8-SAME: 0 1 1 0 1 0 0 1 . 0 0 0 0 0 0 0 1 +# Bpl8-SAME: 0 1 1 0 1 0 1 0 . 0 0 0 0 0 0 0 1 +# Bmi8-SAME: 0 1 1 0 1 0 1 1 . 0 0 0 0 0 0 0 1 +# Bge8-SAME: 0 1 1 0 1 1 0 0 . 0 0 0 0 0 0 0 1 +# Blt8-SAME: 0 1 1 0 1 1 0 1 . 0 0 0 0 0 0 0 1 +# Bgt8-SAME: 0 1 1 0 1 1 1 0 . 0 0 0 0 0 0 0 1 +# Ble8-SAME: 0 1 1 0 1 1 1 1 . 0 0 0 0 0 0 0 1 +# +# NOTE MxBcc8 branches cannot encode 0 displacement, 0 in displacement instructs +# to use additional word. Also it cannot encode -1 since all 1s instruct to use +# two additional words to encode 32bit offset(since M68020). +name: MxBcc8 +body: | + bb.0: + Bhi8 1, implicit $ccr + Bls8 42, implicit $ccr + Bcc8 1, implicit $ccr + Bcs8 1, implicit $ccr + Bne8 1, implicit $ccr + Beq8 1, implicit $ccr + Bvc8 1, implicit $ccr + Bvs8 1, implicit $ccr + Bpl8 1, implicit $ccr + Bmi8 1, implicit $ccr + Bge8 1, implicit $ccr + Blt8 1, implicit $ccr + Bgt8 1, implicit $ccr + Ble8 1, implicit $ccr + +... +--- # MxBcc16 +# ---------------+---------------+------------------------------- +# F E D C | B A 9 8 | 7 6 5 4 3 2 1 0 +# ---------------+---------------+------------------------------- +# 0 1 1 0 | CONDITION | 0 0 0 0 0 0 0 0 +# ---------------+---------------+------------------------------- +# Bhi16-SAME: 0 1 1 0 0 0 1 0 . 0 0 0 0 0 0 0 0 +# Bhi16-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# --------------------------------------------------------------- +# Bls16-SAME: 0 1 1 0 0 0 1 1 . 0 0 0 0 0 0 0 0 +# Bls16-SAME: 0 0 0 0 0 0 0 0 . 0 0 1 0 1 0 1 0 +# --------------------------------------------------------------- +# Bcc16-SAME: 0 1 1 0 0 1 0 0 . 0 0 0 0 0 0 0 0 +# Bcc16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# Bcs16-SAME: 0 1 1 0 0 1 0 1 . 0 0 0 0 0 0 0 0 +# Bcs16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# Bne16-SAME: 0 1 1 0 0 1 1 0 . 0 0 0 0 0 0 0 0 +# Bne16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# Beq16-SAME: 0 1 1 0 0 1 1 1 . 0 0 0 0 0 0 0 0 +# Bge16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# Bvc16-SAME: 0 1 1 0 1 0 0 0 . 0 0 0 0 0 0 0 0 +# Bvc16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# Bvs16-SAME: 0 1 1 0 1 0 0 1 . 0 0 0 0 0 0 0 0 +# Bvs16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# Bpl16-SAME: 0 1 1 0 1 0 1 0 . 0 0 0 0 0 0 0 0 +# Bpl16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# Bmi16-SAME: 0 1 1 0 1 0 1 1 . 0 0 0 0 0 0 0 0 +# Bmi16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# Bge16-SAME: 0 1 1 0 1 1 0 0 . 0 0 0 0 0 0 0 0 +# Ble16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# Blt16-SAME: 0 1 1 0 1 1 0 1 . 0 0 0 0 0 0 0 0 +# Blt16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# Bgt16-SAME: 0 1 1 0 1 1 1 0 . 0 0 0 0 0 0 0 0 +# Bgt16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# Ble16-SAME: 0 1 1 0 1 1 1 1 . 0 0 0 0 0 0 0 0 +# Ble16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +name: MxBcc16 +body: | + bb.0: + Bhi16 -1, implicit $ccr + Bls16 42, implicit $ccr + Bcc16 0, implicit $ccr + Bcs16 0, implicit $ccr + Bne16 0, implicit $ccr + Beq16 0, implicit $ccr + Bvc16 0, implicit $ccr + Bvs16 0, implicit $ccr + Bpl16 0, implicit $ccr + Bmi16 0, implicit $ccr + Bge16 0, implicit $ccr + Blt16 0, implicit $ccr + Bgt16 0, implicit $ccr + Ble16 0, implicit $ccr + +... Index: llvm/test/CodeGen/M680x0/OBJ/Control/Classes/MxCALL.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Control/Classes/MxCALL.mir @@ -0,0 +1,88 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=CALLk,CALLq,CALLb,CALLj + +#------------------------------------------------------------------------------ +# MxCALL pushes address of the next instruction and jumps to the location +#------------------------------------------------------------------------------ + +--- # MxCALL_PCI +# ---------------------------------------+-----------+----------- +# F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0 +# ---------------------------------------+-----------+----------- +# 0 1 0 0 1 1 1 0 1 0 | MODE | REG +# ---------------------------------------+-----------+----------- +# CALLk: 0 1 0 0 1 1 1 0 . 1 0 1 1 1 0 1 1 +# CALLk-SAME: 1 0 0 0 1 0 0 0 . 0 0 0 0 0 0 0 0 +# ---------------------------------------+-----------+----------- +# CALLk-SAME: 0 1 0 0 1 1 1 0 . 1 0 1 1 1 0 1 1 +# CALLk-SAME: 1 0 0 0 1 0 0 0 . 1 1 1 1 1 1 1 1 +# ---------------------------------------+-----------+----------- +# CALLk-SAME: 0 1 0 0 1 1 1 0 . 1 0 1 1 1 0 1 1 +# CALLk-SAME: 1 0 0 0 1 0 0 0 . 0 0 1 0 1 0 1 0 +# ---+-----------+---+-------+---+------------------------------- +# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT +# ---+-----------+---+-------+---+------------------------------- +name: MxCALL_PCI +body: | + bb.0: + CALLk 0, $a0 + CALLk -1, $a0 + CALLk 42, $a0 + +... +--- # MxCALL_PCD +# ---------------------------------------+-----------+----------- +# F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0 +# ---------------------------------------+-----------+----------- +# 0 1 0 0 1 1 1 0 1 0 | MODE | REG +# ---------------------------------------+-----------+----------- +# CALLq-SAME: 0 1 0 0 1 1 1 0 . 1 0 1 1 1 0 1 0 +# CALLq-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# ---------------------------------------+-----------+----------- +# CALLq-SAME: 0 1 0 0 1 1 1 0 . 1 0 1 1 1 0 1 0 +# CALLq-SAME: 0 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +name: MxCALL_PCD +body: | + bb.0: + CALLq 0 + CALLq 32767 + +... +--- # MxCALL_ABS +# ---------------------------------------+-----------+----------- +# F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0 +# ---------------------------------------+-----------+----------- +# 0 1 0 0 1 1 1 0 1 0 | MODE | REG +# ---------------------------------------+-----------+----------- +# CALLb-SAME: 0 1 0 0 1 1 1 0 . 1 0 1 1 1 0 0 1 +# CALLb-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# CALLb-SAME: 0 0 0 0 0 0 0 0 . 0 0 1 0 1 0 1 0 +# ---------------------------------------+-----------+----------- +# CALLb-SAME: 0 1 0 0 1 1 1 0 . 1 0 1 1 1 0 0 1 +# CALLb-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# CALLb-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +name: MxCALL_ABS +body: | + bb.0: + CALLb 42 + CALLb -1 + +... +--- # MxCALL_ARI +# ---------------------------------------+-----------+----------- +# F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0 +# ---------------------------------------+-----------+----------- +# 0 1 0 0 1 1 1 0 1 0 | MODE | REG +# ---------------------------------------+-----------+----------- +# CALLj-SAME: 0 1 0 0 1 1 1 0 . 1 0 0 1 0 0 0 0 +# CALLj-SAME: 0 1 0 0 1 1 1 0 . 1 0 0 1 0 0 0 1 +# CALLj-SAME: 0 1 0 0 1 1 1 0 . 1 0 0 1 0 0 1 0 +name: MxCALL_ARI +body: | + bb.0: + CALLj $a0 + CALLj $a1 + CALLj $a2 + +... Index: llvm/test/CodeGen/M680x0/OBJ/Control/Classes/MxJMP.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Control/Classes/MxJMP.mir @@ -0,0 +1,21 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=JMP32j + +#------------------------------------------------------------------------------ +# MxJMP encodes unconditional jump +#------------------------------------------------------------------------------ + +--- # MxJMP_ARI +# ---------------------------------------+-----------+----------- +# F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0 +# ---------------------------------------+-----------+----------- +# 0 1 0 0 1 1 1 0 1 1 | MODE | REG +# ---------------------------------------+-----------+----------- +# JMP32j: 0 1 0 0 1 1 1 0 . 1 1 0 1 0 0 0 0 +name: MxJMP_ARI +body: | + bb.0: + JMP32j $a0 + +... Index: llvm/test/CodeGen/M680x0/OBJ/Control/Classes/MxNOP.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Control/Classes/MxNOP.mir @@ -0,0 +1,16 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=NOP + +#------------------------------------------------------------------------------ +# MxNOP +#------------------------------------------------------------------------------ + +# --------------------------------------------------------------- +# F E D C B A 9 8 7 6 5 4 3 2 1 0 +# --------------------------------------------------------------- +# NOP: 0 1 0 0 1 1 1 0 . 0 1 1 1 0 0 0 1 +name: MxNOP +body: | + bb.0: + NOP Index: llvm/test/CodeGen/M680x0/OBJ/Control/Classes/MxRTS.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Control/Classes/MxRTS.mir @@ -0,0 +1,16 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=RTS + +#------------------------------------------------------------------------------ +# MxRTS pops return address from the stack and jumps there +#------------------------------------------------------------------------------ + +# --------------------------------------------------------------- +# F E D C B A 9 8 7 6 5 4 3 2 1 0 +# --------------------------------------------------------------- +# RTS: 0 1 0 0 1 1 1 0 . 0 1 1 1 0 1 0 1 +name: MxRTS +body: | + bb.0: + RTS Index: llvm/test/CodeGen/M680x0/OBJ/Control/Classes/MxScc.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Control/Classes/MxScc.mir @@ -0,0 +1,128 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=SETd8cc,SETd8ls,SETd8lt,SETd8eq,SETd8mi,\ +# RUN:SETd8f,SETd8ne,SETd8ge,SETd8cs,SETd8pl,SETd8gt,SETd8t,SETd8hi,SETd8vc,\ +# RUN:SETd8le,SETd8vs,SETp8cc,SETp8ls,SETp8lt,SETp8eq,SETp8mi,SETp8f,SETp8ne,\ +# RUN:SETp8ge,SETp8cs,SETp8pl,SETp8gt,SETp8t,SETp8hi,SETp8vc,SETp8le,SETp8vs + +#------------------------------------------------------------------------------ +# MxScc sets byte filled with 1s or 0s based on cc condition +#------------------------------------------------------------------------------ + +--- # MxScc_D +# ---------------+---------------+-------+-----------+----------- +# F E D C | B A 9 8 | 7 6 | 5 4 3 | 2 1 0 +# ---------------+---------------+-------+-----------+----------- +# 0 1 0 1 | CONDITION | 1 1 | MODE | REG +# ---------------+---------------+-------+-----------+----------- +# SETd8t: 0 1 0 1 0 0 0 0 . 1 1 0 0 0 0 0 0 +# SETd8f-SAME: 0 1 0 1 0 0 0 1 . 1 1 0 0 0 0 0 1 +# SETd8hi-SAME: 0 1 0 1 0 0 1 0 . 1 1 0 0 0 0 1 0 +# SETd8ls-SAME: 0 1 0 1 0 0 1 1 . 1 1 0 0 0 0 1 1 +# SETd8cc-SAME: 0 1 0 1 0 1 0 0 . 1 1 0 0 0 1 0 0 +# SETd8cs-SAME: 0 1 0 1 0 1 0 1 . 1 1 0 0 0 1 0 1 +# SETd8ne-SAME: 0 1 0 1 0 1 1 0 . 1 1 0 0 0 1 1 0 +# SETd8eq-SAME: 0 1 0 1 0 1 1 1 . 1 1 0 0 0 1 1 1 +# SETd8vc-SAME: 0 1 0 1 1 0 0 0 . 1 1 0 0 0 0 0 0 +# SETd8vs-SAME: 0 1 0 1 1 0 0 1 . 1 1 0 0 0 0 0 0 +# SETd8pl-SAME: 0 1 0 1 1 0 1 0 . 1 1 0 0 0 0 0 0 +# SETd8mi-SAME: 0 1 0 1 1 0 1 1 . 1 1 0 0 0 0 0 0 +# SETd8ge-SAME: 0 1 0 1 1 1 0 0 . 1 1 0 0 0 0 0 0 +# SETd8lt-SAME: 0 1 0 1 1 1 0 1 . 1 1 0 0 0 0 0 0 +# SETd8gt-SAME: 0 1 0 1 1 1 1 0 . 1 1 0 0 0 0 0 0 +# SETd8le-SAME: 0 1 0 1 1 1 1 1 . 1 1 0 0 0 0 0 0 +name: MxScc_D +body: | + bb.0: + $bd0 = SETd8t implicit $ccr + $bd1 = SETd8f implicit $ccr + $bd2 = SETd8hi implicit $ccr + $bd3 = SETd8ls implicit $ccr + $bd4 = SETd8cc implicit $ccr + $bd5 = SETd8cs implicit $ccr + $bd6 = SETd8ne implicit $ccr + $bd7 = SETd8eq implicit $ccr + $bd0 = SETd8vc implicit $ccr + $bd0 = SETd8vs implicit $ccr + $bd0 = SETd8pl implicit $ccr + $bd0 = SETd8mi implicit $ccr + $bd0 = SETd8ge implicit $ccr + $bd0 = SETd8lt implicit $ccr + $bd0 = SETd8gt implicit $ccr + $bd0 = SETd8le implicit $ccr + +... +--- # MxScc_ARID +# ---------------+---------------+-------+-----------+----------- +# F E D C | B A 9 8 | 7 6 | 5 4 3 | 2 1 0 +# ---------------+---------------+-------+-----------+----------- +# 0 1 0 1 | CONDITION | 1 1 | MODE | REG +# ---------------+---------------+-------+-----------+----------- +# SETp8t-SAME: 0 1 0 1 0 0 0 0 . 1 1 1 0 1 0 0 0 +# SETp8t-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# --------------------------------------------------------------- +# SETp8f-SAME: 0 1 0 1 0 0 0 1 . 1 1 1 0 1 0 0 1 +# SETp8f-SAME: 0 0 0 0 0 0 0 0 . 0 0 1 0 1 0 1 0 +# --------------------------------------------------------------- +# SETp8hi-SAME: 0 1 0 1 0 0 1 0 . 1 1 1 0 1 0 1 0 +# SETp8hi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# SETp8ls-SAME: 0 1 0 1 0 0 1 1 . 1 1 1 0 1 0 1 1 +# SETp8ls-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# SETp8cc-SAME: 0 1 0 1 0 1 0 0 . 1 1 1 0 1 1 0 0 +# SETp8cc-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# SETp8cs-SAME: 0 1 0 1 0 1 0 1 . 1 1 1 0 1 1 0 1 +# SETp8cs-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# SETp8ne-SAME: 0 1 0 1 0 1 1 0 . 1 1 1 0 1 1 1 0 +# SETp8ne-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# SETp8eq-SAME: 0 1 0 1 0 1 1 1 . 1 1 1 0 1 0 0 0 +# SETp8eq-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# SETp8vc-SAME: 0 1 0 1 1 0 0 0 . 1 1 1 0 1 0 0 0 +# SETp8vc-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# SETp8vs-SAME: 0 1 0 1 1 0 0 1 . 1 1 1 0 1 0 0 0 +# SETp8vs-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# SETp8pl-SAME: 0 1 0 1 1 0 1 0 . 1 1 1 0 1 0 0 0 +# SETp8pl-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# SETp8mi-SAME: 0 1 0 1 1 0 1 1 . 1 1 1 0 1 0 0 0 +# SETp8mi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# SETp8ge-SAME: 0 1 0 1 1 1 0 0 . 1 1 1 0 1 0 0 0 +# SETp8ge-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# SETp8lt-SAME: 0 1 0 1 1 1 0 1 . 1 1 1 0 1 0 0 0 +# SETp8lt-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# SETp8gt-SAME: 0 1 0 1 1 1 1 0 . 1 1 1 0 1 0 0 0 +# SETp8gt-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# SETp8le-SAME: 0 1 0 1 1 1 1 1 . 1 1 1 0 1 0 0 0 +# SETp8le-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +name: MxScc_ARID +body: | + bb.0: + SETp8t -1, $a0, implicit $ccr + SETp8f 42, $a1, implicit $ccr + SETp8hi 0, $a2, implicit $ccr + SETp8ls 0, $a3, implicit $ccr + SETp8cc 0, $a4, implicit $ccr + SETp8cs 0, $a5, implicit $ccr + SETp8ne 0, $a6, implicit $ccr + SETp8eq 0, $a0, implicit $ccr + SETp8vc 0, $a0, implicit $ccr + SETp8vs 0, $a0, implicit $ccr + SETp8pl 0, $a0, implicit $ccr + SETp8mi 0, $a0, implicit $ccr + SETp8ge 0, $a0, implicit $ccr + SETp8lt 0, $a0, implicit $ccr + SETp8gt 0, $a0, implicit $ccr + SETp8le 0, $a0, implicit $ccr + +... Index: llvm/test/CodeGen/M680x0/OBJ/Control/branch-pc-rel.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Control/branch-pc-rel.mir @@ -0,0 +1,31 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj \ +# RUN: -code-model=small -relocation-model=pic -o - \ +# RUN: | extract-section .text -h \ +# RUN: | FileCheck %s -check-prefixes=x00 + +#------------------------------------------------------------------------------ +# This test checks whether branches have correct offset +#------------------------------------------------------------------------------ + +--- # TEXT +# 0 x00: 6702 +# 2 x00-SAME: 6008 +# 4 x00-SAME: d0bc 0000 0000 +# A x00-SAME: 4e75 +# C x00-SAME: d0bc 0000 0001 +# 12 x00-SAME: 4e75 +name: TEXT +body: | + bb.0: + successors: %bb.2,%bb.1 + + Beq8 %bb.1, implicit $ccr + BRA8 %bb.2 + bb.1: + $d0 = ADD32ri $d0, 0, implicit-def $ccr + RET 0, $d0 + bb.2: + $d0 = ADD32ri $d0, 1, implicit-def $ccr + RET 0, $d0 + +... Index: llvm/test/CodeGen/M680x0/OBJ/Control/call-pc-rel.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Control/call-pc-rel.mir @@ -0,0 +1,66 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj \ +# RUN: -code-model=small -relocation-model=pic -o - \ +# RUN: | extract-section .text -h \ +# RUN: | FileCheck %s -check-prefixes=x00 + +#------------------------------------------------------------------------------ +# Tests PC-Relative Calls' offsets. The rest requires relocation and tested +# appropriately elsewhere. +#------------------------------------------------------------------------------ + +# +# +# 00 x00: 4e71 +# 02 x00-SAME: 4e75 +# +# +# 04 x00-SAME: 4ebb 08fa +# 08 x00-SAME: 4ebb 080a +# +# +# 0c x00-SAME: 4eba fff2 +# 10 x00-SAME: 4eba 0002 +# +# +# 14 x00-SAME: 4e71 +# 16 x00-SAME: 4e75 +--- | + + define dso_local void @BACKWARD() { entry: ret void } + define dso_local void @PCI() { entry: ret void } + define dso_local void @PCD() { entry: ret void } + define dso_local void @FORWARD() { entry: ret void } + +... +--- # BACKWARD +name: BACKWARD +body: | + bb.0: + NOP + RTS + +... +--- # PCI +name: PCI +body: | + bb.0: + CALLk @BACKWARD, $d0 + CALLk @FORWARD, $d0 + +... +--- # PCD +name: PCD +body: | + bb.0: + CALLq @BACKWARD + CALLq @FORWARD + +... +--- # FORWARD +name: FORWARD +body: | + bb.0: + NOP + RTS + +... Index: llvm/test/CodeGen/M680x0/OBJ/Data/Classes/MxLEA.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Data/Classes/MxLEA.mir @@ -0,0 +1,65 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=LEA32q,LEA32f,LEA32p + +#------------------------------------------------------------------------------ +# MxLEA is used to calculate effective address and load it into a address reg +#------------------------------------------------------------------------------ + +--- # PCD +# --------------------------------------------------------------- +# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# --------------------------------------------------------------- +# 0 1 0 0 | DST REG | 1 1 1 | MODE | REG +# --------------------------------------------------------------- +# LEA32q: 0 1 0 0 0 0 0 1 . 1 1 1 1 1 0 1 0 +# LEA32q-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# LEA32q-SAME: 0 1 0 0 0 0 0 1 . 1 1 1 1 1 0 1 0 +# LEA32q-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +name: MxLEA_PCD +body: | + bb.0: + $a0 = LEA32q 0, implicit-def $ccr + $a0 = LEA32q -1, implicit-def $ccr + +... +--- # ARII +# --------------------------------------------------------------- +# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# --------------------------------------------------------------- +# 0 1 0 0 | DST REG | 1 1 1 | MODE | REG +# --------------------------------------------------------------- +# LEA32f-SAME: 0 1 0 0 0 0 0 1 . 1 1 1 1 0 0 0 1 +# LEA32f-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# LEA32f-SAME: 0 1 0 0 0 0 1 1 . 1 1 1 1 0 0 1 0 +# LEA32f-SAME: 1 0 1 0 1 0 0 0 . 0 0 0 0 0 0 0 0 +# ---+-----------+---+-------+---+------------------------------- +# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT +# ---+-----------+---+-------+---+------------------------------- +name: MxLEA_ARII +body: | + bb.0: + $a0 = LEA32f 0, $a1, $d1, implicit-def $ccr + $a1 = LEA32f 0, $a2, $a2, implicit-def $ccr + +... +--- # ARID +# --------------------------------------------------------------- +# F E D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# --------------------------------------------------------------- +# 0 1 0 0 | DST REG | 1 1 1 | MODE | REG +# --------------------------------------------------------------- +# LEA32p-SAME: 0 1 0 0 0 0 0 1 . 1 1 1 0 1 0 0 1 +# LEA32p-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# --------------------------------------------------------------- +# LEA32p-SAME: 0 1 0 0 0 0 0 1 . 1 1 1 0 1 0 0 1 +# LEA32p-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +name: MxLEA_ARID +body: | + bb.0: + $a0 = LEA32p -1, $a1, implicit-def $ccr + $a0 = LEA32p -1, $a1, implicit-def $ccr + +... Index: llvm/test/CodeGen/M680x0/OBJ/Data/Classes/MxMOVEM_MR.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Data/Classes/MxMOVEM_MR.mir @@ -0,0 +1,52 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=MOVM32pm,MOVM32jm + +#------------------------------------------------------------------------------ +# MxMOVEM_MR is used to store a list of register sequentially into a memory +# location +#------------------------------------------------------------------------------ + +--- # ARID +# -------------------+---+-----------+---+-----------+----------- +# F E D C B | A | 9 8 7 | 6 | 5 4 3 | 2 1 0 +# -------------------+---+-----------+---+-----------+----------- +# 0 1 0 0 1 | D | 0 0 1 | S | MODE | REG +# -------------------+---+-----------+---+-----------+----------- +# REGISTER LIST MASK +# --------------------------------------------------------------- +# MOVM32pm: 0 1 0 0 1 0 0 0 . 1 1 1 0 1 0 0 1 +# MOVM32pm-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 1 +# MOVM32pm-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# MOVM32pm-SAME: 0 1 0 0 1 0 0 0 . 1 1 1 0 1 0 0 1 +# MOVM32pm-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 1 1 +# MOVM32pm-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +name: MxMOVEM_MR_ARID +body: | + bb.0: + MOVM32pm 0, $a1, 1 + MOVM32pm -1, $a1, 3 + +... +--- # ARI +# -------------------+---+-----------+---+-----------+----------- +# F E D C B | A | 9 8 7 | 6 | 5 4 3 | 2 1 0 +# -------------------+---+-----------+---+-----------+----------- +# 0 1 0 0 1 | D | 0 0 1 | S | MODE | REG +# -------------------+---+-----------+---+-----------+----------- +# MOVM32jm-SAME: 0 1 0 0 1 0 0 0 . 1 1 0 1 0 0 0 1 +# MOVM32jm-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 1 +# --------------------------------------------------------------- +# MOVM32jm-SAME: 0 1 0 0 1 0 0 0 . 1 1 0 1 0 0 0 1 +# MOVM32jm-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 1 1 +# --------------------------------------------------------------- +# REGISTER LIST MASK +# --------------------------------------------------------------- +name: MxMOVEM_MR_ARI +body: | + bb.0: + MOVM32jm $a1, 1 + MOVM32jm $a1, 3 + +... Index: llvm/test/CodeGen/M680x0/OBJ/Data/Classes/MxMOVEM_RM.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Data/Classes/MxMOVEM_RM.mir @@ -0,0 +1,52 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=MOVM32mp,MOVM32mj + +#------------------------------------------------------------------------------ +# MxMOVEM_RM is used to load a list of registers sequentially from a memory +# location +#------------------------------------------------------------------------------ + +--- # ARID +# -------------------+---+-----------+---+-----------+----------- +# F E D C B | A | 9 8 7 | 6 | 5 4 3 | 2 1 0 +# -------------------+---+-----------+---+-----------+----------- +# 0 1 0 0 1 | D | 0 0 1 | S | MODE | REG +# -------------------+---+-----------+---+-----------+----------- +# REGISTER LIST MASK +# --------------------------------------------------------------- +# MOVM32mp: 0 1 0 0 1 1 0 0 . 1 1 1 0 1 0 0 1 +# MOVM32mp-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 1 +# MOVM32mp-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# MOVM32mp-SAME: 0 1 0 0 1 1 0 0 . 1 1 1 0 1 0 0 1 +# MOVM32mp-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 1 1 +# MOVM32mp-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +name: MxMOVEM_RM_ARID +body: | + bb.0: + MOVM32mp 1, 0, $a1 + MOVM32mp 3, -1, $a1 + +... +--- # ARI +# -------------------+---+-----------+---+-----------+----------- +# F E D C B | A | 9 8 7 | 6 | 5 4 3 | 2 1 0 +# -------------------+---+-----------+---+-----------+----------- +# 0 1 0 0 1 | D | 0 0 1 | S | MODE | REG +# -------------------+---+-----------+---+-----------+----------- +# MOVM32mj-SAME: 0 1 0 0 1 1 0 0 . 1 1 0 1 0 0 0 1 +# MOVM32mj-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 1 +# --------------------------------------------------------------- +# MOVM32mj-SAME: 0 1 0 0 1 1 0 0 . 1 1 0 1 0 0 0 1 +# MOVM32mj-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 1 1 +# --------------------------------------------------------------- +# REGISTER LIST MASK +# --------------------------------------------------------------- +name: MxMOVEM_RM_ARI +body: | + bb.0: + MOVM32mj 1, $a1 + MOVM32mj 3, $a1 + +... Index: llvm/test/CodeGen/M680x0/OBJ/Data/Classes/MxMoveCCR.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Data/Classes/MxMoveCCR.mir @@ -0,0 +1,34 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=MOV16cd,MOV16dc + +#------------------------------------------------------------------------------ +# MxMoveToCCR and MxMoveFromCCR load/store condition flag register +#------------------------------------------------------------------------------ + +--- # To CCR +# ---------------------------------------+-----------+----------- +# F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0 +# ---------------------------------------+-----------+----------- +# 0 1 0 0 0 1 0 0 1 1 | MODE | REG +# ---------------------------------------+-----------+----------- +# MOV16cd: 0 1 0 0 0 1 0 0 . 1 1 0 0 0 0 0 1 +name: MxMoveToCCR +body: | + bb.0: + $ccr = MOV16cd $wd1, implicit-def $ccr + +... +--- # From CCR +# ---------------------------------------+-----------+----------- +# F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0 +# ---------------------------------------+-----------+----------- +# 0 1 0 0 0 0 1 0 1 1 | MODE | REG +# ---------------------------------------+-----------+----------- +# MOV16cd-SAME: 0 1 0 0 0 0 1 0 . 1 1 0 0 0 0 0 1 +name: MxMoveFromCCR +body: | + bb.0: + $wd1 = MOV16dc $ccr, implicit $ccr + +... Index: llvm/test/CodeGen/M680x0/OBJ/Data/Classes/MxMove_MI.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Data/Classes/MxMove_MI.mir @@ -0,0 +1,97 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=MOV8fi,MOV32fi,MOV8pi,MOV32pi,MOV8ji,MOV32ji + +#------------------------------------------------------------------------------ +# MxMove_MI is used for moving immediate to memory +#------------------------------------------------------------------------------ + +--- # ARII +# ---------------------------+-----------+-----------+----------- +# F E | D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# -------+-------+-----------+-----------+-----------+----------- +# | | DESTINATION | SOURCE +# 0 0 | SIZE | REG | MODE | MODE | REG +# -------+-------+-----------+-----------+-----------+----------- +# MOV8fi: 0 0 0 1 0 0 0 1 . 1 0 1 1 1 1 0 0 +# MOV8fi-SAME: 0 0 0 0 0 0 0 0 . 1 1 1 1 1 1 1 1 +# MOV8fi-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# MOV8fi-SAME: 0 0 0 1 0 0 0 1 . 1 0 1 1 1 1 0 0 +# MOV8fi-SAME: 0 0 0 0 0 0 0 0 . 0 0 1 0 1 0 1 0 +# MOV8fi-SAME: 0 0 0 1 1 0 0 0 . 1 1 1 1 1 1 1 1 +# --------------------------------------------------------------- +# MOV32fi-SAME: 0 0 1 0 0 0 1 1 . 1 0 1 1 1 1 0 0 +# MOV32fi-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# MOV32fi-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# MOV32fi-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# MOV32fi-SAME: 0 0 1 0 0 1 0 1 . 1 0 1 1 1 1 0 0 +# MOV32fi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# MOV32fi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# MOV32fi-SAME: 1 0 1 0 1 0 0 0 . 0 0 0 0 0 0 0 0 +# ---+-----------+---+-------+---+------------------------------- +# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT +# ---+-----------+---+-------+---+------------------------------- +name: MxMove_MI_ARII +body: | + bb.0: + MOV8fi 0, $a0, $d1, -1, implicit-def $ccr + MOV8fi -1, $a0, $d1, 42, implicit-def $ccr + MOV32fi 0, $a1, $d1, -1, implicit-def $ccr + MOV32fi 0, $a2, $a2, 0, implicit-def $ccr + +... +--- # ARID +# ---------------------------+-----------+-----------+----------- +# F E | D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# -------+-------+-----------+-----------+-----------+----------- +# | | DESTINATION | SOURCE +# 0 0 | SIZE | REG | MODE | MODE | REG +# -------+-------+-----------+-----------+-----------+----------- +# MOV8pi-SAME: 0 0 0 1 0 0 0 1 . 0 1 1 1 1 1 0 0 +# MOV8pi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# MOV8pi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# MOV32pi-SAME: 0 0 1 0 0 0 1 1 . 0 1 1 1 1 1 0 0 +# MOV32pi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# MOV32pi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# MOV32pi-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# --------------------------------------------------------------- +# MOV32pi-SAME: 0 0 1 0 0 0 1 1 . 0 1 1 1 1 1 0 0 +# MOV32pi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# MOV32pi-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# MOV32pi-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +name: MxMove_MI_ARID +body: | + bb.0: + MOV8pi 0, $a0, 0, implicit-def $ccr + MOV32pi -1, $a1, 0, implicit-def $ccr + MOV32pi -1, $a1, 0, implicit-def $ccr + +... +--- # ARI +# ---------------------------+-----------+-----------+----------- +# F E | D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# -------+-------+-----------+-----------+-----------+----------- +# | | DESTINATION | SOURCE +# 0 0 | SIZE | REG | MODE | MODE | REG +# -------+-------+-----------+-----------+-----------+----------- +# MOV8ji-SAME: 0 0 0 1 0 0 0 0 . 1 0 1 1 1 1 0 0 +# MOV8ji-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# MOV32ji-SAME: 0 0 1 0 0 0 1 0 . 1 0 1 1 1 1 0 0 +# MOV32ji-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# MOV32ji-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# MOV32ji-SAME: 0 0 1 0 0 0 1 0 . 1 0 1 1 1 1 0 0 +# MOV32ji-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# MOV32ji-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +name: MxMove_MI_ARI +body: | + bb.0: + MOV8ji $a0, 0, implicit-def $ccr + MOV32ji $a1, 0, implicit-def $ccr + MOV32ji $a1, 0, implicit-def $ccr + +... Index: llvm/test/CodeGen/M680x0/OBJ/Data/Classes/MxMove_MM.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Data/Classes/MxMove_MM.mir @@ -0,0 +1,212 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=MOV8jk,MOV32jk,MOV8jq,MOV32jq,MOV8ff,MOV32ff,\ +# RUN:MOV8pp,MOV32pp,MOV8jj,MOV32jj,MOV8oo,MOV32oo,MOV8ee,MOV32ee,MOV8bb,MOV32bb + +#------------------------------------------------------------------------------ +# MxMove_MM is used for moving data from memory to memory +#------------------------------------------------------------------------------ + +--- # ARI <- PCI +# ---------------------------+-----------+-----------+----------- +# F E | D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# -------+-------+-----------+-----------+-----------+----------- +# | | DESTINATION | SOURCE +# 0 0 | SIZE | REG | MODE | MODE | REG +# -------+-------+-----------+-----------+-----------+----------- +# MOV8jk: 0 0 0 1 0 0 0 0 . 1 0 1 1 1 0 1 1 +# MOV8jk-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# MOV8jk-SAME: 0 0 0 1 0 0 0 0 . 1 0 1 1 1 0 1 1 +# MOV8jk-SAME: 0 0 0 1 1 0 0 0 . 1 1 1 1 1 1 1 1 +# --------------------------------------------------------------- +# MOV32jk-SAME: 0 0 1 0 0 0 0 0 . 1 0 1 1 1 0 1 1 +# MOV32jk-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# MOV32jk-SAME: 0 0 1 0 0 0 1 0 . 1 0 1 1 1 0 1 1 +# MOV32jk-SAME: 1 0 1 0 1 0 0 0 . 0 0 0 0 0 0 0 0 +# ---+-----------+---+-------+---+------------------------------- +# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT +# ---+-----------+---+-------+---+------------------------------- +name: MxMove_RM_ARI_PCI +body: | + bb.0: + MOV8jk $a0, 0, $d1, implicit-def $ccr + MOV8jk $a0, -1, $d1, implicit-def $ccr + MOV32jk $a0, 0, $d1, implicit-def $ccr + MOV32jk $a1, 0, $a2, implicit-def $ccr + +... +--- # ARI <- PCD +# ---------------------------+-----------+-----------+----------- +# F E | D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# -------+-------+-----------+-----------+-----------+----------- +# | | DESTINATION | SOURCE +# 0 0 | SIZE | REG | MODE | MODE | REG +# -------+-------+-----------+-----------+-----------+----------- +# MOV8jq-SAME: 0 0 0 1 0 0 0 0 . 1 0 1 1 1 0 1 0 +# MOV8jq-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# MOV32jq-SAME: 0 0 1 0 0 0 0 0 . 1 0 1 1 1 0 1 0 +# MOV32jq-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# --------------------------------------------------------------- +# MOV32jq-SAME: 0 0 1 0 0 0 0 0 . 1 0 1 1 1 0 1 0 +# MOV32jq-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +name: MxMove_RM_PCD +body: | + bb.0: + MOV8jq $a0, 0, implicit-def $ccr + MOV32jq $a0, -1, implicit-def $ccr + MOV32jq $a0, -1, implicit-def $ccr + +... +--- # ARII <- ARII +# ---------------------------+-----------+-----------+----------- +# F E | D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# -------+-------+-----------+-----------+-----------+----------- +# | | DESTINATION | SOURCE +# 0 0 | SIZE | REG | MODE | MODE | REG +# -------+-------+-----------+-----------+-----------+----------- +# MOV8ff: 0 0 0 1 0 0 0 1 . 1 0 1 1 0 0 0 0 +# MOV8ff-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0 +# MOV8ff-SAME: 0 0 0 1 1 0 0 0 . 1 1 1 1 1 1 1 1 +# --------------------------------------------------------------- +# MOV8ff-SAME: 0 0 0 1 0 0 0 1 . 1 0 1 1 0 0 0 0 +# MOV8ff-SAME: 0 0 0 1 1 0 0 0 . 1 1 1 1 1 1 1 1 +# MOV8ff-SAME: 0 0 0 1 1 0 0 0 . 1 1 1 1 1 1 1 1 +# --------------------------------------------------------------- +# MOV32ff-SAME: 0 0 1 0 0 0 1 1 . 1 0 1 1 0 0 0 1 +# MOV32ff-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0 +# MOV32ff-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# MOV32ff-SAME: 0 0 1 0 0 1 0 1 . 1 0 1 1 0 0 1 0 +# MOV32ff-SAME: 1 0 1 0 1 0 0 0 . 0 0 1 0 1 0 1 0 +# MOV32ff-SAME: 1 0 1 0 1 0 0 0 . 0 0 0 0 0 0 0 0 +# ---+-----------+---+-------+---+------------------------------- +# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT +# ---+-----------+---+-------+---+------------------------------- +name: MxMove_RM_ARII_ARII +body: | + bb.0: + MOV8ff -1, $a0, $d1, 0, $a0, $d1, implicit-def $ccr + MOV8ff -1, $a0, $d1, -1, $a0, $d1, implicit-def $ccr + MOV32ff 0, $a1, $d1, 0, $a1, $d1, implicit-def $ccr + MOV32ff 0, $a2, $a2, 42, $a2, $a2, implicit-def $ccr + +... +--- # ARID <- ARID +# ---------------------------+-----------+-----------+----------- +# F E | D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# -------+-------+-----------+-----------+-----------+----------- +# | | DESTINATION | SOURCE +# 0 0 | SIZE | REG | MODE | MODE | REG +# -------+-------+-----------+-----------+-----------+----------- +# MOV8pp-SAME: 0 0 0 1 0 0 0 1 . 0 1 1 0 1 0 0 0 +# MOV8pp-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# MOV8pp-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# MOV32pp-SAME: 0 0 1 0 0 0 1 1 . 0 1 1 0 1 0 0 1 +# MOV32pp-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# MOV32pp-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# MOV32pp-SAME: 0 0 1 0 0 0 1 1 . 0 1 1 0 1 0 0 1 +# MOV32pp-SAME: 0 0 0 0 0 0 0 0 . 0 0 1 0 1 0 1 0 +# MOV32pp-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +name: MxMove_RM_ARID +body: | + bb.0: + MOV8pp 0, $a0, 0, $a0, implicit-def $ccr + MOV32pp 0, $a1, -1, $a1, implicit-def $ccr + MOV32pp -1, $a1, 42, $a1, implicit-def $ccr + +... +--- # ARIPD <- ARIPD +# ---------------------------+-----------+-----------+----------- +# F E | D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# -------+-------+-----------+-----------+-----------+----------- +# | | DESTINATION | SOURCE +# 0 0 | SIZE | REG | MODE | MODE | REG +# -------+-------+-----------+-----------+-----------+----------- +# MOV8ee-SAME: 0 0 0 1 0 0 0 1 . 0 0 1 0 0 0 0 0 +# --------------------------------------------------------------- +# MOV32ee-SAME: 0 0 1 0 0 0 1 1 . 0 0 1 0 0 0 0 1 +# --------------------------------------------------------------- +# MOV32ee-SAME: 0 0 1 0 0 0 1 1 . 0 0 1 0 0 0 0 1 +name: MxMove_RM_ARIPD +body: | + bb.0: + MOV8ee $a0, $a0, implicit-def $ccr + MOV32ee $a1, $a1, implicit-def $ccr + MOV32ee $a1, $a1, implicit-def $ccr + +... +--- # ARIPI <- ARIPI +# ---------------------------+-----------+-----------+----------- +# F E | D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# -------+-------+-----------+-----------+-----------+----------- +# | | DESTINATION | SOURCE +# 0 0 | SIZE | REG | MODE | MODE | REG +# -------+-------+-----------+-----------+-----------+----------- +# MOV8oo-SAME: 0 0 0 1 0 0 0 0 . 1 1 0 1 1 0 0 0 +# --------------------------------------------------------------- +# MOV32oo-SAME: 0 0 1 0 0 0 1 0 . 1 1 0 1 1 0 0 1 +# --------------------------------------------------------------- +# MOV32oo-SAME: 0 0 1 0 0 0 1 0 . 1 1 0 1 1 0 0 1 +name: MxMove_RM_ARIPI +body: | + bb.0: + MOV8oo $a0, $a0, implicit-def $ccr + MOV32oo $a1, $a1, implicit-def $ccr + MOV32oo $a1, $a1, implicit-def $ccr + +... +--- # ARI <- ARI +# ---------------------------+-----------+-----------+----------- +# F E | D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# -------+-------+-----------+-----------+-----------+----------- +# | | DESTINATION | SOURCE +# 0 0 | SIZE | REG | MODE | MODE | REG +# -------+-------+-----------+-----------+-----------+----------- +# MOV8jj-SAME: 0 0 0 1 0 0 0 0 . 1 0 0 1 0 0 0 0 +# --------------------------------------------------------------- +# MOV32jj-SAME: 0 0 1 0 0 0 1 0 . 1 0 0 1 0 0 0 1 +# --------------------------------------------------------------- +# MOV32jj-SAME: 0 0 1 0 0 0 1 0 . 1 0 0 1 0 0 0 1 +name: MxMove_RM_ARI +body: | + bb.0: + MOV8jj $a0, $a0, implicit-def $ccr + MOV32jj $a1, $a1, implicit-def $ccr + MOV32jj $a1, $a1, implicit-def $ccr + +... +--- # ABS <- ABS +# ---------------------------+-----------+-----------+----------- +# F E | D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# -------+-------+-----------+-----------+-----------+----------- +# | | DESTINATION | SOURCE +# 0 0 | SIZE | REG | MODE | MODE | REG +# -------+-------+-----------+-----------+-----------+----------- +# MOV8bb-SAME: 0 0 0 1 0 0 1 1 . 1 1 1 1 1 0 0 1 +# MOV8bb-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# MOV8bb-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# MOV32bb-SAME: 0 0 1 0 0 0 1 1 . 1 1 1 1 1 0 0 1 +# MOV32bb-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# MOV32bb-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# MOV32bb-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# MOV32bb-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# --------------------------------------------------------------- +# MOV32bb-SAME: 0 0 1 0 0 0 1 1 . 1 1 1 1 1 0 0 1 +# MOV32bb-SAME: 0 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# MOV32bb-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# MOV32bb-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# MOV32bb-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +name: MxMove_RM_ABS +body: | + bb.0: + MOV8bb 0, -1, implicit-def $ccr + MOV32bb -1, 0, implicit-def $ccr + MOV32bb 0, 2147483647, implicit-def $ccr + +... Index: llvm/test/CodeGen/M680x0/OBJ/Data/Classes/MxMove_MR.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Data/Classes/MxMove_MR.mir @@ -0,0 +1,81 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=MOV8fd,MOV32fr,MOV8pd,MOV32pr,MOV8jd,MOV32jr + +#------------------------------------------------------------------------------ +# MxMove_MR is used for moving data from register to memory +#------------------------------------------------------------------------------ + +--- # ARII +# ---------------------------+-----------+-----------+----------- +# F E | D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# -------+-------+-----------+-----------+-----------+----------- +# | | DESTINATION | SOURCE +# 0 0 | SIZE | REG | MODE | MODE | REG +# -------+-------+-----------+-----------+-----------+----------- +# MOV8fd: 0 0 0 1 0 0 0 1 . 1 0 0 0 0 0 0 0 +# MOV8fd-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# MOV8fd-SAME: 0 0 0 1 0 0 0 1 . 1 0 0 0 0 0 0 0 +# MOV8fd-SAME: 0 0 0 1 1 0 0 0 . 1 1 1 1 1 1 1 1 +# --------------------------------------------------------------- +# MOV32fr-SAME: 0 0 1 0 0 0 1 1 . 1 0 0 0 0 0 0 0 +# MOV32fr-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# MOV32fr-SAME: 0 0 1 0 0 1 0 1 . 1 0 0 0 0 0 0 1 +# MOV32fr-SAME: 1 0 1 0 1 0 0 0 . 0 0 0 0 0 0 0 0 +# ---+-----------+---+-------+---+------------------------------- +# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT +# ---+-----------+---+-------+---+------------------------------- +name: MxMove_MR_ARII +body: | + bb.0: + MOV8fd 0, $a0, $d1, $bd0, implicit-def $ccr + MOV8fd -1, $a0, $d1, $bd0, implicit-def $ccr + MOV32fr 0, $a1, $d1, $d0, implicit-def $ccr + MOV32fr 0, $a2, $a2, $d1, implicit-def $ccr + +... +--- # ARID +# ---------------------------+-----------+-----------+----------- +# F E | D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# -------+-------+-----------+-----------+-----------+----------- +# | | DESTINATION | SOURCE +# 0 0 | SIZE | REG | MODE | MODE | REG +# -------+-------+-----------+-----------+-----------+----------- +# MOV8pd-SAME: 0 0 0 1 0 0 0 1 . 0 1 0 0 0 0 0 0 +# MOV8pd-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# MOV32pr-SAME: 0 0 1 0 0 0 1 1 . 0 1 0 0 0 0 0 0 +# MOV32pr-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# --------------------------------------------------------------- +# MOV32pr-SAME: 0 0 1 0 0 0 1 1 . 0 1 0 0 1 0 0 0 +# MOV32pr-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +name: MxMove_MR_ARID +body: | + bb.0: + MOV8pd 0, $a0, $bd0, implicit-def $ccr + MOV32pr -1, $a1, $d0, implicit-def $ccr + MOV32pr -1, $a1, $a0, implicit-def $ccr + +... +--- # ARI +# ---------------------------+-----------+-----------+----------- +# F E | D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# -------+-------+-----------+-----------+-----------+----------- +# | | DESTINATION | SOURCE +# 0 0 | SIZE | REG | MODE | MODE | REG +# -------+-------+-----------+-----------+-----------+----------- +# MOV8jd-SAME: 0 0 0 1 0 0 0 0 . 1 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# MOV32jr-SAME: 0 0 1 0 0 0 1 0 . 1 0 0 0 0 0 1 1 +# --------------------------------------------------------------- +# MOV32jr-SAME: 0 0 1 0 0 0 1 0 . 1 0 0 0 1 1 0 0 +name: MxMove_MR_ARI +body: | + bb.0: + MOV8jd $a0, $bd0, implicit-def $ccr + MOV32jr $a1, $d3, implicit-def $ccr + MOV32jr $a1, $a4, implicit-def $ccr + +... Index: llvm/test/CodeGen/M680x0/OBJ/Data/Classes/MxMove_RI.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Data/Classes/MxMove_RI.mir @@ -0,0 +1,31 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=MOV8di,MOV32ri + +#------------------------------------------------------------------------------ +# MxMove_RI is used for moving immediate to register +#------------------------------------------------------------------------------ + +# ---------------------------+-----------+-----------+----------- +# F E | D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# -------+-------+-----------+-----------+-----------+----------- +# | | DESTINATION | SOURCE +# 0 0 | SIZE | REG | MODE | MODE | REG +# -------+-------+-----------+-----------+-----------+----------- +# MOV8di: 0 0 0 1 0 0 0 0 . 0 0 1 1 1 1 0 0 +# MOV8di-SAME: 0 0 0 0 0 0 0 0 . 1 1 1 1 1 1 1 1 +# --------------------------------------------------------------- +# MOV32ri-SAME: 0 0 1 0 0 0 1 0 . 0 1 1 1 1 1 0 0 +# MOV32ri-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# MOV32ri-SAME: 0 0 0 0 0 0 0 0 . 0 0 1 0 1 0 1 0 +# --------------------------------------------------------------- +# MOV32ri-SAME: 0 0 1 0 0 0 1 0 . 0 1 1 1 1 1 0 0 +# MOV32ri-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# MOV32ri-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +name: MxMove_RI +body: | + bb.0: + $bd0 = MOV8di -1, implicit-def $ccr + $a1 = MOV32ri 42, implicit-def $ccr + $a1 = MOV32ri -1, implicit-def $ccr + Index: llvm/test/CodeGen/M680x0/OBJ/Data/Classes/MxMove_RM.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Data/Classes/MxMove_RM.mir @@ -0,0 +1,200 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=MOV8dk,MOV32rk,MOV8dq,MOV32rq,MOV8df,MOV32rf,\ +# RUN:MOV8dp,MOV32rp,MOV8dj,MOV32rj,MOV8do,MOV32ro,MOV8de,MOV32re,MOV8db,MOV32rb + +#------------------------------------------------------------------------------ +# MxMove_RM is used for moving data from memory to register +#------------------------------------------------------------------------------ + +--- # PCI +# ---------------------------+-----------+-----------+----------- +# F E | D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# -------+-------+-----------+-----------+-----------+----------- +# | | DESTINATION | SOURCE +# 0 0 | SIZE | REG | MODE | MODE | REG +# -------+-------+-----------+-----------+-----------+----------- +# MOV8dk: 0 0 0 1 0 0 0 0 . 0 0 1 1 1 0 1 1 +# MOV8dk-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# MOV8dk-SAME: 0 0 0 1 0 0 0 0 . 0 0 1 1 1 0 1 1 +# MOV8dk-SAME: 0 0 0 1 1 0 0 0 . 1 1 1 1 1 1 1 1 +# --------------------------------------------------------------- +# MOV32rk-SAME: 0 0 1 0 0 0 0 0 . 0 0 1 1 1 0 1 1 +# MOV32rk-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# MOV32rk-SAME: 0 0 1 0 0 0 1 0 . 0 0 1 1 1 0 1 1 +# MOV32rk-SAME: 1 0 1 0 1 0 0 0 . 0 0 0 0 0 0 0 0 +# ---+-----------+---+-------+---+------------------------------- +# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT +# ---+-----------+---+-------+---+------------------------------- +name: MxMove_RM_PCI +body: | + bb.0: + $bd0 = MOV8dk 0, $d1, implicit-def $ccr + $bd0 = MOV8dk -1, $d1, implicit-def $ccr + $d0 = MOV32rk 0, $d1, implicit-def $ccr + $d1 = MOV32rk 0, $a2, implicit-def $ccr + +... +--- # PCD +# ---------------------------+-----------+-----------+----------- +# F E | D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# -------+-------+-----------+-----------+-----------+----------- +# | | DESTINATION | SOURCE +# 0 0 | SIZE | REG | MODE | MODE | REG +# -------+-------+-----------+-----------+-----------+----------- +# MOV8dq-SAME: 0 0 0 1 0 0 0 0 . 0 0 1 1 1 0 1 0 +# MOV8dq-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# MOV32rq-SAME: 0 0 1 0 0 0 0 0 . 0 0 1 1 1 0 1 0 +# MOV32rq-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# --------------------------------------------------------------- +# MOV32rq-SAME: 0 0 1 0 0 0 0 0 . 0 1 1 1 1 0 1 0 +# MOV32rq-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +name: MxMove_RM_PCD +body: | + bb.0: + $bd0 = MOV8dq 0, implicit-def $ccr + $d0 = MOV32rq -1, implicit-def $ccr + $a0 = MOV32rq -1, implicit-def $ccr + +... +--- # ARII +# ---------------------------+-----------+-----------+----------- +# F E | D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# -------+-------+-----------+-----------+-----------+----------- +# | | DESTINATION | SOURCE +# 0 0 | SIZE | REG | MODE | MODE | REG +# -------+-------+-----------+-----------+-----------+----------- +# MOV8df: 0 0 0 1 0 0 0 0 . 0 0 1 1 0 0 0 0 +# MOV8df-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# MOV8df-SAME: 0 0 0 1 0 0 0 0 . 0 0 1 1 0 0 0 0 +# MOV8df-SAME: 0 0 0 1 1 0 0 0 . 1 1 1 1 1 1 1 1 +# --------------------------------------------------------------- +# MOV32rf-SAME: 0 0 1 0 0 0 0 0 . 0 0 1 1 0 0 0 1 +# MOV32rf-SAME: 0 0 0 1 1 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# MOV32rf-SAME: 0 0 1 0 0 0 1 0 . 0 0 1 1 0 0 1 0 +# MOV32rf-SAME: 1 0 1 0 1 0 0 0 . 0 0 0 0 0 0 0 0 +# ---+-----------+---+-------+---+------------------------------- +# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT +# ---+-----------+---+-------+---+------------------------------- +name: MxMove_RM_ARII +body: | + bb.0: + $bd0 = MOV8df 0, $a0, $d1, implicit-def $ccr + $bd0 = MOV8df -1, $a0, $d1, implicit-def $ccr + $d0 = MOV32rf 0, $a1, $d1, implicit-def $ccr + $d1 = MOV32rf 0, $a2, $a2, implicit-def $ccr + +... +--- # ARID +# ---------------------------+-----------+-----------+----------- +# F E | D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# -------+-------+-----------+-----------+-----------+----------- +# | | DESTINATION | SOURCE +# 0 0 | SIZE | REG | MODE | MODE | REG +# -------+-------+-----------+-----------+-----------+----------- +# MOV8dp-SAME: 0 0 0 1 0 0 0 0 . 0 0 1 0 1 0 0 0 +# MOV8dp-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# MOV32rp-SAME: 0 0 1 0 0 0 0 0 . 0 0 1 0 1 0 0 1 +# MOV32rp-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +# --------------------------------------------------------------- +# MOV32rp-SAME: 0 0 1 0 0 0 0 0 . 0 1 1 0 1 0 0 1 +# MOV32rp-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1 +name: MxMove_RM_ARID +body: | + bb.0: + $bd0 = MOV8dp 0, $a0, implicit-def $ccr + $d0 = MOV32rp -1, $a1, implicit-def $ccr + $a0 = MOV32rp -1, $a1, implicit-def $ccr + +... +--- # ARIPD +# ---------------------------+-----------+-----------+----------- +# F E | D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# -------+-------+-----------+-----------+-----------+----------- +# | | DESTINATION | SOURCE +# 0 0 | SIZE | REG | MODE | MODE | REG +# -------+-------+-----------+-----------+-----------+----------- +# MOV8de-SAME: 0 0 0 1 0 0 0 0 . 0 0 1 0 0 0 0 0 +# --------------------------------------------------------------- +# MOV32re-SAME: 0 0 1 0 0 1 1 0 . 0 0 1 0 0 0 0 1 +# --------------------------------------------------------------- +# MOV32re-SAME: 0 0 1 0 1 0 0 0 . 0 1 1 0 0 0 0 1 +name: MxMove_RM_ARIPD +body: | + bb.0: + $bd0 = MOV8de $a0, implicit-def $ccr + $d3 = MOV32re $a1, implicit-def $ccr + $a4 = MOV32re $a1, implicit-def $ccr + +... +--- # ARIPI +# ---------------------------+-----------+-----------+----------- +# F E | D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# -------+-------+-----------+-----------+-----------+----------- +# | | DESTINATION | SOURCE +# 0 0 | SIZE | REG | MODE | MODE | REG +# -------+-------+-----------+-----------+-----------+----------- +# MOV8do-SAME: 0 0 0 1 0 0 0 0 . 0 0 0 1 1 0 0 0 +# --------------------------------------------------------------- +# MOV32ro-SAME: 0 0 1 0 0 1 1 0 . 0 0 0 1 1 0 0 1 +# --------------------------------------------------------------- +# MOV32ro-SAME: 0 0 1 0 1 0 0 0 . 0 1 0 1 1 0 0 1 +name: MxMove_RM_ARIPI +body: | + bb.0: + $bd0 = MOV8do $a0, implicit-def $ccr + $d3 = MOV32ro $a1, implicit-def $ccr + $a4 = MOV32ro $a1, implicit-def $ccr + +... +--- # ARI +# ---------------------------+-----------+-----------+----------- +# F E | D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# -------+-------+-----------+-----------+-----------+----------- +# | | DESTINATION | SOURCE +# 0 0 | SIZE | REG | MODE | MODE | REG +# -------+-------+-----------+-----------+-----------+----------- +# MOV8dj-SAME: 0 0 0 1 0 0 0 0 . 0 0 0 1 0 0 0 0 +# --------------------------------------------------------------- +# MOV32rj-SAME: 0 0 1 0 0 1 1 0 . 0 0 0 1 0 0 0 1 +# --------------------------------------------------------------- +# MOV32rj-SAME: 0 0 1 0 1 0 0 0 . 0 1 0 1 0 0 0 1 +name: MxMove_RM_ARI +body: | + bb.0: + $bd0 = MOV8dj $a0, implicit-def $ccr + $d3 = MOV32rj $a1, implicit-def $ccr + $a4 = MOV32rj $a1, implicit-def $ccr + +... +--- # ABS +# ---------------------------+-----------+-----------+----------- +# F E | D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# -------+-------+-----------+-----------+-----------+----------- +# | | DESTINATION | SOURCE +# 0 0 | SIZE | REG | MODE | MODE | REG +# -------+-------+-----------+-----------+-----------+----------- +# MOV8db-SAME: 0 0 0 1 0 0 0 0 . 0 0 1 1 1 0 0 1 +# MOV8db-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# MOV32rb-SAME: 0 0 1 0 0 1 1 0 . 0 0 1 1 1 0 0 1 +# MOV32rb-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# MOV32rb-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# --------------------------------------------------------------- +# MOV32rb-SAME: 0 0 1 0 1 0 0 0 . 0 1 1 1 1 0 0 1 +# MOV32rb-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +# MOV32rb-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0 +name: MxMove_RM_ABS +body: | + bb.0: + $bd0 = MOV8db 0, implicit-def $ccr + $d3 = MOV32rb 0, implicit-def $ccr + $a4 = MOV32rb 0, implicit-def $ccr + +... Index: llvm/test/CodeGen/M680x0/OBJ/Data/Classes/MxMove_RR.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Data/Classes/MxMove_RR.mir @@ -0,0 +1,30 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=MOV8dd,MOV16ra,MOV32rr + +#------------------------------------------------------------------------------ +# MxMove_RR moves data from register to register +#------------------------------------------------------------------------------ + + +# ---------------------------+-----------+-----------+----------- +# F E | D C | B A 9 | 8 7 6 | 5 4 3 | 2 1 0 +# -------+-------+-----------+-----------+-----------+----------- +# | | DESTINATION | SOURCE +# 0 0 | SIZE | REG | MODE | MODE | REG +# -------+-------+-----------+-----------+-----------+----------- +# MOV8dd: 0 0 0 1 0 0 1 0 . 0 0 0 0 0 0 0 0 +# MOV16rr-SAME: 0 0 1 1 0 1 1 0 . 0 0 0 0 1 0 1 0 +# MOV16rr-SAME: 0 0 1 1 1 1 0 0 . 0 1 0 0 1 0 1 0 +# MOV32ra-SAME: 0 0 1 0 1 1 0 0 . 0 0 0 0 1 0 1 0 +# MOV32rr-SAME: 0 0 1 0 0 0 1 0 . 0 0 0 0 0 0 1 0 +# MOV32rr-SAME: 0 0 1 0 0 0 1 0 . 0 1 0 0 1 0 1 0 +name: MxMove_RR +body: | + bb.0: + $bd1 = MOV8dd $bd0, implicit-def $ccr + $wd3 = MOV16ra $wa2, implicit-def $ccr + $wa6 = MOV16ra $wa2, implicit-def $ccr + $wd1 = MOV16ra $wa2, implicit-def $ccr + $d1 = MOV32rr $d2, implicit-def $ccr + $a1 = MOV32rr $a2, implicit-def $ccr Index: llvm/test/CodeGen/M680x0/OBJ/README.md =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/README.md @@ -0,0 +1,14 @@ +# OBJECT CODE TESTS + +## Purpose +These test snippets are to test object code generation features, specifically +lowering of MxBean encoding, Relocations and specific commands encoding classes. + +### MxBean +TODO + +### Relocations +TODO + +### Encoding Classes +TODO Index: llvm/test/CodeGen/M680x0/OBJ/Relaxations/branch.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Relaxations/branch.mir @@ -0,0 +1,116 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj \ +# RUN: -code-model=small -relocation-model=pic -o - \ +# RUN: | extract-section .text -h \ +# RUN: | FileCheck %s -check-prefixes=x00 + +#------------------------------------------------------------------------------ +# Test branch relaxation. By default codegen choses smallest branch instruction, +# during object code generation it might get clear that offset does not fit and +# bigger instruction is required. +#------------------------------------------------------------------------------ + + +--- # TIGHT +# The offset for the small branch is from the PC value, which points to the +# next instruction, because there is no extension word here. +# 000 x00: 6078 +# 002 x00-SAME: 23f9 0000 0000 0000 0000 +# 00C x00-SAME: 23f9 0000 0000 0000 0000 +# 016 x00-SAME: 23f9 0000 0000 0000 0000 +# 020 x00-SAME: 23f9 0000 0000 0000 0000 +# 02A x00-SAME: 23f9 0000 0000 0000 0000 +# 034 x00-SAME: 23f9 0000 0000 0000 0000 +# 03E x00-SAME: 23f9 0000 0000 0000 0000 +# 048 x00-SAME: 23f9 0000 0000 0000 0000 +# 052 x00-SAME: 23f9 0000 0000 0000 0000 +# 05C x00-SAME: 23f9 0000 0000 0000 0000 +# 066 x00-SAME: 23f9 0000 0000 0000 0000 +# 070 x00-SAME: 23f9 0000 0000 0000 0000 +# 07A x00-SAME: d0bc 0000 0000 +# 080 x00-SAME: 4e75 +# 082 x00-SAME: 4e71 +name: TIGHT +body: | + bb.0: + successors: %bb.2 + + BRA8 %bb.2 + bb.1: + MOV32bb 0, 0, implicit-def $ccr + MOV32bb 0, 0, implicit-def $ccr + MOV32bb 0, 0, implicit-def $ccr + MOV32bb 0, 0, implicit-def $ccr + MOV32bb 0, 0, implicit-def $ccr + MOV32bb 0, 0, implicit-def $ccr + MOV32bb 0, 0, implicit-def $ccr + MOV32bb 0, 0, implicit-def $ccr + MOV32bb 0, 0, implicit-def $ccr + MOV32bb 0, 0, implicit-def $ccr + MOV32bb 0, 0, implicit-def $ccr + MOV32bb 0, 0, implicit-def $ccr + bb.2: + $d0 = ADD32ri $d0, 0, implicit-def $ccr + RET 0, $d0 + +... +--- # RELAXED +# 084 x00-SAME 6000 0084 +# 088 x00-SAME: 23f9 0000 0000 0000 0000 +# 092 x00-SAME: 23f9 0000 0000 0000 0000 +# 09C x00-SAME: 23f9 0000 0000 0000 0000 +# 0A6 x00-SAME: 23f9 0000 0000 0000 0000 +# 0B0 x00-SAME: 23f9 0000 0000 0000 0000 +# 0BA x00-SAME: 23f9 0000 0000 0000 0000 +# 0C4 x00-SAME: 23f9 0000 0000 0000 0000 +# 0CE x00-SAME: 23f9 0000 0000 0000 0000 +# 0D8 x00-SAME: 23f9 0000 0000 0000 0000 +# 0E2 x00-SAME: 23f9 0000 0000 0000 0000 +# 0EC x00-SAME: 23f9 0000 0000 0000 0000 +# 0F6 x00-SAME: 23f9 0000 0000 0000 0000 +# 100 x00-SAME: 23f9 0000 0000 0000 0000 +# 10A x00-SAME: d0bc 0000 0000 +# 110 x00-SAME: 4e75 +# 112 x00-SAME: 4e71 +name: RELAXED +body: | + bb.0: + successors: %bb.2 + + BRA8 %bb.2 + bb.1: + MOV32bb 0, 0, implicit-def $ccr + MOV32bb 0, 0, implicit-def $ccr + MOV32bb 0, 0, implicit-def $ccr + MOV32bb 0, 0, implicit-def $ccr + MOV32bb 0, 0, implicit-def $ccr + MOV32bb 0, 0, implicit-def $ccr + MOV32bb 0, 0, implicit-def $ccr + MOV32bb 0, 0, implicit-def $ccr + MOV32bb 0, 0, implicit-def $ccr + MOV32bb 0, 0, implicit-def $ccr + MOV32bb 0, 0, implicit-def $ccr + MOV32bb 0, 0, implicit-def $ccr + MOV32bb 0, 0, implicit-def $ccr + bb.2: + $d0 = ADD32ri $d0, 0, implicit-def $ccr + RET 0, $d0 + +... +--- # ZERO +# Because of the way M680x0 encodes branches it is not possible to encode 0 +# offset with the smallest insruction(0 in the offset field means exension word +# is used) thus we switch to the wider instruction. +# 114 x00-SAME: 6000 0002 +# 118 x00-SAME: d0bc 0000 0000 +# 11E x00-SAME: 4e75 +name: ZERO +body: | + bb.0: + successors: %bb.1 + + BRA8 %bb.1 + bb.1: + $d0 = ADD32ri $d0, 0, implicit-def $ccr + RET 0, $d0 + +... Index: llvm/test/CodeGen/M680x0/OBJ/Relocations/data-abs.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Relocations/data-abs.mir @@ -0,0 +1,26 @@ + +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj \ +# RUN: -code-model=small -relocation-model=pic -o - \ +# RUN: | llvm-readobj -relocations -elf-output-style=GNU - \ +# RUN: | FileCheck %s -check-prefixes=x00 + +#------------------------------------------------------------------------------ +# Test ABS relocation +#------------------------------------------------------------------------------ + +--- | + + @dst = external global i32 + + define void @DATA() { entry: ret void } + +... +--- # DATA +# Offset Info Type Sym. Value Sym S Addend +# x00: 00000002 {{[0-9a-f]+}} R_M680x0_32 {{[0-9]*}} dst + 0 +name: DATA +body: | + bb.0: + $d0 = MOV32rb @dst, implicit-def $ccr + +... Index: llvm/test/CodeGen/M680x0/OBJ/Relocations/data-gotoff.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Relocations/data-gotoff.mir @@ -0,0 +1,29 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj \ +# RUN: -code-model=small -relocation-model=pic -o - \ +# RUN: | llvm-readobj -relocations -elf-output-style=GNU - \ +# RUN: | FileCheck %s -check-prefixes=x00 + +#------------------------------------------------------------------------------ +# Test GOTOFF relocation +#------------------------------------------------------------------------------ + +--- | + + @dst = external global i32 + + define void @DATA() { entry: ret void } + +... +--- # DATA +# Offset Info Type Sym. Value Sym S Addend +# x00: 00000002 {{[0-9a-f]+}} R_M680x0_GOTPCREL16 {{[0-9]*}} _GLOBAL_OFFSET_TABLE_ + 0 +# x00: 00000007 {{[0-9a-f]+}} R_M680x0_GOTOFF8 {{[0-9]*}} dst + 0 +# x00: 0000000a {{[0-9a-f]+}} R_M680x0_GOTOFF16 {{[0-9]*}} dst + 0 +name: DATA +body: | + bb.0: + $a5 = LEA32q target-flags(M680x0-gotpcrel) &_GLOBAL_OFFSET_TABLE_ + $d0 = MOV32rf target-flags(M680x0-gotoff) @dst, $a5, $d0, implicit-def $ccr + $d0 = MOV32rp target-flags(M680x0-gotoff) @dst, $a5, implicit-def $ccr + +... Index: llvm/test/CodeGen/M680x0/OBJ/Relocations/data-gotpcrel.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Relocations/data-gotpcrel.mir @@ -0,0 +1,27 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj \ +# RUN: -code-model=small -relocation-model=pic -o - \ +# RUN: | llvm-readobj -relocations -elf-output-style=GNU - \ +# RUN: | FileCheck %s -check-prefixes=x00 + +#------------------------------------------------------------------------------ +# Test GOTPCREL relocation +#------------------------------------------------------------------------------ + +--- | + + @dst = external global i32 + + define void @DATA() { entry: ret void } + +... +--- # DATA +# Offset Info Type Sym. Value Sym S Addend +# x00: 00000003 {{[0-9]+}} R_M680x0_GOTPCREL8 {{[0-9]*}} dst + 1 +# x00: 00000006 {{[0-9]+}} R_M680x0_GOTPCREL16 {{[0-9]*}} dst + 0 +name: DATA +body: | + bb.0: + $a0 = MOV32rk target-flags(M680x0-gotpcrel) @dst, $d0, implicit-def $ccr + $a0 = MOV32rq target-flags(M680x0-gotpcrel) @dst, implicit-def $ccr + +... Index: llvm/test/CodeGen/M680x0/OBJ/Relocations/data-pc-rel.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Relocations/data-pc-rel.mir @@ -0,0 +1,30 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj \ +# RUN: -code-model=small -relocation-model=pic -o - \ +# RUN: | llvm-readobj -relocations -elf-output-style=GNU - \ +# RUN: | FileCheck %s -check-prefixes=x00 + +#------------------------------------------------------------------------------ +# Tests PC-Relative data relocations +#------------------------------------------------------------------------------ + +--- | + + @dst = external global i32 + + define void @DATA() { entry: ret void } + +... +--- # DATA +# Offset Info Type Sym. Value Sym S Addend +# x00: 00000003 {{[0-9]+}} R_M680x0_PC8 {{[0-9]*}} dst + 1 +# x00: 00000006 {{[0-9]+}} R_M680x0_PC16 {{[0-9]*}} dst + 0 +# No need for relocation here +# x00-NOT: 0000000a {{[0-9]+}} R_M680x0_PC16 0 +name: DATA +body: | + bb.0: + $a0 = MOV32rk @dst, $a0, implicit-def $ccr + $a0 = MOV32rq @dst, implicit-def $ccr + $a0 = MOV32rq 0, implicit-def $ccr + +... Index: llvm/test/CodeGen/M680x0/OBJ/Relocations/text-plt.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/Relocations/text-plt.mir @@ -0,0 +1,24 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj \ +# RUN: -code-model=small -relocation-model=pic -o - \ +# RUN: | llvm-readobj -relocations -elf-output-style=GNU - \ +# RUN: | FileCheck %s -check-prefixes=x00 + +#------------------------------------------------------------------------------ +# Test PLT relocation +#------------------------------------------------------------------------------ + +--- | + + declare void @TARGET() + define void @TEXT() { entry: ret void } + +... +--- # TEXT +# Offset Info Type Sym. Value Sym S Addend +# x00: 00000002 {{[0-9a-f]+}} R_M680x0_PLT16 {{[0-9]*}} TARGET + 0 +name: TEXT +body: | + bb.0: + CALLq target-flags(M680x0-plt) @TARGET + +... Index: llvm/test/CodeGen/M680x0/OBJ/ShiftRotate/Classes/MxSR_DD.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/ShiftRotate/Classes/MxSR_DD.mir @@ -0,0 +1,41 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=SHL8dd,SHL32dd,LSR8dd,LSR32dd,ASR8dd,ASR32dd,\ +# RUN:ROL8dd,ROL32dd,ROR8dd,ROR32dd + +#------------------------------------------------------------------------------ +# MxSR_DD encodes shift or rotate instructions; shift count is in register +#------------------------------------------------------------------------------ + +# ---------------+-----------+---+-------+---+-------+----------- +# F E D C | B A 9 | 8 | 7 6 | 5 | 4 3 | 2 1 0 +# ---------------+-----------+---+-------+---+-------+----------- +# 1 1 1 0 | Dx | D | SIZE | 1 | OP | Dy +# ---------------+-----------+---+-------+---+-------+----------- +# SHL8dd: 1 1 1 0 0 0 0 1 . 0 0 1 0 1 0 0 1 +# SHL32dd-SAME: 1 1 1 0 0 0 1 1 . 1 0 1 0 1 0 1 0 +# ---------------+-----------+---+-------+---+-------+----------- +# LSR8dd-SAME: 1 1 1 0 0 1 0 0 . 0 0 1 0 1 0 1 1 +# LSR32dd-SAME: 1 1 1 0 0 1 1 0 . 1 0 1 0 1 1 0 0 +# ---------------+-----------+---+-------+---+-------+----------- +# ASR8dd-SAME: 1 1 1 0 1 0 0 0 . 0 0 1 0 0 1 0 1 +# ASR32dd-SAME: 1 1 1 0 1 0 1 0 . 1 0 1 0 0 1 1 0 +# ---------------+-----------+---+-------+---+-------+----------- +# ROL8dd-SAME: 1 1 1 0 1 1 0 1 . 0 0 1 1 1 1 1 1 +# ROL32dd-SAME: 1 1 1 0 1 1 1 1 . 1 0 1 1 1 0 0 1 +# ---------------+-----------+---+-------+---+-------+----------- +# ROR8dd-SAME: 1 1 1 0 0 0 0 0 . 0 0 1 1 1 0 0 1 +# ROR32dd-SAME: 1 1 1 0 0 0 0 0 . 1 0 1 1 1 0 0 1 +name: MxSR_DD +body: | + bb.0: + $bd1 = SHL8dd $bd1, $bd0, implicit-def $ccr + $d2 = SHL32dd $d2, $d1, implicit-def $ccr + $bd3 = LSR8dd $bd3, $bd2, implicit-def $ccr + $d4 = LSR32dd $d4, $d3, implicit-def $ccr + $bd5 = ASR8dd $bd5, $bd4, implicit-def $ccr + $d6 = ASR32dd $d6, $d5, implicit-def $ccr + $bd7 = ROL8dd $bd7, $bd6, implicit-def $ccr + $d1 = ROL32dd $d1, $d7, implicit-def $ccr + $bd1 = ROR8dd $bd1, $bd0, implicit-def $ccr + $d1 = ROR32dd $d1, $d0, implicit-def $ccr Index: llvm/test/CodeGen/M680x0/OBJ/ShiftRotate/Classes/MxSR_DI.mir =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/OBJ/ShiftRotate/Classes/MxSR_DI.mir @@ -0,0 +1,56 @@ +# RUN: llc %s -mtriple=m680x0 -start-after=prologepilog -O0 -filetype=obj -o - \ +# RUN: | extract-section .text \ +# RUN: | FileCheck %s -check-prefixes=SHL8di,SHL32di,LSR8di,LSR32di,ASR8di,ASR32di,\ +# RUN:ROL8di,ROL32di,ROR8di,ROR32di + +#------------------------------------------------------------------------------ +# MxSR_DI encodes shift or rotate instructions; shift count is encoded into +# the instruction +#------------------------------------------------------------------------------ + +# ---------------+-----------+---+-------+---+-------+----------- +# F E D C | B A 9 | 8 | 7 6 | 5 | 4 3 | 2 1 0 +# ---------------+-----------+---+-------+---+-------+----------- +# 1 1 1 0 | Dx | D | SIZE | 0 | OP | Dy +# ---------------+-----------+---+-------+---+-------+----------- +# SHL8di: 1 1 1 0 0 0 1 1 . 0 0 0 0 1 0 0 1 +# SHL32di-SAME: 1 1 1 0 0 0 1 1 . 1 0 0 0 1 0 0 1 +# ---------------+-----------+---+-------+---+-------+----------- +# LSR8di-SAME: 1 1 1 0 0 0 1 0 . 0 0 0 0 1 0 0 1 +# LSR32di-SAME: 1 1 1 0 0 0 1 0 . 1 0 0 0 1 0 0 1 +# ---------------+-----------+---+-------+---+-------+----------- +# ASR8di-SAME: 1 1 1 0 0 0 1 0 . 0 0 0 0 0 0 0 1 +# ASR32di-SAME: 1 1 1 0 0 0 1 0 . 1 0 0 0 0 0 0 1 +# ---------------+-----------+---+-------+---+-------+----------- +# ROL8di-SAME: 1 1 1 0 0 0 1 1 . 0 0 0 1 1 0 0 1 +# ROL32di-SAME: 1 1 1 0 0 0 1 1 . 1 0 0 1 1 0 0 1 +# ---------------+-----------+---+-------+---+-------+----------- +# ROR8di-SAME: 1 1 1 0 0 0 1 0 . 0 0 0 1 1 0 0 1 +# ROR32di-SAME: 1 1 1 0 0 0 1 0 . 1 0 0 1 1 0 0 1 +# ROR32di-SAME: 1 1 1 0 0 1 0 0 . 1 0 0 1 1 0 0 1 +# ROR32di-SAME: 1 1 1 0 0 1 1 0 . 1 0 0 1 1 0 0 1 +# ROR32di-SAME: 1 1 1 0 1 0 0 0 . 1 0 0 1 1 0 0 1 +# ROR32di-SAME: 1 1 1 0 1 0 1 0 . 1 0 0 1 1 0 0 1 +# ROR32di-SAME: 1 1 1 0 1 1 0 0 . 1 0 0 1 1 0 0 1 +# ROR32di-SAME: 1 1 1 0 1 1 1 0 . 1 0 0 1 1 0 0 1 +# ROR32di-SAME: 1 1 1 0 0 0 0 0 . 1 0 0 1 1 0 0 1 +name: MxSR_DI +body: | + bb.0: + $bd1 = SHL8di $bd1, 1, implicit-def $ccr + $d1 = SHL32di $d1, 1, implicit-def $ccr + $bd1 = LSR8di $bd1, 1, implicit-def $ccr + $d1 = LSR32di $d1, 1, implicit-def $ccr + $bd1 = ASR8di $bd1, 1, implicit-def $ccr + $d1 = ASR32di $d1, 1, implicit-def $ccr + $bd1 = ROL8di $bd1, 1, implicit-def $ccr + $d1 = ROL32di $d1, 1, implicit-def $ccr + $bd1 = ROR8di $bd1, 1, implicit-def $ccr + $d1 = ROR32di $d1, 1, implicit-def $ccr + $d1 = ROR32di $d1, 2, implicit-def $ccr + $d1 = ROR32di $d1, 3, implicit-def $ccr + $d1 = ROR32di $d1, 4, implicit-def $ccr + $d1 = ROR32di $d1, 5, implicit-def $ccr + $d1 = ROR32di $d1, 6, implicit-def $ccr + $d1 = ROR32di $d1, 7, implicit-def $ccr + $d1 = ROR32di $d1, 8, implicit-def $ccr Index: llvm/test/CodeGen/M680x0/lit.local.cfg =================================================================== --- /dev/null +++ llvm/test/CodeGen/M680x0/lit.local.cfg @@ -0,0 +1,11 @@ +import os + +config.suffixes = ['.ll', '.mir', '.test', '.txt'] + +config.environment['PATH'] = os.pathsep.join( + [os.path.join(config.llvm_src_root, 'utils')] + + [config.environment.get('PATH')]) + +if not 'M680x0' in config.root.targets: + config.unsupported = True + Index: llvm/utils/benchmark/src/cycleclock.h =================================================================== --- llvm/utils/benchmark/src/cycleclock.h +++ llvm/utils/benchmark/src/cycleclock.h @@ -161,7 +161,7 @@ struct timeval tv; gettimeofday(&tv, nullptr); return static_cast(tv.tv_sec) * 1000000 + tv.tv_usec; -#elif defined(__mips__) +#elif defined(__mips__) || defined(__m68k__) // mips apparently only allows rdtsc for superusers, so we fall // back to gettimeofday. It's possible clock_gettime would be better. struct timeval tv; Index: llvm/utils/extract-section =================================================================== --- /dev/null +++ llvm/utils/extract-section @@ -0,0 +1,38 @@ +#!/bin/bash + +#------------------------------------------------------------------------------- +# Extract Section +# +# Read object file from stdin, extract named section and print its bit-pattern +#------------------------------------------------------------------------------- + +SECTION="\s$1"; shift; +BASE=${1:-'-b'}; + +DIR=/tmp/extract-section +TEMP=$DIR/$(uuidgen).o + +[ -d $DIR ] || mkdir $DIR + +cat > $TEMP + +if [[ $BASE == '-b' ]]; then +llvm-readobj -elf-output-style=GNU --sections $TEMP \ + | grep $SECTION \ + | awk '{print "dd if='$TEMP' bs=1 count=$[0x" $7 "] skip=$[0x" $6 "]"}' \ + | bash 2> /dev/null \ + | xxd -bits -groupsize 0 \ + | cut -d " " -f 2 \ + | tr -d "\n" \ + | fold -w8 | paste -sd'.' - \ + | fold -w1 | paste -sd' ' - +elif [[ $BASE == '-h' ]]; then +llvm-readobj -elf-output-style=GNU --sections $TEMP \ + | grep $SECTION \ + | awk '{print "dd if='$TEMP' bs=1 count=$[0x" $7 "] skip=$[0x" $6 "]"}' \ + | bash 2> /dev/null \ + | xxd -p \ + | fold -w4 | paste -sd' ' - +fi + +rm $TEMP