diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -805,10 +805,10 @@
   AsmOS << "bt";
   if (Action)
     AsmOS << Action;
-  AsmOS << SizeSuffix << " $2, ($1)\n\tsetc ${0:b}";
+  AsmOS << SizeSuffix << " $2, ($1)";
 
   // Build the constraints. FIXME: We should support immediates when possible.
-  std::string Constraints = "=r,r,r,~{cc},~{memory}";
+  std::string Constraints = "={@ccc},r,r,~{cc},~{memory}";
   std::string MachineClobbers = CGF.getTarget().getClobbers();
   if (!MachineClobbers.empty()) {
     Constraints += ',';
diff --git a/clang/test/CodeGen/bittest-intrin.c b/clang/test/CodeGen/bittest-intrin.c
--- a/clang/test/CodeGen/bittest-intrin.c
+++ b/clang/test/CodeGen/bittest-intrin.c
@@ -34,20 +34,20 @@
 #endif
 
 // X64-LABEL: define dso_local void @test32(i32* %base, i32 %idx)
-// X64: call i8 asm sideeffect "btl $2, ($1)\0A\09setc ${0:b}", "=r,r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}})
-// X64: call i8 asm sideeffect "btcl $2, ($1)\0A\09setc ${0:b}", "=r,r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}})
-// X64: call i8 asm sideeffect "btrl $2, ($1)\0A\09setc ${0:b}", "=r,r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}})
-// X64: call i8 asm sideeffect "btsl $2, ($1)\0A\09setc ${0:b}", "=r,r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}})
-// X64: call i8 asm sideeffect "lock btrl $2, ($1)\0A\09setc ${0:b}", "=r,r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}})
-// X64: call i8 asm sideeffect "lock btsl $2, ($1)\0A\09setc ${0:b}", "=r,r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}})
+// X64: call i8 asm sideeffect "btl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}})
+// X64: call i8 asm sideeffect "btcl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}})
+// X64: call i8 asm sideeffect "btrl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}})
+// X64: call i8 asm sideeffect "btsl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}})
+// X64: call i8 asm sideeffect "lock btrl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}})
+// X64: call i8 asm sideeffect "lock btsl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %{{.*}}, i32 {{.*}})
 
 // X64-LABEL: define dso_local void @test64(i64* %base, i64 %idx)
-// X64: call i8 asm sideeffect "btq $2, ($1)\0A\09setc ${0:b}", "=r,r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}})
-// X64: call i8 asm sideeffect "btcq $2, ($1)\0A\09setc ${0:b}", "=r,r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}})
-// X64: call i8 asm sideeffect "btrq $2, ($1)\0A\09setc ${0:b}", "=r,r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}})
-// X64: call i8 asm sideeffect "btsq $2, ($1)\0A\09setc ${0:b}", "=r,r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}})
-// X64: call i8 asm sideeffect "lock btrq $2, ($1)\0A\09setc ${0:b}", "=r,r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}})
-// X64: call i8 asm sideeffect "lock btsq $2, ($1)\0A\09setc ${0:b}", "=r,r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}})
+// X64: call i8 asm sideeffect "btq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}})
+// X64: call i8 asm sideeffect "btcq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}})
+// X64: call i8 asm sideeffect "btrq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}})
+// X64: call i8 asm sideeffect "btsq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}})
+// X64: call i8 asm sideeffect "lock btrq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}})
+// X64: call i8 asm sideeffect "lock btsq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %{{.*}}, i64 {{.*}})
 
 // ARM-LABEL: define dso_local {{.*}}void @test32(i32* %base, i32 %idx)
 // ARM: %[[IDXHI:[^ ]*]] = ashr i32 %{{.*}}, 3
diff --git a/llvm/test/CodeGen/X86/bittest-intrin.ll b/llvm/test/CodeGen/X86/bittest-intrin.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/X86/bittest-intrin.ll
@@ -0,0 +1,101 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-windows-msvc19.11.0 | FileCheck %s
+
+; This matches the code produced by clang/lib/CodeGen/bittest-intrin.c
+
+@sink = global i8 0, align 1
+
+define void @test32(i32* %base, i32 %idx) {
+; CHECK-LABEL: test32:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    btl %edx, (%rcx)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    setb {{.*}}(%rip)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    btcl %edx, (%rcx)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    setb {{.*}}(%rip)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    btrl %edx, (%rcx)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    setb {{.*}}(%rip)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    btsl %edx, (%rcx)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    setb {{.*}}(%rip)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    lock btrl %edx, (%rcx)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    setb {{.*}}(%rip)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    lock btsl %edx, (%rcx)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    setb {{.*}}(%rip)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    lock btsl %edx, (%rcx)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    setb {{.*}}(%rip)
+; CHECK-NEXT:    retq
+entry:
+  %0 = tail call i8 asm sideeffect "btl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %base, i32 %idx)
+  store volatile i8 %0, i8* @sink, align 1
+  %1 = tail call i8 asm sideeffect "btcl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %base, i32 %idx)
+  store volatile i8 %1, i8* @sink, align 1
+  %2 = tail call i8 asm sideeffect "btrl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %base, i32 %idx)
+  store volatile i8 %2, i8* @sink, align 1
+  %3 = tail call i8 asm sideeffect "btsl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %base, i32 %idx)
+  store volatile i8 %3, i8* @sink, align 1
+  %4 = tail call i8 asm sideeffect "lock btrl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %base, i32 %idx)
+  store volatile i8 %4, i8* @sink, align 1
+  %5 = tail call i8 asm sideeffect "lock btsl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %base, i32 %idx)
+  store volatile i8 %5, i8* @sink, align 1
+  %6 = tail call i8 asm sideeffect "lock btsl $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %base, i32 %idx)
+  store volatile i8 %6, i8* @sink, align 1
+  ret void
+}
+
+; Function Attrs: nounwind uwtable
+define void @test64(i64* %base, i64 %idx) {
+; CHECK-LABEL: test64:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    btq %rdx, (%rcx)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    setb {{.*}}(%rip)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    btcq %rdx, (%rcx)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    setb {{.*}}(%rip)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    btrq %rdx, (%rcx)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    setb {{.*}}(%rip)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    btsq %rdx, (%rcx)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    setb {{.*}}(%rip)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    lock btrq %rdx, (%rcx)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    setb {{.*}}(%rip)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    lock btsq %rdx, (%rcx)
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    setb {{.*}}(%rip)
+; CHECK-NEXT:    retq
+entry:
+  %0 = tail call i8 asm sideeffect "btq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %base, i64 %idx)
+  store volatile i8 %0, i8* @sink, align 1
+  %1 = tail call i8 asm sideeffect "btcq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %base, i64 %idx)
+  store volatile i8 %1, i8* @sink, align 1
+  %2 = tail call i8 asm sideeffect "btrq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %base, i64 %idx)
+  store volatile i8 %2, i8* @sink, align 1
+  %3 = tail call i8 asm sideeffect "btsq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %base, i64 %idx)
+  store volatile i8 %3, i8* @sink, align 1
+  %4 = tail call i8 asm sideeffect "lock btrq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %base, i64 %idx)
+  store volatile i8 %4, i8* @sink, align 1
+  %5 = tail call i8 asm sideeffect "lock btsq $2, ($1)", "={@ccc},r,r,~{cc},~{memory},~{dirflag},~{fpsr},~{flags}"(i64* %base, i64 %idx)
+  store volatile i8 %5, i8* @sink, align 1
+  ret void
+}