Index: llvm/lib/Target/ARM/ARMInstrMVE.td =================================================================== --- llvm/lib/Target/ARM/ARMInstrMVE.td +++ llvm/lib/Target/ARM/ARMInstrMVE.td @@ -450,7 +450,7 @@ : MVE_MI_with_pred { let Inst{31-20} = 0b111010100101; let Inst{8} = 0b1; - + let validForTailPredication=1; } class MVE_ScalarShiftSingleReg; } - let Predicates = [HasV8_1MMainline, HasMVEInt] in { + let Predicates = [HasV8_1MMainline, HasMVEInt], + D=MVEDomain, validForTailPredication=1 in { // System level VPR/P0 -> GPR let Uses = [VPR] in def VMRS_VPR : MovFromVFP<0b1100 /* vpr */, (outs GPR:$Rt), (ins), @@ -2845,12 +2846,19 @@ } } -let Predicates = [HasV8_1MMainline, HasMVEInt] in { +let Predicates = [HasV8_1MMainline, HasMVEInt], + D=MVEDomain, validForTailPredication=1 in { let Uses = [VPR] in { defm VSTR_VPR : vfp_vstrldr_sysreg<0b0,0b1100, "vpr">; } defm VSTR_P0 : vfp_vstrldr_sysreg<0b0,0b1101, "p0", (outs), (ins VCCR:$P0)>; + + let Defs = [VPR] in { + defm VLDR_VPR : vfp_vstrldr_sysreg<0b1,0b1100, "vpr">; + } + defm VLDR_P0 : vfp_vstrldr_sysreg<0b1,0b1101, "p0", + (outs VCCR:$P0), (ins)>; } let Uses = [FPSCR] in { @@ -2862,11 +2870,3 @@ defm VLDR_FPCXTS : vfp_vstrldr_sysreg<0b1,0b1111, "fpcxts">; } } - -let Predicates = [HasV8_1MMainline, HasMVEInt] in { - let Defs = [VPR] in { - defm VLDR_VPR : vfp_vstrldr_sysreg<0b1,0b1100, "vpr">; - } - defm VLDR_P0 : vfp_vstrldr_sysreg<0b1,0b1101, "p0", - (outs VCCR:$P0), (ins)>; -} Index: llvm/unittests/Target/ARM/MachineInstrTest.cpp =================================================================== --- llvm/unittests/Target/ARM/MachineInstrTest.cpp +++ llvm/unittests/Target/ARM/MachineInstrTest.cpp @@ -383,12 +383,20 @@ case MVE_ASRLi: case MVE_ASRLr: case MVE_LSRL: + case MVE_LSLLi: + case MVE_LSLLr: case MVE_SQRSHR: + case MVE_SQRSHRL: case MVE_SQSHL: + case MVE_SQSHLL: case MVE_SRSHR: + case MVE_SRSHRL: case MVE_UQRSHL: + case MVE_UQRSHLL: case MVE_UQSHL: + case MVE_UQSHLL: case MVE_URSHR: + case MVE_URSHRL: case MVE_VABDf16: case MVE_VABDf32: case MVE_VABDs16: @@ -972,6 +980,20 @@ case MVE_VSUBi16: case MVE_VSUBi32: case MVE_VSUBi8: + case VLDR_P0_off: + case VLDR_P0_post: + case VLDR_P0_pre: + case VLDR_VPR_off: + case VLDR_VPR_post: + case VLDR_VPR_pre: + case VSTR_P0_off: + case VSTR_P0_post: + case VSTR_P0_pre: + case VSTR_VPR_off: + case VSTR_VPR_post: + case VSTR_VPR_pre: + case VMRS_P0: + case VMRS_VPR: return true; } }; @@ -996,27 +1018,16 @@ ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()), std::string(TM->getTargetFeatureString()), *static_cast(TM.get()), false); - const ARMBaseInstrInfo *TII = ST.getInstrInfo(); - auto MII = TM->getMCInstrInfo(); + auto MII = TM->getMCInstrInfo(); for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) { - const MCInstrDesc &Desc = TII->get(i); - - for (auto &Op : Desc.operands()) { - // Only check instructions that access the MQPR regs. - if ((Op.OperandType & MCOI::OPERAND_REGISTER) == 0 || - (Op.RegClass != ARM::MQPRRegClassID && - Op.RegClass != ARM::QQPRRegClassID && - Op.RegClass != ARM::QQQQPRRegClassID)) - continue; - - uint64_t Flags = MII->get(i).TSFlags; - bool Valid = (Flags & ARMII::ValidForTailPredication) != 0; - ASSERT_EQ(IsValidTPOpcode(i), Valid) - << MII->getName(i) - << ": mismatched expectation for tail-predicated safety\n"; - break; - } + uint64_t Flags = MII->get(i).TSFlags; + if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE) + continue; + bool Valid = (Flags & ARMII::ValidForTailPredication) != 0; + ASSERT_EQ(IsValidTPOpcode(i), Valid) + << MII->getName(i) + << ": mismatched expectation for tail-predicated safety\n"; } }