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[AMDGPU] Enable scheduling around FP MODE-setting instructions
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Authored by foad on Thu, Sep 10, 3:42 AM.

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Summary

Pre-gfx10 all MODE-setting instructions were S_SETREG_B32 which is
marked as having unmodeled side effects, which makes the machine
scheduler treat it as a barrier. Now that we have proper implicit $mode
operands we can use a no-side-effects S_SETMODE_B32 pseudo instead for
setregs that only touch the FP MODE bits, to give the scheduler more
freedom.

Diff Detail

Event Timeline

foad created this revision.Thu, Sep 10, 3:42 AM
Herald added a project: Restricted Project. · View Herald TranscriptThu, Sep 10, 3:42 AM
foad requested review of this revision.Thu, Sep 10, 3:42 AM
arsenm added inline comments.Thu, Sep 10, 7:13 AM
llvm/lib/Target/AMDGPU/SOPInstructions.td
849

I don't like defining pseudos that look like real instruction names. I would prefer to call this something like

S_SETREG_B32_mode or something like that

foad updated this revision to Diff 291000.Thu, Sep 10, 9:31 AM

Rename the pseudo-instructions.

arsenm added inline comments.Fri, Sep 11, 1:46 PM
llvm/lib/Target/AMDGPU/SOPInstructions.td
866

I'm not sure this will be encoded correctly since it's repeating the same instruction definition and not adding the physical aliases. Can you add tests checking the encoding? I think this needs to use PseudoInstExpansion

foad added inline comments.Mon, Sep 14, 8:45 AM
llvm/lib/Target/AMDGPU/SOPInstructions.td
866

I'm not sure this will be encoded correctly since it's repeating the same instruction definition and not adding the physical aliases. Can you add tests checking the encoding? I think this needs to use PseudoInstExpansion

866

I'm not sure this will be encoded correctly since it's repeating the same instruction definition and not adding the physical aliases. Can you add tests checking the encoding?

You mean something like adding -show-mc-encoding to test/CodeGen/AMDGPU/llvm.amdgcn.s.setreg.ll ?

I think this needs to use PseudoInstExpansion

I'm not sure how to do that, because at the place where I want to define S_SETREG_IMM32_B32_mode, I don't know what real instruction it should expand to (S_SETREG_B32_gfx6_gfx7 vs S_SETREG_B32_vi vs S_SETREG_B32_gfx10). Is there an example I could follow?

arsenm added inline comments.Mon, Sep 14, 1:54 PM
llvm/lib/Target/AMDGPU/SOPInstructions.td
866

Yes.

Oh right, this mechanism doesn't have a way handle multiple alternative encodings. I thought this wasn't an issue for scalar instructions, which I thought had a stable encoding. You could hack around this in emitInstruction. I do think we need better infrastructure for dealing with this problem though.

foad updated this revision to Diff 291864.Tue, Sep 15, 4:20 AM

Add -show-mc-encoding.

foad added a comment.Tue, Sep 15, 4:21 AM

The encoding seems OK. I can pre-commit the -show-mc-encoding change to make that clearer if you want.

arsenm accepted this revision.Tue, Sep 15, 10:02 AM

LGTM, but it would be slightly nicer to factor the instruction definition into a class to avoid repeating the operand definition and asm string

This revision is now accepted and ready to land.Tue, Sep 15, 10:02 AM
foad updated this revision to Diff 292222.Wed, Sep 16, 7:54 AM

Factor instruction definitions into a class.

arsenm accepted this revision.Wed, Sep 16, 8:01 AM
This revision was landed with ongoing or failed builds.Wed, Sep 16, 8:11 AM
This revision was automatically updated to reflect the committed changes.