Wordsmith RegionBranchOpInterface verification errors

[silvas]

Summary

I was having a lot of trouble parsing the messages. In particular, the
messages like:

<stdin>:3:8: error: 'scf.if' op  along control flow edge from Region #0 to scf.if source #1 type '!npcomprt.tensor' should match input #1 type 'tensor<?xindex>'

In particular, one thing that kept catching me was parsing the "to scf.if
source #1 type" as one thing, but really it is
"to parent results: source type #1".

[jurahul]

Looks ok. In general if there is a control flow edge from parent->region, the values flowing along may not necessarily be the parent operands, and if there is control flow edge from a region->parent, the values flowing may not necessarily flow into parent results. But the current RegionBranchOpInterface is designed to model this, so this looks ok.

mlir/lib/Interfaces/ControlFlowInterfaces.cpp

for (RegionSuccessor &succ : successors) {
     if (!succ.isParent())
       succRegionNo = succ.getSuccessor()->getRegionNumber();
 
     auto printEdgeName = [&](InFlightDiagnostic &diag) -> InFlightDiagnostic & {
       diag << "from ";
       if (sourceNo)
         diag << "Region #" << sourceNo.getValue();
       else
-        diag << op->getName();
+        diag << "parent operands";
 
       diag << " to ";
       if (succRegionNo)
         diag << "Region #" << succRegionNo.getValue();
       else
-        diag << op->getName();
+        diag << "parent results";
       return diag;
     };
 
     TypeRange sourceTypes = getInputsTypesForRegion(succRegionNo);
     TypeRange succInputsTypes = succ.getSuccessorInputs().getTypes();
     if (sourceTypes.size() != succInputsTypes.size()) {
       InFlightDiagnostic diag = op->emitOpError(" region control flow edge ");
-      return printEdgeName(diag)
-             << " has " << sourceTypes.size()
-             << " source operands, but target successor needs "
+      return printEdgeName(diag) << ": source has " << sourceTypes.size()
+                                 << " operands, but target successor needs "
                                  << succInputsTypes.size();
     }
 
     for (auto typesIdx :
          llvm::enumerate(llvm::zip(sourceTypes, succInputsTypes))) {
       Type sourceType = std::get<0>(typesIdx.value());
       Type inputType = std::get<1>(typesIdx.value());
       if (sourceType != inputType) {
         InFlightDiagnostic diag = op->emitOpError(" along control flow edge ");
         return printEdgeName(diag)
-               << " source #" << typesIdx.index() << " type " << sourceType
-               << " should match input #" << typesIdx.index() << " type "
+               << ": source type #" << typesIdx.index() << " " << sourceType
+               << " should match input type #" << typesIdx.index() << " "
                << inputType;
       }
     }
   }
   return success();
 }
 
 /// Verify that types match along control flow edges described the given op.

mlir/test/Dialect/SCF/invalid.mlir

func @reduceReturn_not_inside_reduce(%arg0 : f32) {
   }): () -> ()
   return
 }
 
 // -----
 
 func @std_if_incorrect_yield(%arg0: i1, %arg1: f32)
 {
-  // expected-error@+1 {{region control flow edge from Region #0 to scf.if has 1 source operands, but target successor needs 2}}
+  // expected-error@+1 {{region control flow edge from Region #0 to parent results: source has 1 operands, but target successor needs 2}}
   %x, %y = scf.if %arg0 -> (f32, f32) {
     %0 = addf %arg1, %arg1 : f32
     scf.yield %0 : f32
   } else {
     %0 = subf %arg1, %arg1 : f32
     scf.yield %0, %0 : f32, f32
   }
   return
func @std_for_operands_mismatch_3(%arg0 : index, %arg1 : index, %arg2 : index) {
   return
 }
 
 // -----
 
 func @std_for_operands_mismatch_4(%arg0 : index, %arg1 : index, %arg2 : index) {
   %s0 = constant 0.0 : f32
   %t0 = constant 1.0 : f32
-  // expected-error @+1 {{along control flow edge from Region #0 to Region #0 source #1 type 'i32' should match input #1 type 'f32'}}
+  // expected-error @+1 {{along control flow edge from Region #0 to Region #0: source type #1 'i32' should match input type #1 'f32'}}
   %result1:2 = scf.for %i0 = %arg0 to %arg1 step %arg2
                     iter_args(%si = %s0, %ti = %t0) -> (f32, f32) {
     %sn = addf %si, %si : f32
     %ic = constant 1 : i32
     scf.yield %sn, %ic : f32, i32
   }
   return
 }