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Differential D87161

[DemandedBits][BDCE] Add support for min/max intrinsics
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Authored by nikic on Sep 4 2020, 1:45 PM.

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Reviewers
lebedev.ri
spatel
hfinkel
Commits
rGa5168bdb4a25: [DemandedBits][BDCE] Add support for min/max intrinsics
Summary

Add DemandedBits / BDCE support for min/max intrinsics: If the low bits are not demanded in the result, they also aren't demanded in the operands.

We'll want the same in InstCombineSimplifyDemanded, but we need KnownBits support to land first, so that's waiting on D87034.

Diff Detail

Event Timeline

nikic created this revision.Sep 4 2020, 1:45 PM
Herald added a project: Restricted Project. · View Herald TranscriptSep 4 2020, 1:45 PM
Herald added subscribers: llvm-commits, hiraditya. · View Herald Transcript
nikic requested review of this revision.Sep 4 2020, 1:45 PM
Harbormaster completed remote builds in B70690: Diff 290022.Sep 4 2020, 2:24 PM
spatel accepted this revision.Sep 10 2020, 9:03 AM

LGTM

llvm/lib/Analysis/DemandedBits.cpp
181–183

Nit: this is where LLVM formatting rules break down. I couldn't tell that we were in a switch-within-an-if-within-a-swich from that single brace/indent. At the least, I'd add braces on the 'if'.

This revision is now accepted and ready to land.Sep 10 2020, 9:03 AM
Closed by commit rGa5168bdb4a25: [DemandedBits][BDCE] Add support for min/max intrinsics (authored by nikic). · Explain WhySep 10 2020, 1:14 PM
This revision was automatically updated to reflect the committed changes.
nikic added a commit: rGa5168bdb4a25: [DemandedBits][BDCE] Add support for min/max intrinsics.
nikic marked an inline comment as done.Sep 10 2020, 1:14 PM
nikic added inline comments.
llvm/lib/Analysis/DemandedBits.cpp
181–183

Agreed. I've added braces for the if in a separate commit: https://github.com/llvm/llvm-project/commit/99e78cb7185db1a15afd33020a1e026dc7ac5e1b

Revision Contents

PathSize
llvm/
lib/
Analysis/
8 lines
test/
Transforms/
BDCE/
16 lines

Diff 291071

llvm/lib/Analysis/DemandedBits.cpp

Show First 20 Lines • Show All 164 Lines • ▼ Show 20 Lines if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(UserI)) {
if (OperandNo == 0) if (OperandNo == 0)
AB = AOut.lshr(ShiftAmt); AB = AOut.lshr(ShiftAmt);
else if (OperandNo == 1) else if (OperandNo == 1)
AB = AOut.shl(BitWidth - ShiftAmt); AB = AOut.shl(BitWidth - ShiftAmt);
} }
break; break;
} }
case Intrinsic::umax:
case Intrinsic::umin:
case Intrinsic::smax:
case Intrinsic::smin:
// If low bits of result are not demanded, they are also not demanded
// for the min/max operands.
AB = APInt::getBitsSetFrom(BitWidth, AOut.countTrailingZeros());
break;
} }
} }
break; break;
spatelUnsubmitted
Not Done
ReplyInline Actions

Nit: this is where LLVM formatting rules break down. I couldn't tell that we were in a switch-within-an-if-within-a-swich from that single brace/indent. At the least, I'd add braces on the 'if'.

spatel: Nit: this is where LLVM formatting rules break down. I couldn't tell that we were in a switch…
nikicAuthorUnsubmitted
Done
ReplyInline Actions

Agreed. I've added braces for the if in a separate commit: https://github.com/llvm/llvm-project/commit/99e78cb7185db1a15afd33020a1e026dc7ac5e1b

nikic: Agreed. I've added braces for the if in a separate commit: https://github.com/llvm/llvm…
case Instruction::Add: case Instruction::Add:
if (AOut.isMask()) { if (AOut.isMask()) {
AB = AOut; AB = AOut;
} else { } else {
ComputeKnownBits(BitWidth, UserI->getOperand(0), UserI->getOperand(1)); ComputeKnownBits(BitWidth, UserI->getOperand(0), UserI->getOperand(1));
AB = determineLiveOperandBitsAdd(OperandNo, AOut, Known, Known2); AB = determineLiveOperandBitsAdd(OperandNo, AOut, Known, Known2);
} }
break; break;
▲ Show 20 Lines • Show All 401 Lines • Show Last 20 Lines

llvm/test/Transforms/BDCE/intrinsics.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -bdce < %s | FileCheck %s ; RUN: opt -S -bdce < %s | FileCheck %s
declare i8 @llvm.umax.i8(i8, i8) declare i8 @llvm.umax.i8(i8, i8)
declare i8 @llvm.umin.i8(i8, i8) declare i8 @llvm.umin.i8(i8, i8)
declare i8 @llvm.smax.i8(i8, i8) declare i8 @llvm.smax.i8(i8, i8)
declare i8 @llvm.smin.i8(i8, i8) declare i8 @llvm.smin.i8(i8, i8)
define i8 @umax(i8 %x, i8 %y, i1 %a, i1 %b) { define i8 @umax(i8 %x, i8 %y, i1 %a, i1 %b) {
; CHECK-LABEL: @umax( ; CHECK-LABEL: @umax(
; CHECK-NEXT: [[A2:%.*]] = zext i1 [[A:%.*]] to i8 ; CHECK-NEXT: [[A2:%.*]] = zext i1 false to i8
; CHECK-NEXT: [[B2:%.*]] = zext i1 [[B:%.*]] to i8 ; CHECK-NEXT: [[B2:%.*]] = zext i1 false to i8
; CHECK-NEXT: [[X2:%.*]] = or i8 [[X:%.*]], [[A2]] ; CHECK-NEXT: [[X2:%.*]] = or i8 [[X:%.*]], [[A2]]
; CHECK-NEXT: [[Y2:%.*]] = or i8 [[Y:%.*]], [[B2]] ; CHECK-NEXT: [[Y2:%.*]] = or i8 [[Y:%.*]], [[B2]]
; CHECK-NEXT: [[M:%.*]] = call i8 @llvm.umax.i8(i8 [[X2]], i8 [[Y2]]) ; CHECK-NEXT: [[M:%.*]] = call i8 @llvm.umax.i8(i8 [[X2]], i8 [[Y2]])
; CHECK-NEXT: [[R:%.*]] = lshr i8 [[M]], 1 ; CHECK-NEXT: [[R:%.*]] = lshr i8 [[M]], 1
; CHECK-NEXT: ret i8 [[R]] ; CHECK-NEXT: ret i8 [[R]]
; ;
%a2 = zext i1 %a to i8 %a2 = zext i1 %a to i8
%b2 = zext i1 %b to i8 %b2 = zext i1 %b to i8
%x2 = or i8 %x, %a2 %x2 = or i8 %x, %a2
%y2 = or i8 %y, %b2 %y2 = or i8 %y, %b2
%m = call i8 @llvm.umax.i8(i8 %x2, i8 %y2) %m = call i8 @llvm.umax.i8(i8 %x2, i8 %y2)
%r = lshr i8 %m, 1 %r = lshr i8 %m, 1
ret i8 %r ret i8 %r
} }
define i8 @umin(i8 %x, i8 %y, i1 %a, i1 %b) { define i8 @umin(i8 %x, i8 %y, i1 %a, i1 %b) {
; CHECK-LABEL: @umin( ; CHECK-LABEL: @umin(
; CHECK-NEXT: [[A2:%.*]] = zext i1 [[A:%.*]] to i8 ; CHECK-NEXT: [[A2:%.*]] = zext i1 false to i8
; CHECK-NEXT: [[B2:%.*]] = zext i1 [[B:%.*]] to i8 ; CHECK-NEXT: [[B2:%.*]] = zext i1 false to i8
; CHECK-NEXT: [[X2:%.*]] = or i8 [[X:%.*]], [[A2]] ; CHECK-NEXT: [[X2:%.*]] = or i8 [[X:%.*]], [[A2]]
; CHECK-NEXT: [[Y2:%.*]] = or i8 [[Y:%.*]], [[B2]] ; CHECK-NEXT: [[Y2:%.*]] = or i8 [[Y:%.*]], [[B2]]
; CHECK-NEXT: [[M:%.*]] = call i8 @llvm.umin.i8(i8 [[X2]], i8 [[Y2]]) ; CHECK-NEXT: [[M:%.*]] = call i8 @llvm.umin.i8(i8 [[X2]], i8 [[Y2]])
; CHECK-NEXT: [[R:%.*]] = lshr i8 [[M]], 1 ; CHECK-NEXT: [[R:%.*]] = lshr i8 [[M]], 1
; CHECK-NEXT: ret i8 [[R]] ; CHECK-NEXT: ret i8 [[R]]
; ;
%a2 = zext i1 %a to i8 %a2 = zext i1 %a to i8
%b2 = zext i1 %b to i8 %b2 = zext i1 %b to i8
%x2 = or i8 %x, %a2 %x2 = or i8 %x, %a2
%y2 = or i8 %y, %b2 %y2 = or i8 %y, %b2
%m = call i8 @llvm.umin.i8(i8 %x2, i8 %y2) %m = call i8 @llvm.umin.i8(i8 %x2, i8 %y2)
%r = lshr i8 %m, 1 %r = lshr i8 %m, 1
ret i8 %r ret i8 %r
} }
define i8 @smax(i8 %x, i8 %y, i1 %a, i1 %b) { define i8 @smax(i8 %x, i8 %y, i1 %a, i1 %b) {
; CHECK-LABEL: @smax( ; CHECK-LABEL: @smax(
; CHECK-NEXT: [[A2:%.*]] = zext i1 [[A:%.*]] to i8 ; CHECK-NEXT: [[A2:%.*]] = zext i1 false to i8
; CHECK-NEXT: [[B2:%.*]] = zext i1 [[B:%.*]] to i8 ; CHECK-NEXT: [[B2:%.*]] = zext i1 false to i8
; CHECK-NEXT: [[X2:%.*]] = or i8 [[X:%.*]], [[A2]] ; CHECK-NEXT: [[X2:%.*]] = or i8 [[X:%.*]], [[A2]]
; CHECK-NEXT: [[Y2:%.*]] = or i8 [[Y:%.*]], [[B2]] ; CHECK-NEXT: [[Y2:%.*]] = or i8 [[Y:%.*]], [[B2]]
; CHECK-NEXT: [[M:%.*]] = call i8 @llvm.smax.i8(i8 [[X2]], i8 [[Y2]]) ; CHECK-NEXT: [[M:%.*]] = call i8 @llvm.smax.i8(i8 [[X2]], i8 [[Y2]])
; CHECK-NEXT: [[R:%.*]] = lshr i8 [[M]], 1 ; CHECK-NEXT: [[R:%.*]] = lshr i8 [[M]], 1
; CHECK-NEXT: ret i8 [[R]] ; CHECK-NEXT: ret i8 [[R]]
; ;
%a2 = zext i1 %a to i8 %a2 = zext i1 %a to i8
%b2 = zext i1 %b to i8 %b2 = zext i1 %b to i8
%x2 = or i8 %x, %a2 %x2 = or i8 %x, %a2
%y2 = or i8 %y, %b2 %y2 = or i8 %y, %b2
%m = call i8 @llvm.smax.i8(i8 %x2, i8 %y2) %m = call i8 @llvm.smax.i8(i8 %x2, i8 %y2)
%r = lshr i8 %m, 1 %r = lshr i8 %m, 1
ret i8 %r ret i8 %r
} }
define i8 @smin(i8 %x, i8 %y, i1 %a, i1 %b) { define i8 @smin(i8 %x, i8 %y, i1 %a, i1 %b) {
; CHECK-LABEL: @smin( ; CHECK-LABEL: @smin(
; CHECK-NEXT: [[A2:%.*]] = zext i1 [[A:%.*]] to i8 ; CHECK-NEXT: [[A2:%.*]] = zext i1 false to i8
; CHECK-NEXT: [[B2:%.*]] = zext i1 [[B:%.*]] to i8 ; CHECK-NEXT: [[B2:%.*]] = zext i1 false to i8
; CHECK-NEXT: [[X2:%.*]] = or i8 [[X:%.*]], [[A2]] ; CHECK-NEXT: [[X2:%.*]] = or i8 [[X:%.*]], [[A2]]
; CHECK-NEXT: [[Y2:%.*]] = or i8 [[Y:%.*]], [[B2]] ; CHECK-NEXT: [[Y2:%.*]] = or i8 [[Y:%.*]], [[B2]]
; CHECK-NEXT: [[M:%.*]] = call i8 @llvm.smin.i8(i8 [[X2]], i8 [[Y2]]) ; CHECK-NEXT: [[M:%.*]] = call i8 @llvm.smin.i8(i8 [[X2]], i8 [[Y2]])
; CHECK-NEXT: [[R:%.*]] = lshr i8 [[M]], 1 ; CHECK-NEXT: [[R:%.*]] = lshr i8 [[M]], 1
; CHECK-NEXT: ret i8 [[R]] ; CHECK-NEXT: ret i8 [[R]]
; ;
%a2 = zext i1 %a to i8 %a2 = zext i1 %a to i8
%b2 = zext i1 %b to i8 %b2 = zext i1 %b to i8
%x2 = or i8 %x, %a2 %x2 = or i8 %x, %a2
%y2 = or i8 %y, %b2 %y2 = or i8 %y, %b2
%m = call i8 @llvm.smin.i8(i8 %x2, i8 %y2) %m = call i8 @llvm.smin.i8(i8 %x2, i8 %y2)
%r = lshr i8 %m, 1 %r = lshr i8 %m, 1
ret i8 %r ret i8 %r
} }