[X86] Support -march=sapphirerapids

[FreddyYe]

Summary

Support -march=sapphirerapids for x86.
Compare with Icelake Server, it includes 14 more new features. They are
amxtile, amxint8, amxbf16, avx512bf16, avx512vp2intersect, cldemote,
enqcmd, movdir64b, movdiri, ptwrite, serialize, shstk, tsxldtrk, waitpkg.

[craig.topper]

LGTM

clang/lib/Basic/Targets/X86.cpp

void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
   case CK_SkylakeClient:
   case CK_SkylakeServer:
   case CK_Cascadelake:
   case CK_Cooperlake:
   case CK_Cannonlake:
   case CK_IcelakeClient:
   case CK_IcelakeServer:
   case CK_Tigerlake:
+  case CK_SapphireRapids:
     // FIXME: Historically, we defined this legacy name, it would be nice to
     // remove it at some point. We've never exposed fine-grained names for
     // recent primary x86 CPUs, and we should keep it that way.
     defineCPUMacros(Builder, "corei7");
     break;
   case CK_KNL:
     defineCPUMacros(Builder, "knl");
     break;
switch (CPU) {
     case CK_Broadwell:
     case CK_SkylakeClient:
     case CK_SkylakeServer:
     case CK_Cascadelake:
     case CK_Nehalem:
     case CK_Cooperlake:
     case CK_Cannonlake:
     case CK_Tigerlake:
+    case CK_SapphireRapids:
     case CK_IcelakeClient:
     case CK_IcelakeServer:
     case CK_KNL:
     case CK_KNM:
     // K7
     case CK_Athlon:
     case CK_AthlonXP:
     // K8

clang/test/CodeGen/attr-target-mv.c

 // RUN: %clang_cc1 -triple x86_64-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=LINUX
 // RUN: %clang_cc1 -triple x86_64-windows-pc -emit-llvm %s -o - | FileCheck %s --check-prefix=WINDOWS
 
 int __attribute__((target("sse4.2"))) foo(void) { return 0; }
 int __attribute__((target("arch=sandybridge"))) foo(void);
 int __attribute__((target("arch=ivybridge"))) foo(void) {return 1;}
 int __attribute__((target("arch=goldmont"))) foo(void) {return 3;}
 int __attribute__((target("arch=goldmont-plus"))) foo(void) {return 4;}
 int __attribute__((target("arch=tremont"))) foo(void) {return 5;}
 int __attribute__((target("arch=icelake-client"))) foo(void) {return 6;}
 int __attribute__((target("arch=icelake-server"))) foo(void) {return 7;}
 int __attribute__((target("arch=cooperlake"))) foo(void) {return 8;}
 int __attribute__((target("arch=tigerlake"))) foo(void) {return 9;}
+int __attribute__((target("arch=sapphirerapids"))) foo(void) {return 10;}
 int __attribute__((target("default"))) foo(void) { return 2; }
 
 int bar() {
   return foo();
 }
 
 inline int __attribute__((target("sse4.2"))) foo_inline(void) { return 0; }
 inline int __attribute__((target("arch=sandybridge"))) foo_inline(void);

 // LINUX: define i32 @foo.arch_icelake-client()
 // LINUX: ret i32 6
 // LINUX: define i32 @foo.arch_icelake-server()
 // LINUX: ret i32 7
 // LINUX: define i32 @foo.arch_cooperlake()
 // LINUX: ret i32 8
 // LINUX: define i32 @foo.arch_tigerlake()
 // LINUX: ret i32 9
+// LINUX: define i32 @foo.arch_sapphirerapids()
+// LINUX: ret i32 10
 // LINUX: define i32 @foo()
 // LINUX: ret i32 2
 // LINUX: define i32 @bar()
 // LINUX: call i32 @foo.ifunc()
 
 // WINDOWS: define dso_local i32 @foo.sse4.2()
 // WINDOWS: ret i32 0
 // WINDOWS: define dso_local i32 @foo.arch_ivybridge()

clang/test/CodeGen/target-builtin-noerror.c

void verifycpustrings() {
   (void)__builtin_cpu_is("nehalem");
   (void)__builtin_cpu_is("sandybridge");
   (void)__builtin_cpu_is("shanghai");
   (void)__builtin_cpu_is("silvermont");
   (void)__builtin_cpu_is("skylake");
   (void)__builtin_cpu_is("skylake-avx512");
   (void)__builtin_cpu_is("slm");
   (void)__builtin_cpu_is("tigerlake");
+  (void)__builtin_cpu_is("sapphirerapids");
   (void)__builtin_cpu_is("tremont");
   (void)__builtin_cpu_is("westmere");
   (void)__builtin_cpu_is("znver1");
   (void)__builtin_cpu_is("znver2");
 }

clang/test/Driver/x86-march.c

 // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=goldmont-plus 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=goldmont-plus
 // goldmont-plus: "-target-cpu" "goldmont-plus"
 //
 // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=tremont 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=tremont
 // tremont: "-target-cpu" "tremont"
 //
+// RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=sapphirerapids 2>&1 \
+// RUN:   | FileCheck %s -check-prefix=sapphirerapids
+// sapphirerapids: "-target-cpu" "sapphirerapids"
+//
 // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=k8 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=k8
 // k8: "-target-cpu" "k8"
 //
 // RUN: %clang -target x86_64-unknown-unknown -c -### %s -march=opteron 2>&1 \
 // RUN:   | FileCheck %s -check-prefix=opteron
 // opteron: "-target-cpu" "opteron"
 //

clang/test/Misc/target-invalid-cpu-note.c

 // RUN: not %clang_cc1 -triple i386--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix X86
 // X86: error: unknown target CPU 'not-a-cpu'
 // X86: note: valid target CPU values are: i386, i486, winchip-c6, winchip2, c3,
 // X86-SAME: i586, pentium, pentium-mmx, pentiumpro, i686, pentium2, pentium3,
 // X86-SAME: pentium3m, pentium-m, c3-2, yonah, pentium4, pentium4m, prescott,
 // X86-SAME: nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont,
 // X86-SAME: nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge,
 // X86-SAME: core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512,
-// X86-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, icelake-server, tigerlake, knl, knm, lakemont, k6, k6-2, k6-3,
+// X86-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, icelake-server, tigerlake, sapphirerapids, knl, knm, lakemont, k6, k6-2, k6-3,
 // X86-SAME: athlon, athlon-tbird, athlon-xp, athlon-mp, athlon-4, k8, athlon64,
 // X86-SAME: athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10,
 // X86-SAME: barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2,
 // X86-SAME: x86-64, geode
 
 // RUN: not %clang_cc1 -triple x86_64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix X86_64
 // X86_64: error: unknown target CPU 'not-a-cpu'
 // X86_64: note: valid target CPU values are: nocona, core2, penryn, bonnell,
 // X86_64-SAME: atom, silvermont, slm, goldmont, goldmont-plus, tremont, nehalem, corei7, westmere,
 // X86_64-SAME: sandybridge, corei7-avx, ivybridge, core-avx-i, haswell,
 // X86_64-SAME: core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cooperlake, cannonlake,
-// X86_64-SAME: icelake-client, icelake-server, tigerlake, knl, knm, k8, athlon64, athlon-fx, opteron, k8-sse3,
+// X86_64-SAME: icelake-client, icelake-server, tigerlake, sapphirerapids, knl, knm, k8, athlon64, athlon-fx, opteron, k8-sse3,
 // X86_64-SAME: athlon64-sse3, opteron-sse3, amdfam10, barcelona, btver1,
 // X86_64-SAME: btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, x86-64
 
 // RUN: not %clang_cc1 -triple i386--- -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE_X86
 // TUNE_X86: error: unknown target CPU 'not-a-cpu'
 // TUNE_X86: note: valid target CPU values are: i386, i486, winchip-c6, winchip2, c3,
 // TUNE_X86-SAME: i586, pentium, pentium-mmx, pentiumpro, i686, pentium2, pentium3,
 // TUNE_X86-SAME: pentium3m, pentium-m, c3-2, yonah, pentium4, pentium4m, prescott,
 // TUNE_X86-SAME: nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont,
 // TUNE_X86-SAME: nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge,
 // TUNE_X86-SAME: core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512,
-// TUNE_X86-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, icelake-server, tigerlake, knl, knm, lakemont, k6, k6-2, k6-3,
+// TUNE_X86-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, icelake-server, tigerlake, sapphirerapids, knl, knm, lakemont, k6, k6-2, k6-3,
 // TUNE_X86-SAME: athlon, athlon-tbird, athlon-xp, athlon-mp, athlon-4, k8, athlon64,
 // TUNE_X86-SAME: athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10,
 // TUNE_X86-SAME: barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2,
 // TUNE_X86-SAME: x86-64, geode
 
 // RUN: not %clang_cc1 -triple x86_64--- -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE_X86_64
 // TUNE_X86_64: error: unknown target CPU 'not-a-cpu'
 // TUNE_X86_64: note: valid target CPU values are: i386, i486, winchip-c6, winchip2, c3,
 // TUNE_X86_64-SAME: i586, pentium, pentium-mmx, pentiumpro, i686, pentium2, pentium3,
 // TUNE_X86_64-SAME: pentium3m, pentium-m, c3-2, yonah, pentium4, pentium4m, prescott,
 // TUNE_X86_64-SAME: nocona, core2, penryn, bonnell, atom, silvermont, slm, goldmont, goldmont-plus, tremont,
 // TUNE_X86_64-SAME: nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge,
 // TUNE_X86_64-SAME: core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512,
-// TUNE_X86_64-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, icelake-server, tigerlake, knl, knm, lakemont, k6, k6-2, k6-3,
+// TUNE_X86_64-SAME: skx, cascadelake, cooperlake, cannonlake, icelake-client, icelake-server, tigerlake, sapphirerapids, knl, knm, lakemont, k6, k6-2, k6-3,
 // TUNE_X86_64-SAME: athlon, athlon-tbird, athlon-xp, athlon-mp, athlon-4, k8, athlon64,
 // TUNE_X86_64-SAME: athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10,
 // TUNE_X86_64-SAME: barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2,
 // TUNE_X86_64-SAME: x86-64, geode
 
 // RUN: not %clang_cc1 -triple nvptx--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix NVPTX
 // NVPTX: error: unknown target CPU 'not-a-cpu'
 // NVPTX: note: valid target CPU values are: sm_20, sm_21, sm_30, sm_32, sm_35,

clang/test/Preprocessor/predefined-arch-macros.c

 // CHECK_TGL_M64: #define __amd64 1
 // CHECK_TGL_M64: #define __amd64__ 1
 // CHECK_TGL_M64: #define __corei7 1
 // CHECK_TGL_M64: #define __corei7__ 1
 // CHECK_TGL_M64: #define __tune_corei7__ 1
 // CHECK_TGL_M64: #define __x86_64 1
 // CHECK_TGL_M64: #define __x86_64__ 1
 
+// RUN: %clang -march=sapphirerapids -m32 -E -dM %s -o - 2>&1 \
+// RUN:     -target i386-unknown-linux \
+// RUN:   | FileCheck -match-full-lines %s -check-prefix=CHECK_SPR_M32
+// CHECK_SPR_M32: #define __AES__ 1
+// CHECK_SPR_M32: #define __AMXBF16__ 1
+// CHECK_SPR_M32: #define __AMXINT8__ 1
+// CHECK_SPR_M32: #define __AMXTILE__ 1
+// CHECK_SPR_M32: #define __AVX2__ 1
+// CHECK_SPR_M32: #define __AVX512BF16__ 1
+// CHECK_SPR_M32: #define __AVX512BITALG__ 1
+// CHECK_SPR_M32: #define __AVX512BW__ 1
+// CHECK_SPR_M32: #define __AVX512CD__ 1
+// CHECK_SPR_M32: #define __AVX512DQ__ 1
+// CHECK_SPR_M32: #define __AVX512F__ 1
+// CHECK_SPR_M32: #define __AVX512IFMA__ 1
+// CHECK_SPR_M32: #define __AVX512VBMI2__ 1
+// CHECK_SPR_M32: #define __AVX512VBMI__ 1
+// CHECK_SPR_M32: #define __AVX512VL__ 1
+// CHECK_SPR_M32: #define __AVX512VNNI__ 1
+// CHECK_SPR_M32: #define __AVX512VPOPCNTDQ__ 1
+// CHECK_SPR_M32: #define __AVX__ 1
+// CHECK_SPR_M32: #define __BMI2__ 1
+// CHECK_SPR_M32: #define __BMI__ 1
+// CHECK_SPR_M32: #define __CLDEMOTE__ 1
+// CHECK_SPR_M32: #define __CLFLUSHOPT__ 1
+// CHECK_SPR_M32: #define __CLWB__ 1
+// CHECK_SPR_M32: #define __ENQCMD__ 1
+// CHECK_SPR_M32: #define __F16C__ 1
+// CHECK_SPR_M32: #define __FMA__ 1
+// CHECK_SPR_M32: #define __GFNI__ 1
+// CHECK_SPR_M32: #define __INVPCID__ 1
+// CHECK_SPR_M32: #define __LZCNT__ 1
+// CHECK_SPR_M32: #define __MMX__ 1
+// CHECK_SPR_M32: #define __MOVBE__ 1
+// CHECK_SPR_M32: #define __PCLMUL__ 1
+// CHECK_SPR_M32: #define __PCONFIG__ 1
+// CHECK_SPR_M32: #define __PKU__ 1
+// CHECK_SPR_M32: #define __POPCNT__ 1
+// CHECK_SPR_M32: #define __PRFCHW__ 1
+// CHECK_SPR_M32: #define __PTWRITE__ 1
+// CHECK_SPR_M32: #define __RDPID__ 1
+// CHECK_SPR_M32: #define __RDRND__ 1
+// CHECK_SPR_M32: #define __RDSEED__ 1
+// CHECK_SPR_M32: #define __SERIALIZE__ 1
+// CHECK_SPR_M32: #define __SGX__ 1
+// CHECK_SPR_M32: #define __SHA__ 1
+// CHECK_SPR_M32: #define __SHSTK__ 1
+// CHECK_SPR_M32: #define __SSE2__ 1
+// CHECK_SPR_M32: #define __SSE3__ 1
+// CHECK_SPR_M32: #define __SSE4_1__ 1
+// CHECK_SPR_M32: #define __SSE4_2__ 1
+// CHECK_SPR_M32: #define __SSE__ 1
+// CHECK_SPR_M32: #define __SSSE3__ 1
+// CHECK_SPR_M32: #define __TSXLDTRK__ 1
+// CHECK_SPR_M32: #define __VAES__ 1
+// CHECK_SPR_M32: #define __VPCLMULQDQ__ 1
+// CHECK_SPR_M32: #define __WAITPKG__ 1
+// CHECK_SPR_M32: #define __WBNOINVD__ 1
+// CHECK_SPR_M32: #define __XSAVEC__ 1
+// CHECK_SPR_M32: #define __XSAVEOPT__ 1
+// CHECK_SPR_M32: #define __XSAVES__ 1
+// CHECK_SPR_M32: #define __XSAVE__ 1
+// CHECK_SPR_M32: #define __corei7 1
+// CHECK_SPR_M32: #define __corei7__ 1
+// CHECK_SPR_M32: #define __i386 1
+// CHECK_SPR_M32: #define __i386__ 1
+// CHECK_SPR_M32: #define __tune_corei7__ 1
+// CHECK_SPR_M32: #define i386 1
+
+// RUN: %clang -march=sapphirerapids -m64 -E -dM %s -o - 2>&1 \
+// RUN:     -target i386-unknown-linux \
+// RUN:   | FileCheck -match-full-lines %s -check-prefix=CHECK_SPR_M64
+// CHECK_SPR_M64: #define __AES__ 1
+// CHECK_SPR_M64: #define __AMXBF16__ 1
+// CHECK_SPR_M64: #define __AMXINT8__ 1
+// CHECK_SPR_M64: #define __AMXTILE__ 1
+// CHECK_SPR_M64: #define __AVX2__ 1
+// CHECK_SPR_M64: #define __AVX512BF16__ 1
+// CHECK_SPR_M64: #define __AVX512BITALG__ 1
+// CHECK_SPR_M64: #define __AVX512BW__ 1
+// CHECK_SPR_M64: #define __AVX512CD__ 1
+// CHECK_SPR_M64: #define __AVX512DQ__ 1
+// CHECK_SPR_M64: #define __AVX512F__ 1
+// CHECK_SPR_M64: #define __AVX512IFMA__ 1
+// CHECK_SPR_M64: #define __AVX512VBMI2__ 1
+// CHECK_SPR_M64: #define __AVX512VBMI__ 1
+// CHECK_SPR_M64: #define __AVX512VL__ 1
+// CHECK_SPR_M64: #define __AVX512VNNI__ 1
+// CHECK_SPR_M64: #define __AVX512VPOPCNTDQ__ 1
+// CHECK_SPR_M64: #define __AVX__ 1
+// CHECK_SPR_M64: #define __BMI2__ 1
+// CHECK_SPR_M64: #define __BMI__ 1
+// CHECK_SPR_M64: #define __CLDEMOTE__ 1
+// CHECK_SPR_M64: #define __CLFLUSHOPT__ 1
+// CHECK_SPR_M64: #define __CLWB__ 1
+// CHECK_SPR_M64: #define __ENQCMD__ 1
+// CHECK_SPR_M64: #define __F16C__ 1
+// CHECK_SPR_M64: #define __FMA__ 1
+// CHECK_SPR_M64: #define __GFNI__ 1
+// CHECK_SPR_M64: #define __INVPCID__ 1
+// CHECK_SPR_M64: #define __LZCNT__ 1
+// CHECK_SPR_M64: #define __MMX__ 1
+// CHECK_SPR_M64: #define __MOVBE__ 1
+// CHECK_SPR_M64: #define __PCLMUL__ 1
+// CHECK_SPR_M64: #define __PCONFIG__ 1
+// CHECK_SPR_M64: #define __PKU__ 1
+// CHECK_SPR_M64: #define __POPCNT__ 1
+// CHECK_SPR_M64: #define __PRFCHW__ 1
+// CHECK_SPR_M64: #define __PTWRITE__ 1
+// CHECK_SPR_M64: #define __RDPID__ 1
+// CHECK_SPR_M64: #define __RDRND__ 1
+// CHECK_SPR_M64: #define __RDSEED__ 1
+// CHECK_SPR_M64: #define __SERIALIZE__ 1
+// CHECK_SPR_M64: #define __SGX__ 1
+// CHECK_SPR_M64: #define __SHA__ 1
+// CHECK_SPR_M64: #define __SHSTK__ 1
+// CHECK_SPR_M64: #define __SSE2__ 1
+// CHECK_SPR_M64: #define __SSE3__ 1
+// CHECK_SPR_M64: #define __SSE4_1__ 1
+// CHECK_SPR_M64: #define __SSE4_2__ 1
+// CHECK_SPR_M64: #define __SSE__ 1
+// CHECK_SPR_M64: #define __SSSE3__ 1
+// CHECK_SPR_M64: #define __TSXLDTRK__ 1
+// CHECK_SPR_M64: #define __VAES__ 1
+// CHECK_SPR_M64: #define __VPCLMULQDQ__ 1
+// CHECK_SPR_M64: #define __WAITPKG__ 1
+// CHECK_SPR_M64: #define __WBNOINVD__ 1
+// CHECK_SPR_M64: #define __XSAVEC__ 1
+// CHECK_SPR_M64: #define __XSAVEOPT__ 1
+// CHECK_SPR_M64: #define __XSAVES__ 1
+// CHECK_SPR_M64: #define __XSAVE__ 1
+// CHECK_SPR_M64: #define __amd64 1
+// CHECK_SPR_M64: #define __amd64__ 1
+// CHECK_SPR_M64: #define __corei7 1
+// CHECK_SPR_M64: #define __corei7__ 1
+// CHECK_SPR_M64: #define __tune_corei7__ 1
+// CHECK_SPR_M64: #define __x86_64 1
+// CHECK_SPR_M64: #define __x86_64__ 1
+
 // RUN: %clang -march=atom -m32 -E -dM %s -o - 2>&1 \
 // RUN:     -target i386-unknown-linux \
 // RUN:   | FileCheck -match-full-lines %s -check-prefix=CHECK_ATOM_M32
 // CHECK_ATOM_M32: #define __MMX__ 1
 // CHECK_ATOM_M32: #define __MOVBE__ 1
 // CHECK_ATOM_M32: #define __SSE2__ 1
 // CHECK_ATOM_M32: #define __SSE3__ 1
 // CHECK_ATOM_M32: #define __SSE__ 1

compiler-rt/lib/builtins/cpu_model.c

enum ProcessorSubtypes {
   INTEL_COREI7_SKYLAKE_AVX512,
   INTEL_COREI7_CANNONLAKE,
   INTEL_COREI7_ICELAKE_CLIENT,
   INTEL_COREI7_ICELAKE_SERVER,
   AMDFAM17H_ZNVER2,
   INTEL_COREI7_CASCADELAKE,
   INTEL_COREI7_TIGERLAKE,
   INTEL_COREI7_COOPERLAKE,
+  INTEL_COREI7_SAPPHIRERAPIDS,
   CPU_SUBTYPE_MAX
 };
 
 enum ProcessorFeatures {
   FEATURE_CMOV = 0,
   FEATURE_MMX,
   FEATURE_POPCNT,
   FEATURE_SSE,
case 6:
     // Icelake Xeon:
     case 0x6a:
     case 0x6c:
       CPU = "icelake-server";
       *Type = INTEL_COREI7;
       *Subtype = INTEL_COREI7_ICELAKE_SERVER;
       break;
 
+    // Sapphire Rapids:
+    case 0x8f:
+      CPU = "sapphirerapids";
+      *Type = INTEL_COREI7;
+      *Subtype = INTEL_COREI7_SAPPHIRERAPIDS;
+      break;
+
     case 0x1c: // Most 45 nm Intel Atom processors
     case 0x26: // 45 nm Atom Lincroft
     case 0x27: // 32 nm Atom Medfield
     case 0x35: // 32 nm Atom Midview
     case 0x36: // 32 nm Atom Midview
       CPU = "bonnell";
       *Type = INTEL_BONNELL;
       break;

llvm/include/llvm/Support/X86TargetParser.h

enum CPUKind {
   CK_SkylakeClient,
   CK_SkylakeServer,
   CK_Cascadelake,
   CK_Cooperlake,
   CK_Cannonlake,
   CK_IcelakeClient,
   CK_IcelakeServer,
   CK_Tigerlake,
+  CK_SapphireRapids,
   CK_KNL,
   CK_KNM,
   CK_Lakemont,
   CK_K6,
   CK_K6_2,
   CK_K6_3,
   CK_Athlon,
   CK_AthlonXP,

llvm/include/llvm/Support/X86TargetParser.def

 X86_CPU_SUBTYPE(INTEL_COREI7_SKYLAKE_AVX512, "skylake-avx512")
 X86_CPU_SUBTYPE(INTEL_COREI7_CANNONLAKE,     "cannonlake")
 X86_CPU_SUBTYPE(INTEL_COREI7_ICELAKE_CLIENT, "icelake-client")
 X86_CPU_SUBTYPE(INTEL_COREI7_ICELAKE_SERVER, "icelake-server")
 X86_CPU_SUBTYPE(AMDFAM17H_ZNVER2,            "znver2")
 X86_CPU_SUBTYPE(INTEL_COREI7_CASCADELAKE,    "cascadelake")
 X86_CPU_SUBTYPE(INTEL_COREI7_TIGERLAKE,      "tigerlake")
 X86_CPU_SUBTYPE(INTEL_COREI7_COOPERLAKE,     "cooperlake")
+X86_CPU_SUBTYPE(INTEL_COREI7_SAPPHIRERAPIDS, "sapphirerapids")
 #undef X86_CPU_SUBTYPE
 
 
 // This macro is used for cpu types present in compiler-rt/libgcc.
 #ifndef X86_FEATURE_COMPAT
 #define X86_FEATURE_COMPAT(ENUM, STR) X86_FEATURE(ENUM, STR)
 #endif
 

llvm/lib/Support/Host.cpp

case 6:
     // Icelake Xeon:
     case 0x6a:
     case 0x6c:
       CPU = "icelake-server";
       *Type = X86::INTEL_COREI7;
       *Subtype = X86::INTEL_COREI7_ICELAKE_SERVER;
       break;
 
+    // Sapphire Rapids:
+    case 0x8f:
+      CPU = "sapphirerapids";
+      *Type = X86::INTEL_COREI7;
+      *Subtype = X86::INTEL_COREI7_SAPPHIRERAPIDS;
+      break;
+
     case 0x1c: // Most 45 nm Intel Atom processors
     case 0x26: // 45 nm Atom Lincroft
     case 0x27: // 32 nm Atom Medfield
     case 0x35: // 32 nm Atom Midview
     case 0x36: // 32 nm Atom Midview
       CPU = "bonnell";
       *Type = X86::INTEL_BONNELL;
       break;

llvm/lib/Support/X86TargetParser.cpp

static constexpr FeatureBitset FeaturesICLClient =
     FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 |
     FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureCLWB | FeatureGFNI |
     FeatureRDPID | FeatureVAES | FeatureVPCLMULQDQ;
 static constexpr FeatureBitset FeaturesICLServer =
     FeaturesICLClient | FeaturePCONFIG | FeatureWBNOINVD;
 static constexpr FeatureBitset FeaturesTigerlake =
     FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B |
     FeatureMOVDIRI | FeatureSHSTK;
+static constexpr FeatureBitset FeaturesSapphireRapids =
+    FeaturesICLServer | FeatureAMX_TILE | FeatureAMX_INT8 | FeatureAMX_BF16 |
+    FeatureAVX512BF16 | FeatureAVX512VP2INTERSECT | FeatureCLDEMOTE | FeatureENQCMD |
+    FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE | FeatureSERIALIZE |
+    FeatureSHSTK | FeatureTSXLDTRK | FeatureWAITPKG;
 
 // Intel Atom processors.
 // Bonnell has feature parity with Core2 and adds MOVBE.
 static constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE;
 // Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND.
 static constexpr FeatureBitset FeaturesSilvermont =
     FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND;
 static constexpr FeatureBitset FeaturesGoldmont =
static constexpr ProcInfo Processors[] = {
   // Cannonlake client microarchitecture based processors.
   { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake },
   // Icelake client microarchitecture based processors.
   { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient },
   // Icelake server microarchitecture based processors.
   { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer },
   // Tigerlake microarchitecture based processors.
   { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake },
+  // Sapphire Rapids microarchitecture based processors.
+  { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512VP2INTERSECT, FeaturesSapphireRapids },
   // Knights Landing processor.
   { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL },
   // Knights Mill processor.
   { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM },
   // Lakemont microarchitecture based processors.
   { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B },
   // K6 architecture processors.
   { {"k6"}, CK_K6, ~0U, FeaturesK6 },

llvm/lib/Target/X86/X86.td

def ProcessorFeatures {
   list<SubtargetFeature> TGLAdditionalFeatures = [FeatureVP2INTERSECT,
                                                   FeatureMOVDIRI,
                                                   FeatureMOVDIR64B,
                                                   FeatureSHSTK];
   list<SubtargetFeature> TGLTuning = CNLTuning;
   list<SubtargetFeature> TGLFeatures =
     !listconcat(ICLFeatures, TGLAdditionalFeatures );
 
+  //Sapphirerapids
+  list<SubtargetFeature> SPRAdditionalFeatures = [FeatureAMXTILE,
+                                                  FeatureAMXINT8,
+                                                  FeatureAMXBF16,
+                                                  FeatureBF16,
+                                                  FeatureSERIALIZE,
+                                                  FeatureCLDEMOTE,
+                                                  FeatureWAITPKG,
+                                                  FeaturePTWRITE,
+                                                  FeatureTSXLDTRK,
+                                                  FeatureENQCMD,
+                                                  FeatureSHSTK,
+                                                  FeatureVP2INTERSECT,
+                                                  FeatureMOVDIRI,
+                                                  FeatureMOVDIR64B];
+  list<SubtargetFeature> SPRTuning = ICXTuning;
+  list<SubtargetFeature> SPRFeatures =
+    !listconcat(ICXFeatures, SPRAdditionalFeatures);
+
   // Atom
   list<SubtargetFeature> AtomFeatures = [FeatureX87,
                                          FeatureCMPXCHG8B,
                                          FeatureCMOV,
                                          FeatureMMX,
                                          FeatureSSSE3,
                                          FeatureFXSR,
                                          FeatureNOPL,

 def : ProcModel<"cannonlake", SkylakeServerModel,
                 ProcessorFeatures.CNLFeatures, ProcessorFeatures.CNLTuning>;
 def : ProcModel<"icelake-client", SkylakeServerModel,
                 ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>;
 def : ProcModel<"icelake-server", SkylakeServerModel,
                 ProcessorFeatures.ICXFeatures, ProcessorFeatures.ICXTuning>;
 def : ProcModel<"tigerlake", SkylakeServerModel,
                 ProcessorFeatures.TGLFeatures, ProcessorFeatures.TGLTuning>;
+def : ProcModel<"sapphirerapids", SkylakeServerModel,
+                ProcessorFeatures.SPRFeatures, ProcessorFeatures.SPRTuning>;
 
 // AMD CPUs.
 
 def : Proc<"k6",   [FeatureX87, FeatureCMPXCHG8B, FeatureMMX],
                    [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
 def : Proc<"k6-2", [FeatureX87, FeatureCMPXCHG8B, Feature3DNow],
                    [FeatureSlowUAMem16, FeatureInsertVZEROUPPER]>;
 def : Proc<"k6-3", [FeatureX87, FeatureCMPXCHG8B, Feature3DNow],

llvm/test/CodeGen/X86/cpus-intel.ll

 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=skylake-avx512 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=skx 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=cascadelake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=cooperlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=cannonlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=icelake-client 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=icelake-server 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=tigerlake 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
+; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=sapphirerapids 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=atom 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=bonnell 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=silvermont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=slm 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=goldmont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=goldmont-plus 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=tremont 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=knl 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 ; RUN: llc < %s -o /dev/null -mtriple=x86_64-unknown-unknown -mcpu=knm 2>&1 | FileCheck %s --check-prefix=CHECK-NO-ERROR --allow-empty
 
 define void @foo() {
   ret void
 }